1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2017 The FreeBSD Foundation
5 *
6 * This software was developed by Landon Fuller under sponsorship from
7 * the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/bus.h>
35 #include <sys/gpio.h>
36 #include <sys/limits.h>
37 #include <sys/module.h>
38
39 #include <machine/_inttypes.h>
40 #include <machine/bus.h>
41 #include <sys/rman.h>
42 #include <machine/resource.h>
43
44 #include <dev/bhnd/bhnd.h>
45 #include <dev/gpio/gpiobusvar.h>
46
47 #include "gpio_if.h"
48
49 #include "bhnd_nvram_map.h"
50
51 #include "chipcreg.h"
52 #include "chipc_gpiovar.h"
53
54 /*
55 * ChipCommon GPIO driver
56 */
57
58 static int chipc_gpio_check_flags(
59 struct chipc_gpio_softc *sc,
60 uint32_t pin_num, uint32_t flags,
61 chipc_gpio_pin_mode *mode);
62 static int chipc_gpio_pin_update(
63 struct chipc_gpio_softc *sc,
64 struct chipc_gpio_update *update,
65 uint32_t pin_num, uint32_t flags);
66 static int chipc_gpio_commit_update(
67 struct chipc_gpio_softc *sc,
68 struct chipc_gpio_update *update);
69 static chipc_gpio_pin_mode chipc_gpio_pin_get_mode(
70 struct chipc_gpio_softc *sc,
71 uint32_t pin_num);
72
73 /* Debugging flags */
74 static u_long chipc_gpio_debug = 0;
75 TUNABLE_ULONG("hw.bhnd_chipc.gpio_debug", &chipc_gpio_debug);
76
77 enum {
78 /** Allow userspace GPIO access on bridged network (e.g. wi-fi)
79 * adapters */
80 CC_GPIO_DEBUG_ADAPTER_GPIOC = 1 << 0,
81 };
82
83 #define CC_GPIO_DEBUG(_type) (CC_GPIO_DEBUG_ ## _type & chipc_gpio_debug)
84
85 static struct bhnd_device_quirk chipc_gpio_quirks[];
86
87 /* Supported parent core device identifiers */
88 static const struct bhnd_device chipc_gpio_devices[] = {
89 BHND_DEVICE(BCM, CC, "Broadcom ChipCommon GPIO", chipc_gpio_quirks),
90 BHND_DEVICE_END
91 };
92
93 /* Device quirks table */
94 static struct bhnd_device_quirk chipc_gpio_quirks[] = {
95 BHND_CORE_QUIRK (HWREV_LTE(10), CC_GPIO_QUIRK_NO_EVENTS),
96 BHND_CORE_QUIRK (HWREV_LTE(15), CC_GPIO_QUIRK_NO_DCTIMER),
97 BHND_CORE_QUIRK (HWREV_LTE(19), CC_GPIO_QUIRK_NO_PULLUPDOWN),
98
99 BHND_DEVICE_QUIRK_END
100 };
101
102 static int
chipc_gpio_probe(device_t dev)103 chipc_gpio_probe(device_t dev)
104 {
105 const struct bhnd_device *id;
106 device_t chipc;
107
108 /* Look for compatible chipc parent */
109 chipc = device_get_parent(dev);
110 id = bhnd_device_lookup(chipc, chipc_gpio_devices,
111 sizeof(chipc_gpio_devices[0]));
112 if (id == NULL)
113 return (ENXIO);
114
115 device_set_desc(dev, id->desc);
116 return (BUS_PROBE_NOWILDCARD);
117 }
118
119 static int
chipc_gpio_attach(device_t dev)120 chipc_gpio_attach(device_t dev)
121 {
122 struct chipc_gpio_softc *sc;
123 device_t chipc;
124 int error;
125
126 chipc = device_get_parent(dev);
127
128 sc = device_get_softc(dev);
129 sc->dev = dev;
130 sc->quirks = bhnd_device_quirks(chipc, chipc_gpio_devices,
131 sizeof(chipc_gpio_devices[0]));
132
133 /* If this is a bridged wi-fi adapter, we don't want to support
134 * userspace requests via gpioc(4) */
135 if (bhnd_get_attach_type(chipc) == BHND_ATTACH_ADAPTER) {
136 if (!CC_GPIO_DEBUG(ADAPTER_GPIOC))
137 sc->quirks |= CC_GPIO_QUIRK_NO_GPIOC;
138 }
139
140 CC_GPIO_LOCK_INIT(sc);
141
142 sc->mem_rid = 0;
143 sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
144 RF_ACTIVE|RF_SHAREABLE);
145 if (sc->mem_res == NULL) {
146 device_printf(dev, "failed to allocate chipcommon registers\n");
147 error = ENXIO;
148 goto failed;
149 }
150
151 /*
152 * If hardware 'pulsate' support is available, set the timer duty-cycle
153 * to either the NVRAM 'leddc' value if available, or the default duty
154 * cycle.
155 */
156 if (!CC_GPIO_QUIRK(sc, NO_DCTIMER)) {
157 uint32_t dctimerval;
158
159 error = bhnd_nvram_getvar_uint32(chipc, BHND_NVAR_LEDDC,
160 &dctimerval);
161 if (error == ENOENT) {
162 /* Fall back on default duty cycle */
163 dctimerval = CHIPC_GPIOTIMERVAL_DEFAULT;
164 } else if (error) {
165 device_printf(dev, "error reading %s from NVRAM: %d\n",
166 BHND_NVAR_LEDDC, error);
167 goto failed;
168 }
169
170 CC_GPIO_WR4(sc, CHIPC_GPIOTIMERVAL, dctimerval);
171 }
172
173 /* Attach gpioc/gpiobus */
174 if (CC_GPIO_QUIRK(sc, NO_GPIOC)) {
175 sc->gpiobus = NULL;
176 } else {
177 if ((sc->gpiobus = gpiobus_attach_bus(dev)) == NULL) {
178 device_printf(dev, "failed to attach gpiobus\n");
179 error = ENXIO;
180 goto failed;
181 }
182 }
183
184 /* Register as the bus GPIO provider */
185 if ((error = bhnd_register_provider(dev, BHND_SERVICE_GPIO))) {
186 device_printf(dev, "failed to register gpio with bus: %d\n",
187 error);
188 goto failed;
189 }
190
191 return (0);
192
193 failed:
194 device_delete_children(dev);
195
196 if (sc->mem_res != NULL) {
197 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
198 sc->mem_res);
199 }
200
201 CC_GPIO_LOCK_DESTROY(sc);
202
203 return (error);
204 }
205
206 static int
chipc_gpio_detach(device_t dev)207 chipc_gpio_detach(device_t dev)
208 {
209 struct chipc_gpio_softc *sc;
210 int error;
211
212 sc = device_get_softc(dev);
213
214 if ((error = bus_generic_detach(dev)))
215 return (error);
216
217 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY)))
218 return (error);
219
220 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
221 CC_GPIO_LOCK_DESTROY(sc);
222
223 return (0);
224 }
225
226 static device_t
chipc_gpio_get_bus(device_t dev)227 chipc_gpio_get_bus(device_t dev)
228 {
229 struct chipc_gpio_softc *sc = device_get_softc(dev);
230
231 return (sc->gpiobus);
232 }
233
234 static int
chipc_gpio_pin_max(device_t dev,int * maxpin)235 chipc_gpio_pin_max(device_t dev, int *maxpin)
236 {
237 *maxpin = CC_GPIO_NPINS-1;
238 return (0);
239 }
240
241 static int
chipc_gpio_pin_set(device_t dev,uint32_t pin_num,uint32_t pin_value)242 chipc_gpio_pin_set(device_t dev, uint32_t pin_num, uint32_t pin_value)
243 {
244 struct chipc_gpio_softc *sc;
245 bool pin_high;
246 int error;
247
248 sc = device_get_softc(dev);
249 error = 0;
250
251 if (!CC_GPIO_VALID_PIN(pin_num))
252 return (EINVAL);
253
254 switch (pin_value) {
255 case GPIO_PIN_HIGH:
256 pin_high = true;
257 break;
258 case GPIO_PIN_LOW:
259 pin_high = false;
260 break;
261 default:
262 return (EINVAL);
263 }
264
265 CC_GPIO_LOCK(sc);
266
267 switch (chipc_gpio_pin_get_mode(sc, pin_num)) {
268 case CC_GPIO_PIN_INPUT:
269 case CC_GPIO_PIN_TRISTATE:
270 error = ENODEV;
271 break;
272
273 case CC_GPIO_PIN_OUTPUT:
274 CC_GPIO_WRFLAG(sc, pin_num, GPIOOUT, pin_high);
275 break;
276 }
277
278 CC_GPIO_UNLOCK(sc);
279
280 return (error);
281 }
282
283 static int
chipc_gpio_pin_get(device_t dev,uint32_t pin_num,uint32_t * pin_value)284 chipc_gpio_pin_get(device_t dev, uint32_t pin_num, uint32_t *pin_value)
285 {
286 struct chipc_gpio_softc *sc;
287 bool pin_high;
288
289 if (!CC_GPIO_VALID_PIN(pin_num))
290 return (EINVAL);
291
292 sc = device_get_softc(dev);
293 pin_high = false;
294
295 CC_GPIO_LOCK(sc);
296
297 switch (chipc_gpio_pin_get_mode(sc, pin_num)) {
298 case CC_GPIO_PIN_INPUT:
299 pin_high = CC_GPIO_RDFLAG(sc, pin_num, GPIOIN);
300 break;
301
302 case CC_GPIO_PIN_OUTPUT:
303 pin_high = CC_GPIO_RDFLAG(sc, pin_num, GPIOOUT);
304 break;
305
306 case CC_GPIO_PIN_TRISTATE:
307 pin_high = false;
308 break;
309 }
310
311 CC_GPIO_UNLOCK(sc);
312
313 *pin_value = pin_high ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
314
315 return (0);
316 }
317
318 static int
chipc_gpio_pin_toggle(device_t dev,uint32_t pin_num)319 chipc_gpio_pin_toggle(device_t dev, uint32_t pin_num)
320 {
321 struct chipc_gpio_softc *sc;
322 bool pin_high;
323 int error;
324
325 if (!CC_GPIO_VALID_PIN(pin_num))
326 return (EINVAL);
327
328 sc = device_get_softc(dev);
329 error = 0;
330
331 CC_GPIO_LOCK(sc);
332
333 switch (chipc_gpio_pin_get_mode(sc, pin_num)) {
334 case CC_GPIO_PIN_INPUT:
335 case CC_GPIO_PIN_TRISTATE:
336 error = ENODEV;
337 break;
338
339 case CC_GPIO_PIN_OUTPUT:
340 pin_high = CC_GPIO_RDFLAG(sc, pin_num, GPIOOUT);
341 CC_GPIO_WRFLAG(sc, pin_num, GPIOOUT, !pin_high);
342 break;
343 }
344
345 CC_GPIO_UNLOCK(sc);
346
347 return (error);
348 }
349
350 static int
chipc_gpio_pin_getcaps(device_t dev,uint32_t pin_num,uint32_t * caps)351 chipc_gpio_pin_getcaps(device_t dev, uint32_t pin_num, uint32_t *caps)
352 {
353 struct chipc_gpio_softc *sc = device_get_softc(dev);
354
355 if (!CC_GPIO_VALID_PIN(pin_num))
356 return (EINVAL);
357
358 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
359
360 if (!CC_GPIO_QUIRK(sc, NO_PULLUPDOWN))
361 *caps |= (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN);
362
363 if (!CC_GPIO_QUIRK(sc, NO_DCTIMER))
364 *caps |= GPIO_PIN_PULSATE;
365
366 return (0);
367 }
368
369 static int
chipc_gpio_pin_getflags(device_t dev,uint32_t pin_num,uint32_t * flags)370 chipc_gpio_pin_getflags(device_t dev, uint32_t pin_num, uint32_t *flags)
371 {
372 struct chipc_gpio_softc *sc = device_get_softc(dev);
373
374 if (!CC_GPIO_VALID_PIN(pin_num))
375 return (EINVAL);
376
377 CC_GPIO_LOCK(sc);
378
379 switch (chipc_gpio_pin_get_mode(sc, pin_num)) {
380 case CC_GPIO_PIN_INPUT:
381 *flags = GPIO_PIN_INPUT;
382
383 if (!CC_GPIO_QUIRK(sc, NO_PULLUPDOWN)) {
384 if (CC_GPIO_RDFLAG(sc, pin_num, GPIOPU)) {
385 *flags |= GPIO_PIN_PULLUP;
386 } else if (CC_GPIO_RDFLAG(sc, pin_num, GPIOPD)) {
387 *flags |= GPIO_PIN_PULLDOWN;
388 }
389 }
390 break;
391
392 case CC_GPIO_PIN_OUTPUT:
393 *flags = GPIO_PIN_OUTPUT;
394
395 if (!CC_GPIO_QUIRK(sc, NO_DCTIMER)) {
396 if (CC_GPIO_RDFLAG(sc, pin_num, GPIOTIMEROUTMASK))
397 *flags |= GPIO_PIN_PULSATE;
398 }
399
400 break;
401
402 case CC_GPIO_PIN_TRISTATE:
403 *flags = GPIO_PIN_TRISTATE|GPIO_PIN_OUTPUT;
404 break;
405 }
406
407 CC_GPIO_UNLOCK(sc);
408
409 return (0);
410 }
411
412 static int
chipc_gpio_pin_getname(device_t dev,uint32_t pin_num,char * name)413 chipc_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name)
414 {
415 int ret;
416
417 if (!CC_GPIO_VALID_PIN(pin_num))
418 return (EINVAL);
419
420 ret = snprintf(name, GPIOMAXNAME, "bhnd_gpio%02" PRIu32, pin_num);
421
422 if (ret < 0)
423 return (ENXIO);
424
425 if (ret >= GPIOMAXNAME)
426 return (ENOMEM);
427
428 return (0);
429 }
430
431 static int
chipc_gpio_pin_setflags(device_t dev,uint32_t pin_num,uint32_t flags)432 chipc_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
433 {
434 struct chipc_gpio_softc *sc;
435 struct chipc_gpio_update upd;
436 int error;
437
438 sc = device_get_softc(dev);
439
440 if (!CC_GPIO_VALID_PIN(pin_num))
441 return (EINVAL);
442
443 /* Produce an update descriptor */
444 memset(&upd, 0, sizeof(upd));
445 if ((error = chipc_gpio_pin_update(sc, &upd, pin_num, flags)))
446 return (error);
447
448 /* Commit the update */
449 CC_GPIO_LOCK(sc);
450 error = chipc_gpio_commit_update(sc, &upd);
451 CC_GPIO_UNLOCK(sc);
452
453 return (error);
454 }
455
456 static int
chipc_gpio_pin_access_32(device_t dev,uint32_t first_pin,uint32_t clear_pins,uint32_t change_pins,uint32_t * orig_pins)457 chipc_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
458 uint32_t change_pins, uint32_t *orig_pins)
459 {
460 struct chipc_gpio_softc *sc;
461 struct chipc_gpio_update upd;
462 uint32_t out, outen, ctrl;
463 uint32_t num_pins;
464 int error;
465
466 sc = device_get_softc(dev);
467
468 if (first_pin >= CC_GPIO_NPINS)
469 return (EINVAL);
470
471 /* Determine the actual number of referenced pins */
472 if (clear_pins == 0 && change_pins == 0) {
473 num_pins = CC_GPIO_NPINS - first_pin;
474 } else {
475 int num_clear_pins, num_change_pins;
476
477 num_clear_pins = flsl((u_long)clear_pins);
478 num_change_pins = flsl((u_long)change_pins);
479 num_pins = MAX(num_clear_pins, num_change_pins);
480 }
481
482 /* Validate the full pin range */
483 if (!CC_GPIO_VALID_PINS(first_pin, num_pins))
484 return (EINVAL);
485
486 /* Produce an update descriptor for all pins, relative to the current
487 * pin state */
488 CC_GPIO_LOCK(sc);
489 memset(&upd, 0, sizeof(upd));
490
491 out = CC_GPIO_RD4(sc, CHIPC_GPIOOUT);
492 outen = CC_GPIO_RD4(sc, CHIPC_GPIOOUTEN);
493 ctrl = CC_GPIO_RD4(sc, CHIPC_GPIOCTRL);
494
495 for (uint32_t i = 0; i < num_pins; i++) {
496 uint32_t pin;
497 bool pin_high;
498
499 pin = first_pin + i;
500
501 /* The pin must be configured for output */
502 if ((outen & (1 << pin)) == 0) {
503 CC_GPIO_UNLOCK(sc);
504 return (EINVAL);
505 }
506
507 /* The pin must not tristated */
508 if ((ctrl & (1 << pin)) != 0) {
509 CC_GPIO_UNLOCK(sc);
510 return (EINVAL);
511 }
512
513 /* Fetch current state */
514 if (out & (1 << pin)) {
515 pin_high = true;
516 } else {
517 pin_high = false;
518 }
519
520 /* Apply clear/toggle request */
521 if (clear_pins & (1 << pin))
522 pin_high = false;
523
524 if (change_pins & (1 << pin))
525 pin_high = !pin_high;
526
527 /* Add to our update descriptor */
528 CC_GPIO_UPDATE(&upd, pin, out, pin_high);
529 }
530
531 /* Commit the update */
532 error = chipc_gpio_commit_update(sc, &upd);
533 CC_GPIO_UNLOCK(sc);
534
535 return (error);
536 }
537
538 static int
chipc_gpio_pin_config_32(device_t dev,uint32_t first_pin,uint32_t num_pins,uint32_t * pin_flags)539 chipc_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
540 uint32_t *pin_flags)
541 {
542 struct chipc_gpio_softc *sc;
543 struct chipc_gpio_update upd;
544 int error;
545
546 sc = device_get_softc(dev);
547
548 if (!CC_GPIO_VALID_PINS(first_pin, num_pins))
549 return (EINVAL);
550
551 /* Produce an update descriptor */
552 memset(&upd, 0, sizeof(upd));
553 for (uint32_t i = 0; i < num_pins; i++) {
554 uint32_t pin, flags;
555
556 pin = first_pin + i;
557 flags = pin_flags[i];
558
559 /* As per the gpio_config_32 API documentation, any pins for
560 * which neither GPIO_PIN_OUTPUT or GPIO_PIN_INPUT are set
561 * should be ignored and left unmodified */
562 if ((flags & (GPIO_PIN_OUTPUT|GPIO_PIN_INPUT)) == 0)
563 continue;
564
565 if ((error = chipc_gpio_pin_update(sc, &upd, pin, flags)))
566 return (error);
567 }
568
569 /* Commit the update */
570 CC_GPIO_LOCK(sc);
571 error = chipc_gpio_commit_update(sc, &upd);
572 CC_GPIO_UNLOCK(sc);
573
574 return (error);
575 }
576
577 /**
578 * Commit a single @p reg register update.
579 */
580 static void
chipc_gpio_commit_reg(struct chipc_gpio_softc * sc,bus_size_t offset,struct chipc_gpio_reg * reg)581 chipc_gpio_commit_reg(struct chipc_gpio_softc *sc, bus_size_t offset,
582 struct chipc_gpio_reg *reg)
583 {
584 uint32_t value;
585
586 CC_GPIO_LOCK_ASSERT(sc, MA_OWNED);
587
588 if (reg->mask == 0)
589 return;
590
591 value = bhnd_bus_read_4(sc->mem_res, offset);
592 value &= ~reg->mask;
593 value |= reg->value;
594
595 bhnd_bus_write_4(sc->mem_res, offset, value);
596 }
597
598 /**
599 * Commit the set of GPIO register updates described by @p update.
600 */
601 static int
chipc_gpio_commit_update(struct chipc_gpio_softc * sc,struct chipc_gpio_update * update)602 chipc_gpio_commit_update(struct chipc_gpio_softc *sc,
603 struct chipc_gpio_update *update)
604 {
605 CC_GPIO_LOCK_ASSERT(sc, MA_OWNED);
606
607 /* Commit pulldown/pullup before potentially disabling an output pin */
608 chipc_gpio_commit_reg(sc, CHIPC_GPIOPD, &update->pulldown);
609 chipc_gpio_commit_reg(sc, CHIPC_GPIOPU, &update->pullup);
610
611 /* Commit output settings before potentially enabling an output pin */
612 chipc_gpio_commit_reg(sc, CHIPC_GPIOTIMEROUTMASK,
613 &update->timeroutmask);
614 chipc_gpio_commit_reg(sc, CHIPC_GPIOOUT, &update->out);
615
616 /* Commit input/output/tristate modes */
617 chipc_gpio_commit_reg(sc, CHIPC_GPIOOUTEN, &update->outen);
618 chipc_gpio_commit_reg(sc, CHIPC_GPIOCTRL, &update->ctrl);
619
620 return (0);
621 }
622
623 /**
624 * Apply the changes described by @p flags for @p pin_num to the given @p update
625 * descriptor.
626 */
627 static int
chipc_gpio_pin_update(struct chipc_gpio_softc * sc,struct chipc_gpio_update * update,uint32_t pin_num,uint32_t flags)628 chipc_gpio_pin_update(struct chipc_gpio_softc *sc,
629 struct chipc_gpio_update *update, uint32_t pin_num, uint32_t flags)
630 {
631 chipc_gpio_pin_mode mode;
632 int error;
633
634 if (!CC_GPIO_VALID_PIN(pin_num))
635 return (EINVAL);
636
637 /* Verify flag compatibility and determine the pin mode */
638 if ((error = chipc_gpio_check_flags(sc, pin_num, flags, &mode)))
639 return (error);
640
641 /* Apply the mode-specific changes */
642 switch (mode) {
643 case CC_GPIO_PIN_INPUT:
644 CC_GPIO_UPDATE(update, pin_num, pullup, false);
645 CC_GPIO_UPDATE(update, pin_num, pulldown, false);
646 CC_GPIO_UPDATE(update, pin_num, out, false);
647 CC_GPIO_UPDATE(update, pin_num, outen, false);
648 CC_GPIO_UPDATE(update, pin_num, timeroutmask, false);
649 CC_GPIO_UPDATE(update, pin_num, ctrl, false);
650
651 if (flags & GPIO_PIN_PULLUP) {
652 CC_GPIO_UPDATE(update, pin_num, pullup, true);
653 } else if (flags & GPIO_PIN_PULLDOWN) {
654 CC_GPIO_UPDATE(update, pin_num, pulldown, true);
655 }
656
657 return (0);
658
659 case CC_GPIO_PIN_OUTPUT:
660 CC_GPIO_UPDATE(update, pin_num, pullup, false);
661 CC_GPIO_UPDATE(update, pin_num, pulldown, false);
662 CC_GPIO_UPDATE(update, pin_num, outen, true);
663 CC_GPIO_UPDATE(update, pin_num, timeroutmask, false);
664 CC_GPIO_UPDATE(update, pin_num, ctrl, false);
665
666 if (flags & GPIO_PIN_PRESET_HIGH) {
667 CC_GPIO_UPDATE(update, pin_num, out, true);
668 } else if (flags & GPIO_PIN_PRESET_LOW) {
669 CC_GPIO_UPDATE(update, pin_num, out, false);
670 }
671
672 if (flags & GPIO_PIN_PULSATE)
673 CC_GPIO_UPDATE(update, pin_num, timeroutmask, true);
674
675 return (0);
676
677 case CC_GPIO_PIN_TRISTATE:
678 CC_GPIO_UPDATE(update, pin_num, pullup, false);
679 CC_GPIO_UPDATE(update, pin_num, pulldown, false);
680 CC_GPIO_UPDATE(update, pin_num, out, false);
681 CC_GPIO_UPDATE(update, pin_num, outen, false);
682 CC_GPIO_UPDATE(update, pin_num, timeroutmask, false);
683 CC_GPIO_UPDATE(update, pin_num, ctrl, true);
684
685 if (flags & GPIO_PIN_OUTPUT)
686 CC_GPIO_UPDATE(update, pin_num, outen, true);
687
688 return (0);
689 }
690
691 device_printf(sc->dev, "unknown pin mode %d\n", mode);
692 return (EINVAL);
693 }
694
695 /**
696 * Verify that @p flags are valid for use with @p pin_num, and on success,
697 * return the pin mode described by @p flags in @p mode.
698 *
699 * @param sc GPIO driver instance state.
700 * @param pin_num The pin number to configure.
701 * @param flags The pin flags to be validated.
702 * @param[out] mode On success, will be populated with the GPIO pin mode
703 * defined by @p flags.
704 *
705 * @retval 0 success
706 * @retval EINVAL if @p flags are invalid.
707 */
708 static int
chipc_gpio_check_flags(struct chipc_gpio_softc * sc,uint32_t pin_num,uint32_t flags,chipc_gpio_pin_mode * mode)709 chipc_gpio_check_flags(struct chipc_gpio_softc *sc, uint32_t pin_num,
710 uint32_t flags, chipc_gpio_pin_mode *mode)
711 {
712 uint32_t mode_flag, input_flag, output_flag;
713
714 CC_GPIO_ASSERT_VALID_PIN(sc, pin_num);
715
716 mode_flag = flags & (GPIO_PIN_OUTPUT | GPIO_PIN_INPUT |
717 GPIO_PIN_TRISTATE);
718 output_flag = flags & (GPIO_PIN_PRESET_HIGH | GPIO_PIN_PRESET_LOW
719 | GPIO_PIN_PULSATE);
720 input_flag = flags & (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN);
721
722 switch (mode_flag) {
723 case GPIO_PIN_OUTPUT:
724 /* No input flag(s) should be set */
725 if (input_flag != 0)
726 return (EINVAL);
727
728 /* Validate our output flag(s) */
729 switch (output_flag) {
730 case GPIO_PIN_PRESET_HIGH:
731 case GPIO_PIN_PRESET_LOW:
732 case (GPIO_PIN_PRESET_HIGH|GPIO_PIN_PULSATE):
733 case (GPIO_PIN_PRESET_LOW|GPIO_PIN_PULSATE):
734 case 0:
735 /* Check for unhandled flags */
736 if ((flags & ~(mode_flag | output_flag)) != 0)
737 return (EINVAL);
738
739 *mode = CC_GPIO_PIN_OUTPUT;
740 return (0);
741
742 default:
743 /* Incompatible output flags */
744 return (EINVAL);
745 }
746
747 case GPIO_PIN_INPUT:
748 /* No output flag(s) should be set */
749 if (output_flag != 0)
750 return (EINVAL);
751
752 /* Validate our input flag(s) */
753 switch (input_flag) {
754 case GPIO_PIN_PULLUP:
755 case GPIO_PIN_PULLDOWN:
756 case 0:
757 /* Check for unhandled flags */
758 if ((flags & ~(mode_flag | input_flag)) != 0)
759 return (EINVAL);
760
761 *mode = CC_GPIO_PIN_INPUT;
762 return (0);
763
764 default:
765 /* Incompatible input flags */
766 return (EINVAL);
767 }
768
769 break;
770
771 case (GPIO_PIN_TRISTATE|GPIO_PIN_OUTPUT):
772 case GPIO_PIN_TRISTATE:
773 /* No input or output flag(s) should be set */
774 if (input_flag != 0 || output_flag != 0)
775 return (EINVAL);
776
777 /* Check for unhandled flags */
778 if ((flags & ~mode_flag) != 0)
779 return (EINVAL);
780
781 *mode = CC_GPIO_PIN_TRISTATE;
782 return (0);
783
784 default:
785 /* Incompatible mode flags */
786 return (EINVAL);
787 }
788 }
789
790 /**
791 * Return the current pin mode for @p pin_num.
792 *
793 * @param sc GPIO driver instance state.
794 * @param pin_num The pin number to query.
795 */
796 static chipc_gpio_pin_mode
chipc_gpio_pin_get_mode(struct chipc_gpio_softc * sc,uint32_t pin_num)797 chipc_gpio_pin_get_mode(struct chipc_gpio_softc *sc, uint32_t pin_num)
798 {
799 CC_GPIO_LOCK_ASSERT(sc, MA_OWNED);
800 CC_GPIO_ASSERT_VALID_PIN(sc, pin_num);
801
802 if (CC_GPIO_RDFLAG(sc, pin_num, GPIOCTRL)) {
803 return (CC_GPIO_PIN_TRISTATE);
804 } else if (CC_GPIO_RDFLAG(sc, pin_num, GPIOOUTEN)) {
805 return (CC_GPIO_PIN_OUTPUT);
806 } else {
807 return (CC_GPIO_PIN_INPUT);
808 }
809 }
810
811 static device_method_t chipc_gpio_methods[] = {
812 /* Device interface */
813 DEVMETHOD(device_probe, chipc_gpio_probe),
814 DEVMETHOD(device_attach, chipc_gpio_attach),
815 DEVMETHOD(device_detach, chipc_gpio_detach),
816
817 /* GPIO interface */
818 DEVMETHOD(gpio_get_bus, chipc_gpio_get_bus),
819 DEVMETHOD(gpio_pin_max, chipc_gpio_pin_max),
820 DEVMETHOD(gpio_pin_getname, chipc_gpio_pin_getname),
821 DEVMETHOD(gpio_pin_getflags, chipc_gpio_pin_getflags),
822 DEVMETHOD(gpio_pin_getcaps, chipc_gpio_pin_getcaps),
823 DEVMETHOD(gpio_pin_setflags, chipc_gpio_pin_setflags),
824 DEVMETHOD(gpio_pin_get, chipc_gpio_pin_get),
825 DEVMETHOD(gpio_pin_set, chipc_gpio_pin_set),
826 DEVMETHOD(gpio_pin_toggle, chipc_gpio_pin_toggle),
827 DEVMETHOD(gpio_pin_access_32, chipc_gpio_pin_access_32),
828 DEVMETHOD(gpio_pin_config_32, chipc_gpio_pin_config_32),
829
830 DEVMETHOD_END
831 };
832
833 static devclass_t gpio_devclass;
834
835 DEFINE_CLASS_0(gpio, chipc_gpio_driver, chipc_gpio_methods, sizeof(struct chipc_gpio_softc));
836 EARLY_DRIVER_MODULE(chipc_gpio, bhnd_chipc, chipc_gpio_driver,
837 gpio_devclass, NULL, NULL, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
838
839 MODULE_DEPEND(chipc_gpio, bhnd, 1, 1, 1);
840 MODULE_DEPEND(chipc_gpio, gpiobus, 1, 1, 1);
841 MODULE_VERSION(chipc_gpio, 1);
842