1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
17 *
18 * NO WARRANTY
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
30 */
31
32 #include <sys/cdefs.h>
33 /*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40 #include "opt_inet.h"
41 #include "opt_ath.h"
42 /*
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
45 *
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
48 */
49 #include "opt_ah.h"
50 #include "opt_wlan.h"
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
55 #include <sys/mbuf.h>
56 #include <sys/malloc.h>
57 #include <sys/lock.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
64 #include <sys/bus.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
68 #include <sys/priv.h>
69 #include <sys/module.h>
70 #include <sys/ktr.h>
71 #include <sys/smp.h> /* for mp_ncpus */
72
73 #include <machine/bus.h>
74
75 #include <net/if.h>
76 #include <net/if_var.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_llc.h>
83
84 #include <net80211/ieee80211_var.h>
85 #include <net80211/ieee80211_regdomain.h>
86 #ifdef IEEE80211_SUPPORT_SUPERG
87 #include <net80211/ieee80211_superg.h>
88 #endif
89 #ifdef IEEE80211_SUPPORT_TDMA
90 #include <net80211/ieee80211_tdma.h>
91 #endif
92
93 #include <net/bpf.h>
94
95 #ifdef INET
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
98 #endif
99
100 #include <dev/ath/if_athvar.h>
101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
102 #include <dev/ath/ath_hal/ah_diagcodes.h>
103
104 #include <dev/ath/if_ath_debug.h>
105 #include <dev/ath/if_ath_misc.h>
106 #include <dev/ath/if_ath_tsf.h>
107 #include <dev/ath/if_ath_tx.h>
108 #include <dev/ath/if_ath_sysctl.h>
109 #include <dev/ath/if_ath_led.h>
110 #include <dev/ath/if_ath_keycache.h>
111 #include <dev/ath/if_ath_rx.h>
112 #include <dev/ath/if_ath_beacon.h>
113 #include <dev/ath/if_athdfs.h>
114 #include <dev/ath/if_ath_descdma.h>
115
116 #ifdef ATH_TX99_DIAG
117 #include <dev/ath/ath_tx99/ath_tx99.h>
118 #endif
119
120 #ifdef ATH_DEBUG_ALQ
121 #include <dev/ath/if_ath_alq.h>
122 #endif
123
124 #include <dev/ath/if_ath_lna_div.h>
125
126 /*
127 * Calculate the receive filter according to the
128 * operating mode and state:
129 *
130 * o always accept unicast, broadcast, and multicast traffic
131 * o accept PHY error frames when hardware doesn't have MIB support
132 * to count and we need them for ANI (sta mode only until recently)
133 * and we are not scanning (ANI is disabled)
134 * NB: older hal's add rx filter bits out of sight and we need to
135 * blindly preserve them
136 * o probe request frames are accepted only when operating in
137 * hostap, adhoc, mesh, or monitor modes
138 * o enable promiscuous mode
139 * - when in monitor mode
140 * - if interface marked PROMISC (assumes bridge setting is filtered)
141 * o accept beacons:
142 * - when operating in station mode for collecting rssi data when
143 * the station is otherwise quiet, or
144 * - when operating in adhoc mode so the 802.11 layer creates
145 * node table entries for peers,
146 * - when scanning
147 * - when doing s/w beacon miss (e.g. for ap+sta)
148 * - when operating in ap mode in 11g to detect overlapping bss that
149 * require protection
150 * - when operating in mesh mode to detect neighbors
151 * o accept control frames:
152 * - when in monitor mode
153 * XXX HT protection for 11n
154 */
155 u_int32_t
ath_calcrxfilter(struct ath_softc * sc)156 ath_calcrxfilter(struct ath_softc *sc)
157 {
158 struct ieee80211com *ic = &sc->sc_ic;
159 u_int32_t rfilt;
160
161 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
162 if (!sc->sc_needmib && !sc->sc_scanning)
163 rfilt |= HAL_RX_FILTER_PHYERR;
164 if (ic->ic_opmode != IEEE80211_M_STA)
165 rfilt |= HAL_RX_FILTER_PROBEREQ;
166 /* XXX ic->ic_monvaps != 0? */
167 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0)
168 rfilt |= HAL_RX_FILTER_PROM;
169
170 /*
171 * Only listen to all beacons if we're scanning.
172 *
173 * Otherwise we only really need to hear beacons from
174 * our own BSSID.
175 *
176 * IBSS? software beacon miss? Just receive all beacons.
177 * We need to hear beacons/probe requests from everyone so
178 * we can merge ibss.
179 */
180 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) {
181 rfilt |= HAL_RX_FILTER_BEACON;
182 } else if (ic->ic_opmode == IEEE80211_M_STA) {
183 if (sc->sc_do_mybeacon && ! sc->sc_scanning) {
184 rfilt |= HAL_RX_FILTER_MYBEACON;
185 } else { /* scanning, non-mybeacon chips */
186 rfilt |= HAL_RX_FILTER_BEACON;
187 }
188 }
189
190 /*
191 * NB: We don't recalculate the rx filter when
192 * ic_protmode changes; otherwise we could do
193 * this only when ic_protmode != NONE.
194 */
195 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
196 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
197 rfilt |= HAL_RX_FILTER_BEACON;
198
199 /*
200 * Enable hardware PS-POLL RX only for hostap mode;
201 * STA mode sends PS-POLL frames but never
202 * receives them.
203 */
204 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL,
205 0, NULL) == HAL_OK &&
206 ic->ic_opmode == IEEE80211_M_HOSTAP)
207 rfilt |= HAL_RX_FILTER_PSPOLL;
208
209 if (sc->sc_nmeshvaps) {
210 rfilt |= HAL_RX_FILTER_BEACON;
211 if (sc->sc_hasbmatch)
212 rfilt |= HAL_RX_FILTER_BSSID;
213 else
214 rfilt |= HAL_RX_FILTER_PROM;
215 }
216 if (ic->ic_opmode == IEEE80211_M_MONITOR)
217 rfilt |= HAL_RX_FILTER_CONTROL;
218
219 /*
220 * Enable RX of compressed BAR frames only when doing
221 * 802.11n. Required for A-MPDU.
222 */
223 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan))
224 rfilt |= HAL_RX_FILTER_COMPBAR;
225
226 /*
227 * Enable radar PHY errors if requested by the
228 * DFS module.
229 */
230 if (sc->sc_dodfs)
231 rfilt |= HAL_RX_FILTER_PHYRADAR;
232
233 /*
234 * Enable spectral PHY errors if requested by the
235 * spectral module.
236 */
237 if (sc->sc_dospectral)
238 rfilt |= HAL_RX_FILTER_PHYRADAR;
239
240 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n",
241 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]);
242 return rfilt;
243 }
244
245 static int
ath_legacy_rxbuf_init(struct ath_softc * sc,struct ath_buf * bf)246 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
247 {
248 struct ath_hal *ah = sc->sc_ah;
249 int error;
250 struct mbuf *m;
251 struct ath_desc *ds;
252
253 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */
254
255 m = bf->bf_m;
256 if (m == NULL) {
257 /*
258 * NB: by assigning a page to the rx dma buffer we
259 * implicitly satisfy the Atheros requirement that
260 * this buffer be cache-line-aligned and sized to be
261 * multiple of the cache line size. Not doing this
262 * causes weird stuff to happen (for the 5210 at least).
263 */
264 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
265 if (m == NULL) {
266 DPRINTF(sc, ATH_DEBUG_ANY,
267 "%s: no mbuf/cluster\n", __func__);
268 sc->sc_stats.ast_rx_nombuf++;
269 return ENOMEM;
270 }
271 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
272
273 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
274 bf->bf_dmamap, m,
275 bf->bf_segs, &bf->bf_nseg,
276 BUS_DMA_NOWAIT);
277 if (error != 0) {
278 DPRINTF(sc, ATH_DEBUG_ANY,
279 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
280 __func__, error);
281 sc->sc_stats.ast_rx_busdma++;
282 m_freem(m);
283 return error;
284 }
285 KASSERT(bf->bf_nseg == 1,
286 ("multi-segment packet; nseg %u", bf->bf_nseg));
287 bf->bf_m = m;
288 }
289 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
290
291 /*
292 * Setup descriptors. For receive we always terminate
293 * the descriptor list with a self-linked entry so we'll
294 * not get overrun under high load (as can happen with a
295 * 5212 when ANI processing enables PHY error frames).
296 *
297 * To insure the last descriptor is self-linked we create
298 * each descriptor as self-linked and add it to the end. As
299 * each additional descriptor is added the previous self-linked
300 * entry is ``fixed'' naturally. This should be safe even
301 * if DMA is happening. When processing RX interrupts we
302 * never remove/process the last, self-linked, entry on the
303 * descriptor list. This insures the hardware always has
304 * someplace to write a new frame.
305 */
306 /*
307 * 11N: we can no longer afford to self link the last descriptor.
308 * MAC acknowledges BA status as long as it copies frames to host
309 * buffer (or rx fifo). This can incorrectly acknowledge packets
310 * to a sender if last desc is self-linked.
311 */
312 ds = bf->bf_desc;
313 if (sc->sc_rxslink)
314 ds->ds_link = bf->bf_daddr; /* link to self */
315 else
316 ds->ds_link = 0; /* terminate the list */
317 ds->ds_data = bf->bf_segs[0].ds_addr;
318 ath_hal_setuprxdesc(ah, ds
319 , m->m_len /* buffer size */
320 , 0
321 );
322
323 if (sc->sc_rxlink != NULL)
324 *sc->sc_rxlink = bf->bf_daddr;
325 sc->sc_rxlink = &ds->ds_link;
326 return 0;
327 }
328
329 /*
330 * Intercept management frames to collect beacon rssi data
331 * and to do ibss merges.
332 */
333 void
ath_recv_mgmt(struct ieee80211_node * ni,struct mbuf * m,int subtype,const struct ieee80211_rx_stats * rxs,int rssi,int nf)334 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
335 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf)
336 {
337 struct ieee80211vap *vap = ni->ni_vap;
338 struct ath_softc *sc = vap->iv_ic->ic_softc;
339 uint64_t tsf_beacon_old, tsf_beacon;
340 uint64_t nexttbtt;
341 int64_t tsf_delta;
342 int32_t tsf_delta_bmiss;
343 int32_t tsf_remainder;
344 uint64_t tsf_beacon_target;
345 int tsf_intval;
346
347 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32;
348 tsf_beacon_old |= le32dec(ni->ni_tstamp.data);
349
350 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10)
351 tsf_intval = 1;
352 if (ni->ni_intval > 0) {
353 tsf_intval = TU_TO_TSF(ni->ni_intval);
354 }
355 #undef TU_TO_TSF
356
357 /*
358 * Call up first so subsequent work can use information
359 * potentially stored in the node (e.g. for ibss merge).
360 */
361 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf);
362 switch (subtype) {
363 case IEEE80211_FC0_SUBTYPE_BEACON:
364 /*
365 * Always update the per-node beacon RSSI if we're hearing
366 * beacons from that node.
367 */
368 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgbrssi, rssi);
369
370 /*
371 * Only do the following processing if it's for
372 * the current BSS.
373 *
374 * In scan and IBSS mode we receive all beacons,
375 * which means we need to filter out stuff
376 * that isn't for us or we'll end up constantly
377 * trying to sync / merge to BSSes that aren't
378 * actually us.
379 */
380 if ((vap->iv_opmode != IEEE80211_M_HOSTAP) &&
381 IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) {
382 /* update rssi statistics for use by the hal */
383 /* XXX unlocked check against vap->iv_bss? */
384 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
385
386 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32;
387 tsf_beacon |= le32dec(ni->ni_tstamp.data);
388
389 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah);
390
391 /*
392 * Let's calculate the delta and remainder, so we can see
393 * if the beacon timer from the AP is varying by more than
394 * a few TU. (Which would be a huge, huge problem.)
395 */
396 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old;
397
398 tsf_delta_bmiss = tsf_delta / tsf_intval;
399
400 /*
401 * If our delta is greater than half the beacon interval,
402 * let's round the bmiss value up to the next beacon
403 * interval. Ie, we're running really, really early
404 * on the next beacon.
405 */
406 if (tsf_delta % tsf_intval > (tsf_intval / 2))
407 tsf_delta_bmiss ++;
408
409 tsf_beacon_target = tsf_beacon_old +
410 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval);
411
412 /*
413 * The remainder using '%' is between 0 .. intval-1.
414 * If we're actually running too fast, then the remainder
415 * will be some large number just under intval-1.
416 * So we need to look at whether we're running
417 * before or after the target beacon interval
418 * and if we are, modify how we do the remainder
419 * calculation.
420 */
421 if (tsf_beacon < tsf_beacon_target) {
422 tsf_remainder =
423 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval));
424 } else {
425 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval;
426 }
427
428 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: %s: old_tsf=%llu (%u), new_tsf=%llu (%u), target_tsf=%llu (%u), delta=%lld, bmiss=%d, remainder=%d\n",
429 __func__,
430 ieee80211_get_vap_ifname(vap),
431 (unsigned long long) tsf_beacon_old,
432 (unsigned int) (tsf_beacon_old >> 10),
433 (unsigned long long) tsf_beacon,
434 (unsigned int ) (tsf_beacon >> 10),
435 (unsigned long long) tsf_beacon_target,
436 (unsigned int) (tsf_beacon_target >> 10),
437 (long long) tsf_delta,
438 tsf_delta_bmiss,
439 tsf_remainder);
440
441 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: %s: ni=%6D bssid=%6D tsf=%llu (%u), nexttbtt=%llu (%u), delta=%d\n",
442 __func__,
443 ieee80211_get_vap_ifname(vap),
444 ni->ni_bssid, ":",
445 vap->iv_bss->ni_bssid, ":",
446 (unsigned long long) tsf_beacon,
447 (unsigned int) (tsf_beacon >> 10),
448 (unsigned long long) nexttbtt,
449 (unsigned int) (nexttbtt >> 10),
450 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval);
451
452 /*
453 * We only do syncbeacon on STA VAPs; not on IBSS;
454 * but don't do it with swbmiss enabled or we
455 * may end up overwriting AP mode beacon config.
456 *
457 * The driver (and net80211) should be smarter about
458 * this..
459 */
460 if (vap->iv_opmode == IEEE80211_M_STA &&
461 sc->sc_syncbeacon &&
462 (!sc->sc_swbmiss) &&
463 ni == vap->iv_bss &&
464 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) {
465 DPRINTF(sc, ATH_DEBUG_BEACON,
466 "%s: syncbeacon=1; syncing\n",
467 __func__);
468 /*
469 * Resync beacon timers using the tsf of the beacon
470 * frame we just received.
471 */
472 ath_beacon_config(sc, vap);
473 sc->sc_syncbeacon = 0;
474 }
475 }
476
477 /* fall thru... */
478 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
479 if (vap->iv_opmode == IEEE80211_M_IBSS &&
480 vap->iv_state == IEEE80211_S_RUN &&
481 ieee80211_ibss_merge_check(ni)) {
482 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
483 uint64_t tsf = ath_extend_tsf(sc, rstamp,
484 ath_hal_gettsf64(sc->sc_ah));
485 /*
486 * Handle ibss merge as needed; check the tsf on the
487 * frame before attempting the merge. The 802.11 spec
488 * says the station should change it's bssid to match
489 * the oldest station with the same ssid, where oldest
490 * is determined by the tsf. Note that hardware
491 * reconfiguration happens through callback to
492 * ath_newstate as the state machine will go from
493 * RUN -> RUN when this happens.
494 */
495 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
496 DPRINTF(sc, ATH_DEBUG_STATE,
497 "ibss merge, rstamp %u tsf %ju "
498 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
499 (uintmax_t)ni->ni_tstamp.tsf);
500 (void) ieee80211_ibss_merge(ni);
501 }
502 }
503 break;
504 }
505 }
506
507 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
508 static void
ath_rx_tap_vendor(struct ath_softc * sc,struct mbuf * m,const struct ath_rx_status * rs,u_int64_t tsf,int16_t nf)509 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m,
510 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
511 {
512
513 /* Fill in the extension bitmap */
514 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER);
515
516 /* Fill in the vendor header */
517 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f;
518 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03;
519 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00;
520
521 /* XXX what should this be? */
522 sc->sc_rx_th.wr_vh.vh_sub_ns = 0;
523 sc->sc_rx_th.wr_vh.vh_skip_len =
524 htole16(sizeof(struct ath_radiotap_vendor_hdr));
525
526 /* General version info */
527 sc->sc_rx_th.wr_v.vh_version = 1;
528
529 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask;
530
531 /* rssi */
532 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0];
533 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1];
534 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2];
535 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0];
536 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1];
537 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2];
538
539 /* evm */
540 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0;
541 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1;
542 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2;
543 /* These are only populated from the AR9300 or later */
544 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3;
545 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4;
546
547 /* direction */
548 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX;
549
550 /* RX rate */
551 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate;
552
553 /* RX flags */
554 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags;
555
556 if (rs->rs_isaggr)
557 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR;
558 if (rs->rs_moreaggr)
559 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR;
560
561 /* phyerr info */
562 if (rs->rs_status & HAL_RXERR_PHY) {
563 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr;
564 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR;
565 } else {
566 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff;
567 }
568 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status;
569 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi;
570 }
571 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
572
573 static void
ath_rx_tap(struct ath_softc * sc,struct mbuf * m,const struct ath_rx_status * rs,u_int64_t tsf,int16_t nf)574 ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
575 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
576 {
577 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
578 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
579 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
580 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
581 const HAL_RATE_TABLE *rt;
582 uint8_t rix;
583
584 rt = sc->sc_currates;
585 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
586 rix = rt->rateCodeToIndex[rs->rs_rate];
587 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
588 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
589
590 /* 802.11 specific flags */
591 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
592 if (rs->rs_status & HAL_RXERR_PHY) {
593 /*
594 * PHY error - make sure the channel flags
595 * reflect the actual channel configuration,
596 * not the received frame.
597 */
598 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan))
599 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
600 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan))
601 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
602 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan))
603 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
604 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
605 struct ieee80211com *ic = &sc->sc_ic;
606
607 if ((rs->rs_flags & HAL_RX_2040) == 0)
608 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
609 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
610 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
611 else
612 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
613
614 if (rs->rs_flags & HAL_RX_GI)
615 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
616 }
617
618 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf));
619 if (rs->rs_status & HAL_RXERR_CRC)
620 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
621 /* XXX propagate other error flags from descriptor */
622 sc->sc_rx_th.wr_antnoise = nf;
623 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
624 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
625 #undef CHAN_HT
626 #undef CHAN_HT20
627 #undef CHAN_HT40U
628 #undef CHAN_HT40D
629 }
630
631 static void
ath_handle_micerror(struct ieee80211com * ic,struct ieee80211_frame * wh,int keyix)632 ath_handle_micerror(struct ieee80211com *ic,
633 struct ieee80211_frame *wh, int keyix)
634 {
635 struct ieee80211_node *ni;
636
637 /* XXX recheck MIC to deal w/ chips that lie */
638 /* XXX discard MIC errors on !data frames */
639 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
640 if (ni != NULL) {
641 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
642 ieee80211_free_node(ni);
643 }
644 }
645
646 /*
647 * Process a single packet.
648 *
649 * The mbuf must already be synced, unmapped and removed from bf->bf_m
650 * by this stage.
651 *
652 * The mbuf must be consumed by this routine - either passed up the
653 * net80211 stack, put on the holding queue, or freed.
654 */
655 int
ath_rx_pkt(struct ath_softc * sc,struct ath_rx_status * rs,HAL_STATUS status,uint64_t tsf,int nf,HAL_RX_QUEUE qtype,struct ath_buf * bf,struct mbuf * m)656 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status,
657 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf,
658 struct mbuf *m)
659 {
660 uint64_t rstamp;
661 /* XXX TODO: make this an mbuf tag? */
662 struct ieee80211_rx_stats rxs;
663 int len, type, i;
664 struct ieee80211com *ic = &sc->sc_ic;
665 struct ieee80211_node *ni;
666 int is_good = 0;
667 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
668
669 /*
670 * Calculate the correct 64 bit TSF given
671 * the TSF64 register value and rs_tstamp.
672 */
673 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
674
675 /* 802.11 return codes - These aren't specifically errors */
676 if (rs->rs_flags & HAL_RX_GI)
677 sc->sc_stats.ast_rx_halfgi++;
678 if (rs->rs_flags & HAL_RX_2040)
679 sc->sc_stats.ast_rx_2040++;
680 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE)
681 sc->sc_stats.ast_rx_pre_crc_err++;
682 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST)
683 sc->sc_stats.ast_rx_post_crc_err++;
684 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY)
685 sc->sc_stats.ast_rx_decrypt_busy_err++;
686 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
687 sc->sc_stats.ast_rx_hi_rx_chain++;
688 if (rs->rs_flags & HAL_RX_STBC)
689 sc->sc_stats.ast_rx_stbc++;
690
691 if (rs->rs_status != 0) {
692 if (rs->rs_status & HAL_RXERR_CRC)
693 sc->sc_stats.ast_rx_crcerr++;
694 if (rs->rs_status & HAL_RXERR_FIFO)
695 sc->sc_stats.ast_rx_fifoerr++;
696 if (rs->rs_status & HAL_RXERR_PHY) {
697 sc->sc_stats.ast_rx_phyerr++;
698 /* Process DFS radar events */
699 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) ||
700 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) {
701 /* Now pass it to the radar processing code */
702 ath_dfs_process_phy_err(sc, m, rstamp, rs);
703 }
704
705 /*
706 * Be suitably paranoid about receiving phy errors
707 * out of the stats array bounds
708 */
709 if (rs->rs_phyerr < ATH_IOCTL_STATS_NUM_RX_PHYERR)
710 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
711 goto rx_error; /* NB: don't count in ierrors */
712 }
713 if (rs->rs_status & HAL_RXERR_DECRYPT) {
714 /*
715 * Decrypt error. If the error occurred
716 * because there was no hardware key, then
717 * let the frame through so the upper layers
718 * can process it. This is necessary for 5210
719 * parts which have no way to setup a ``clear''
720 * key cache entry.
721 *
722 * XXX do key cache faulting
723 */
724 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
725 goto rx_accept;
726 sc->sc_stats.ast_rx_badcrypt++;
727 }
728 /*
729 * Similar as above - if the failure was a keymiss
730 * just punt it up to the upper layers for now.
731 */
732 if (rs->rs_status & HAL_RXERR_KEYMISS) {
733 sc->sc_stats.ast_rx_keymiss++;
734 goto rx_accept;
735 }
736 if (rs->rs_status & HAL_RXERR_MIC) {
737 sc->sc_stats.ast_rx_badmic++;
738 /*
739 * Do minimal work required to hand off
740 * the 802.11 header for notification.
741 */
742 /* XXX frag's and qos frames */
743 len = rs->rs_datalen;
744 if (len >= sizeof (struct ieee80211_frame)) {
745 ath_handle_micerror(ic,
746 mtod(m, struct ieee80211_frame *),
747 sc->sc_splitmic ?
748 rs->rs_keyix-32 : rs->rs_keyix);
749 }
750 }
751 counter_u64_add(ic->ic_ierrors, 1);
752 rx_error:
753 /*
754 * Cleanup any pending partial frame.
755 */
756 if (re->m_rxpending != NULL) {
757 m_freem(re->m_rxpending);
758 re->m_rxpending = NULL;
759 }
760 /*
761 * When a tap is present pass error frames
762 * that have been requested. By default we
763 * pass decrypt+mic errors but others may be
764 * interesting (e.g. crc).
765 */
766 if (ieee80211_radiotap_active(ic) &&
767 (rs->rs_status & sc->sc_monpass)) {
768 /* NB: bpf needs the mbuf length setup */
769 len = rs->rs_datalen;
770 m->m_pkthdr.len = m->m_len = len;
771 ath_rx_tap(sc, m, rs, rstamp, nf);
772 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
773 ath_rx_tap_vendor(sc, m, rs, rstamp, nf);
774 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
775 ieee80211_radiotap_rx_all(ic, m);
776 }
777 /* XXX pass MIC errors up for s/w reclaculation */
778 m_freem(m); m = NULL;
779 goto rx_next;
780 }
781 rx_accept:
782 len = rs->rs_datalen;
783 m->m_len = len;
784
785 if (rs->rs_more) {
786 /*
787 * Frame spans multiple descriptors; save
788 * it for the next completed descriptor, it
789 * will be used to construct a jumbogram.
790 */
791 if (re->m_rxpending != NULL) {
792 /* NB: max frame size is currently 2 clusters */
793 sc->sc_stats.ast_rx_toobig++;
794 m_freem(re->m_rxpending);
795 }
796 m->m_pkthdr.len = len;
797 re->m_rxpending = m;
798 m = NULL;
799 goto rx_next;
800 } else if (re->m_rxpending != NULL) {
801 /*
802 * This is the second part of a jumbogram,
803 * chain it to the first mbuf, adjust the
804 * frame length, and clear the rxpending state.
805 */
806 re->m_rxpending->m_next = m;
807 re->m_rxpending->m_pkthdr.len += len;
808 m = re->m_rxpending;
809 re->m_rxpending = NULL;
810 } else {
811 /*
812 * Normal single-descriptor receive; setup packet length.
813 */
814 m->m_pkthdr.len = len;
815 }
816
817 /*
818 * Validate rs->rs_antenna.
819 *
820 * Some users w/ AR9285 NICs have reported crashes
821 * here because rs_antenna field is bogusly large.
822 * Let's enforce the maximum antenna limit of 8
823 * (and it shouldn't be hard coded, but that's a
824 * separate problem) and if there's an issue, print
825 * out an error and adjust rs_antenna to something
826 * sensible.
827 *
828 * This code should be removed once the actual
829 * root cause of the issue has been identified.
830 * For example, it may be that the rs_antenna
831 * field is only valid for the last frame of
832 * an aggregate and it just happens that it is
833 * "mostly" right. (This is a general statement -
834 * the majority of the statistics are only valid
835 * for the last frame in an aggregate.
836 */
837 if (rs->rs_antenna >= ATH_IOCTL_STATS_NUM_RX_ANTENNA) {
838 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
839 __func__, rs->rs_antenna);
840 #ifdef ATH_DEBUG
841 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
842 #endif /* ATH_DEBUG */
843 rs->rs_antenna = 0; /* XXX better than nothing */
844 }
845
846 /*
847 * If this is an AR9285/AR9485, then the receive and LNA
848 * configuration is stored in RSSI[2] / EXTRSSI[2].
849 * We can extract this out to build a much better
850 * receive antenna profile.
851 *
852 * Yes, this just blurts over the above RX antenna field
853 * for now. It's fine, the AR9285 doesn't really use
854 * that.
855 *
856 * Later on we should store away the fine grained LNA
857 * information and keep separate counters just for
858 * that. It'll help when debugging the AR9285/AR9485
859 * combined diversity code.
860 */
861 if (sc->sc_rx_lnamixer) {
862 rs->rs_antenna = 0;
863
864 /* Bits 0:1 - the LNA configuration used */
865 rs->rs_antenna |=
866 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED)
867 >> HAL_RX_LNA_CFG_USED_S);
868
869 /* Bit 2 - the external RX antenna switch */
870 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG)
871 rs->rs_antenna |= 0x4;
872 }
873
874 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
875
876 /*
877 * Populate the rx status block. When there are bpf
878 * listeners we do the additional work to provide
879 * complete status. Otherwise we fill in only the
880 * material required by ieee80211_input. Note that
881 * noise setting is filled in above.
882 */
883 if (ieee80211_radiotap_active(ic)) {
884 ath_rx_tap(sc, m, rs, rstamp, nf);
885 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
886 ath_rx_tap_vendor(sc, m, rs, rstamp, nf);
887 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
888 }
889
890 /*
891 * From this point on we assume the frame is at least
892 * as large as ieee80211_frame_min; verify that.
893 */
894 if (len < IEEE80211_MIN_LEN) {
895 if (!ieee80211_radiotap_active(ic)) {
896 DPRINTF(sc, ATH_DEBUG_RECV,
897 "%s: short packet %d\n", __func__, len);
898 sc->sc_stats.ast_rx_tooshort++;
899 } else {
900 /* NB: in particular this captures ack's */
901 ieee80211_radiotap_rx_all(ic, m);
902 }
903 m_freem(m); m = NULL;
904 goto rx_next;
905 }
906
907 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
908 const HAL_RATE_TABLE *rt = sc->sc_currates;
909 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
910
911 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
912 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
913 }
914
915 m_adj(m, -IEEE80211_CRC_LEN);
916
917 /*
918 * Locate the node for sender, track state, and then
919 * pass the (referenced) node up to the 802.11 layer
920 * for its use.
921 */
922 ni = ieee80211_find_rxnode_withkey(ic,
923 mtod(m, const struct ieee80211_frame_min *),
924 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
925 IEEE80211_KEYIX_NONE : rs->rs_keyix);
926 sc->sc_lastrs = rs;
927
928 if (rs->rs_isaggr)
929 sc->sc_stats.ast_rx_agg++;
930
931 /*
932 * Populate the per-chain RSSI values where appropriate.
933 */
934 bzero(&rxs, sizeof(rxs));
935 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI |
936 IEEE80211_R_C_CHAIN |
937 IEEE80211_R_C_NF |
938 IEEE80211_R_C_RSSI |
939 IEEE80211_R_TSF64 |
940 IEEE80211_R_TSF_START; /* XXX TODO: validate */
941 rxs.c_rssi = rs->rs_rssi;
942 rxs.c_nf = nf;
943 rxs.c_chain = 3; /* XXX TODO: check */
944 rxs.c_rx_tsf = rstamp;
945
946 for (i = 0; i < 3; i++) {
947 rxs.c_rssi_ctl[i] = rs->rs_rssi_ctl[i];
948 rxs.c_rssi_ext[i] = rs->rs_rssi_ext[i];
949 /*
950 * XXX note: we currently don't track
951 * per-chain noisefloor.
952 */
953 rxs.c_nf_ctl[i] = nf;
954 rxs.c_nf_ext[i] = nf;
955 }
956
957 if (ni != NULL) {
958 /*
959 * Only punt packets for ampdu reorder processing for
960 * 11n nodes; net80211 enforces that M_AMPDU is only
961 * set for 11n nodes.
962 */
963 if (ni->ni_flags & IEEE80211_NODE_HT)
964 m->m_flags |= M_AMPDU;
965
966 /*
967 * Inform rate control about the received RSSI.
968 * It can then use this information to potentially drastically
969 * alter the available rate based on the RSSI estimate.
970 *
971 * This is super important when associating to a far away station;
972 * you don't want to waste time trying higher rates at some low
973 * packet exchange rate (like during DHCP) just to establish
974 * that higher MCS rates aren't available.
975 */
976 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgrssi,
977 rs->rs_rssi);
978 ath_rate_update_rx_rssi(sc, ATH_NODE(ni),
979 ATH_RSSI(ATH_NODE(ni)->an_node_stats.ns_avgrssi));
980
981 /*
982 * Sending station is known, dispatch directly.
983 */
984 (void) ieee80211_add_rx_params(m, &rxs);
985 type = ieee80211_input_mimo(ni, m);
986 ieee80211_free_node(ni);
987 m = NULL;
988 /*
989 * Arrange to update the last rx timestamp only for
990 * frames from our ap when operating in station mode.
991 * This assumes the rx key is always setup when
992 * associated.
993 */
994 if (ic->ic_opmode == IEEE80211_M_STA &&
995 rs->rs_keyix != HAL_RXKEYIX_INVALID)
996 is_good = 1;
997 } else {
998 (void) ieee80211_add_rx_params(m, &rxs);
999 type = ieee80211_input_mimo_all(ic, m);
1000 m = NULL;
1001 }
1002
1003 /*
1004 * At this point we have passed the frame up the stack; thus
1005 * the mbuf is no longer ours.
1006 */
1007
1008 /*
1009 * Track legacy station RX rssi and do any rx antenna management.
1010 */
1011 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
1012 if (sc->sc_diversity) {
1013 /*
1014 * When using fast diversity, change the default rx
1015 * antenna if diversity chooses the other antenna 3
1016 * times in a row.
1017 */
1018 if (sc->sc_defant != rs->rs_antenna) {
1019 if (++sc->sc_rxotherant >= 3)
1020 ath_setdefantenna(sc, rs->rs_antenna);
1021 } else
1022 sc->sc_rxotherant = 0;
1023 }
1024
1025 /* Handle slow diversity if enabled */
1026 if (sc->sc_dolnadiv) {
1027 ath_lna_rx_comb_scan(sc, rs, ticks, hz);
1028 }
1029
1030 if (sc->sc_softled) {
1031 /*
1032 * Blink for any data frame. Otherwise do a
1033 * heartbeat-style blink when idle. The latter
1034 * is mainly for station mode where we depend on
1035 * periodic beacon frames to trigger the poll event.
1036 */
1037 if (type == IEEE80211_FC0_TYPE_DATA) {
1038 const HAL_RATE_TABLE *rt = sc->sc_currates;
1039 ath_led_event(sc,
1040 rt->rateCodeToIndex[rs->rs_rate]);
1041 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
1042 ath_led_event(sc, 0);
1043 }
1044 rx_next:
1045 /*
1046 * Debugging - complain if we didn't NULL the mbuf pointer
1047 * here.
1048 */
1049 if (m != NULL) {
1050 device_printf(sc->sc_dev,
1051 "%s: mbuf %p should've been freed!\n",
1052 __func__,
1053 m);
1054 }
1055 return (is_good);
1056 }
1057
1058 #define ATH_RX_MAX 128
1059
1060 /*
1061 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like
1062 * the EDMA code does.
1063 *
1064 * XXX TODO: then, do all of the RX list management stuff inside
1065 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA
1066 * code is doing it right.
1067 */
1068 static void
ath_rx_proc(struct ath_softc * sc,int resched)1069 ath_rx_proc(struct ath_softc *sc, int resched)
1070 {
1071 #define PA2DESC(_sc, _pa) \
1072 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1073 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1074 struct ath_buf *bf;
1075 struct ath_hal *ah = sc->sc_ah;
1076 #ifdef IEEE80211_SUPPORT_SUPERG
1077 struct ieee80211com *ic = &sc->sc_ic;
1078 #endif
1079 struct ath_desc *ds;
1080 struct ath_rx_status *rs;
1081 struct mbuf *m;
1082 int ngood;
1083 HAL_STATUS status;
1084 int16_t nf;
1085 u_int64_t tsf;
1086 int npkts = 0;
1087 int kickpcu = 0;
1088 int ret;
1089
1090 /* XXX we must not hold the ATH_LOCK here */
1091 ATH_UNLOCK_ASSERT(sc);
1092 ATH_PCU_UNLOCK_ASSERT(sc);
1093
1094 ATH_PCU_LOCK(sc);
1095 sc->sc_rxproc_cnt++;
1096 kickpcu = sc->sc_kickpcu;
1097 ATH_PCU_UNLOCK(sc);
1098
1099 ATH_LOCK(sc);
1100 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1101 ATH_UNLOCK(sc);
1102
1103 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__);
1104 ngood = 0;
1105 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
1106 sc->sc_stats.ast_rx_noise = nf;
1107 tsf = ath_hal_gettsf64(ah);
1108 do {
1109 /*
1110 * Don't process too many packets at a time; give the
1111 * TX thread time to also run - otherwise the TX
1112 * latency can jump by quite a bit, causing throughput
1113 * degredation.
1114 */
1115 if (!kickpcu && npkts >= ATH_RX_MAX)
1116 break;
1117
1118 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1119 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */
1120 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__);
1121 break;
1122 } else if (bf == NULL) {
1123 /*
1124 * End of List:
1125 * this can happen for non-self-linked RX chains
1126 */
1127 sc->sc_stats.ast_rx_hitqueueend++;
1128 break;
1129 }
1130 m = bf->bf_m;
1131 if (m == NULL) { /* NB: shouldn't happen */
1132 /*
1133 * If mbuf allocation failed previously there
1134 * will be no mbuf; try again to re-populate it.
1135 */
1136 /* XXX make debug msg */
1137 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__);
1138 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1139 goto rx_proc_next;
1140 }
1141 ds = bf->bf_desc;
1142 if (ds->ds_link == bf->bf_daddr) {
1143 /* NB: never process the self-linked entry at the end */
1144 sc->sc_stats.ast_rx_hitqueueend++;
1145 break;
1146 }
1147 /* XXX sync descriptor memory */
1148 /*
1149 * Must provide the virtual address of the current
1150 * descriptor, the physical address, and the virtual
1151 * address of the next descriptor in the h/w chain.
1152 * This allows the HAL to look ahead to see if the
1153 * hardware is done with a descriptor by checking the
1154 * done bit in the following descriptor and the address
1155 * of the current descriptor the DMA engine is working
1156 * on. All this is necessary because of our use of
1157 * a self-linked list to avoid rx overruns.
1158 */
1159 rs = &bf->bf_status.ds_rxstat;
1160 status = ath_hal_rxprocdesc(ah, ds,
1161 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1162 #ifdef ATH_DEBUG
1163 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
1164 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
1165 #endif
1166
1167 #ifdef ATH_DEBUG_ALQ
1168 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
1169 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
1170 sc->sc_rx_statuslen, (char *) ds);
1171 #endif /* ATH_DEBUG_ALQ */
1172
1173 if (status == HAL_EINPROGRESS)
1174 break;
1175
1176 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1177 npkts++;
1178
1179 /*
1180 * Process a single frame.
1181 */
1182 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD);
1183 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
1184 bf->bf_m = NULL;
1185 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m))
1186 ngood++;
1187 rx_proc_next:
1188 /*
1189 * If there's a holding buffer, insert that onto
1190 * the RX list; the hardware is now definitely not pointing
1191 * to it now.
1192 */
1193 ret = 0;
1194 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) {
1195 TAILQ_INSERT_TAIL(&sc->sc_rxbuf,
1196 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf,
1197 bf_list);
1198 ret = ath_rxbuf_init(sc,
1199 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf);
1200 }
1201 /*
1202 * Next, throw our buffer into the holding entry. The hardware
1203 * may use the descriptor to read the link pointer before
1204 * DMAing the next descriptor in to write out a packet.
1205 */
1206 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf;
1207 } while (ret == 0);
1208
1209 /* rx signal state monitoring */
1210 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
1211 if (ngood)
1212 sc->sc_lastrx = tsf;
1213
1214 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood);
1215 /* Queue DFS tasklet if needed */
1216 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan))
1217 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
1218
1219 /*
1220 * Now that all the RX frames were handled that
1221 * need to be handled, kick the PCU if there's
1222 * been an RXEOL condition.
1223 */
1224 if (resched && kickpcu) {
1225 ATH_PCU_LOCK(sc);
1226 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu");
1227 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n",
1228 __func__, npkts);
1229
1230 /*
1231 * Go through the process of fully tearing down
1232 * the RX buffers and reinitialising them.
1233 *
1234 * There's a hardware bug that causes the RX FIFO
1235 * to get confused under certain conditions and
1236 * constantly write over the same frame, leading
1237 * the RX driver code here to get heavily confused.
1238 */
1239 /*
1240 * XXX Has RX DMA stopped enough here to just call
1241 * ath_startrecv()?
1242 * XXX Do we need to use the holding buffer to restart
1243 * RX DMA by appending entries to the final
1244 * descriptor? Quite likely.
1245 */
1246 #if 1
1247 ath_startrecv(sc);
1248 #else
1249 /*
1250 * Disabled for now - it'd be nice to be able to do
1251 * this in order to limit the amount of CPU time spent
1252 * reinitialising the RX side (and thus minimise RX
1253 * drops) however there's a hardware issue that
1254 * causes things to get too far out of whack.
1255 */
1256 /*
1257 * XXX can we hold the PCU lock here?
1258 * Are there any net80211 buffer calls involved?
1259 */
1260 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1261 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1262 ath_hal_rxena(ah); /* enable recv descriptors */
1263 ath_mode_init(sc); /* set filters, etc. */
1264 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */
1265 #endif
1266
1267 ath_hal_intrset(ah, sc->sc_imask);
1268 sc->sc_kickpcu = 0;
1269 ATH_PCU_UNLOCK(sc);
1270 }
1271
1272 #ifdef IEEE80211_SUPPORT_SUPERG
1273 if (resched)
1274 ieee80211_ff_age_all(ic, 100);
1275 #endif
1276
1277 /*
1278 * Put the hardware to sleep again if we're done with it.
1279 */
1280 ATH_LOCK(sc);
1281 ath_power_restore_power_state(sc);
1282 ATH_UNLOCK(sc);
1283
1284 /*
1285 * If we hit the maximum number of frames in this round,
1286 * reschedule for another immediate pass. This gives
1287 * the TX and TX completion routines time to run, which
1288 * will reduce latency.
1289 */
1290 if (npkts >= ATH_RX_MAX)
1291 sc->sc_rx.recv_sched(sc, resched);
1292
1293 ATH_PCU_LOCK(sc);
1294 sc->sc_rxproc_cnt--;
1295 ATH_PCU_UNLOCK(sc);
1296 }
1297 #undef PA2DESC
1298 #undef ATH_RX_MAX
1299
1300 /*
1301 * Only run the RX proc if it's not already running.
1302 * Since this may get run as part of the reset/flush path,
1303 * the task can't clash with an existing, running tasklet.
1304 */
1305 static void
ath_legacy_rx_tasklet(void * arg,int npending)1306 ath_legacy_rx_tasklet(void *arg, int npending)
1307 {
1308 struct ath_softc *sc = arg;
1309
1310 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending);
1311 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
1312 ATH_PCU_LOCK(sc);
1313 if (sc->sc_inreset_cnt > 0) {
1314 device_printf(sc->sc_dev,
1315 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
1316 ATH_PCU_UNLOCK(sc);
1317 return;
1318 }
1319 ATH_PCU_UNLOCK(sc);
1320
1321 ath_rx_proc(sc, 1);
1322 }
1323
1324 static void
ath_legacy_flushrecv(struct ath_softc * sc)1325 ath_legacy_flushrecv(struct ath_softc *sc)
1326 {
1327
1328 ath_rx_proc(sc, 0);
1329 }
1330
1331 static void
ath_legacy_flush_rxpending(struct ath_softc * sc)1332 ath_legacy_flush_rxpending(struct ath_softc *sc)
1333 {
1334
1335 /* XXX ATH_RX_LOCK_ASSERT(sc); */
1336
1337 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) {
1338 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
1339 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1340 }
1341 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) {
1342 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
1343 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1344 }
1345 }
1346
1347 static int
ath_legacy_flush_rxholdbf(struct ath_softc * sc)1348 ath_legacy_flush_rxholdbf(struct ath_softc *sc)
1349 {
1350 struct ath_buf *bf;
1351
1352 /* XXX ATH_RX_LOCK_ASSERT(sc); */
1353 /*
1354 * If there are RX holding buffers, free them here and return
1355 * them to the list.
1356 *
1357 * XXX should just verify that bf->bf_m is NULL, as it must
1358 * be at this point!
1359 */
1360 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf;
1361 if (bf != NULL) {
1362 if (bf->bf_m != NULL)
1363 m_freem(bf->bf_m);
1364 bf->bf_m = NULL;
1365 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1366 (void) ath_rxbuf_init(sc, bf);
1367 }
1368 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL;
1369
1370 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf;
1371 if (bf != NULL) {
1372 if (bf->bf_m != NULL)
1373 m_freem(bf->bf_m);
1374 bf->bf_m = NULL;
1375 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1376 (void) ath_rxbuf_init(sc, bf);
1377 }
1378 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL;
1379
1380 return (0);
1381 }
1382
1383 /*
1384 * Disable the receive h/w in preparation for a reset.
1385 */
1386 static void
ath_legacy_stoprecv(struct ath_softc * sc,int dodelay)1387 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay)
1388 {
1389 #define PA2DESC(_sc, _pa) \
1390 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1391 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1392 struct ath_hal *ah = sc->sc_ah;
1393
1394 ATH_RX_LOCK(sc);
1395
1396 ath_hal_stoppcurecv(ah); /* disable PCU */
1397 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
1398 ath_hal_stopdmarecv(ah); /* disable DMA engine */
1399 /*
1400 * TODO: see if this particular DELAY() is required; it may be
1401 * masking some missing FIFO flush or DMA sync.
1402 */
1403 #if 0
1404 if (dodelay)
1405 #endif
1406 DELAY(3000); /* 3ms is long enough for 1 frame */
1407 #ifdef ATH_DEBUG
1408 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
1409 struct ath_buf *bf;
1410 u_int ix;
1411
1412 device_printf(sc->sc_dev,
1413 "%s: rx queue %p, link %p\n",
1414 __func__,
1415 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP),
1416 sc->sc_rxlink);
1417 ix = 0;
1418 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1419 struct ath_desc *ds = bf->bf_desc;
1420 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
1421 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
1422 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1423 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
1424 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
1425 ix++;
1426 }
1427 }
1428 #endif
1429
1430 (void) ath_legacy_flush_rxpending(sc);
1431 (void) ath_legacy_flush_rxholdbf(sc);
1432
1433 sc->sc_rxlink = NULL; /* just in case */
1434
1435 ATH_RX_UNLOCK(sc);
1436 #undef PA2DESC
1437 }
1438
1439 /*
1440 * XXX TODO: something was calling startrecv without calling
1441 * stoprecv. Let's figure out what/why. It was showing up
1442 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.)
1443 */
1444
1445 /*
1446 * Enable the receive h/w following a reset.
1447 */
1448 static int
ath_legacy_startrecv(struct ath_softc * sc)1449 ath_legacy_startrecv(struct ath_softc *sc)
1450 {
1451 struct ath_hal *ah = sc->sc_ah;
1452 struct ath_buf *bf;
1453
1454 ATH_RX_LOCK(sc);
1455
1456 /*
1457 * XXX should verify these are already all NULL!
1458 */
1459 sc->sc_rxlink = NULL;
1460 (void) ath_legacy_flush_rxpending(sc);
1461 (void) ath_legacy_flush_rxholdbf(sc);
1462
1463 /*
1464 * Re-chain all of the buffers in the RX buffer list.
1465 */
1466 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1467 int error = ath_rxbuf_init(sc, bf);
1468 if (error != 0) {
1469 DPRINTF(sc, ATH_DEBUG_RECV,
1470 "%s: ath_rxbuf_init failed %d\n",
1471 __func__, error);
1472 return error;
1473 }
1474 }
1475
1476 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1477 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1478 ath_hal_rxena(ah); /* enable recv descriptors */
1479 ath_mode_init(sc); /* set filters, etc. */
1480 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */
1481
1482 ATH_RX_UNLOCK(sc);
1483 return 0;
1484 }
1485
1486 static int
ath_legacy_dma_rxsetup(struct ath_softc * sc)1487 ath_legacy_dma_rxsetup(struct ath_softc *sc)
1488 {
1489 int error;
1490
1491 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
1492 "rx", sizeof(struct ath_desc), ath_rxbuf, 1);
1493 if (error != 0)
1494 return (error);
1495
1496 return (0);
1497 }
1498
1499 static int
ath_legacy_dma_rxteardown(struct ath_softc * sc)1500 ath_legacy_dma_rxteardown(struct ath_softc *sc)
1501 {
1502
1503 if (sc->sc_rxdma.dd_desc_len != 0)
1504 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
1505 return (0);
1506 }
1507
1508 static void
ath_legacy_recv_sched(struct ath_softc * sc,int dosched)1509 ath_legacy_recv_sched(struct ath_softc *sc, int dosched)
1510 {
1511
1512 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1513 }
1514
1515 static void
ath_legacy_recv_sched_queue(struct ath_softc * sc,HAL_RX_QUEUE q,int dosched)1516 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q,
1517 int dosched)
1518 {
1519
1520 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1521 }
1522
1523 void
ath_recv_setup_legacy(struct ath_softc * sc)1524 ath_recv_setup_legacy(struct ath_softc *sc)
1525 {
1526
1527 /* Sensible legacy defaults */
1528 /*
1529 * XXX this should be changed to properly support the
1530 * exact RX descriptor size for each HAL.
1531 */
1532 sc->sc_rx_statuslen = sizeof(struct ath_desc);
1533
1534 sc->sc_rx.recv_start = ath_legacy_startrecv;
1535 sc->sc_rx.recv_stop = ath_legacy_stoprecv;
1536 sc->sc_rx.recv_flush = ath_legacy_flushrecv;
1537 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet;
1538 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init;
1539
1540 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup;
1541 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown;
1542 sc->sc_rx.recv_sched = ath_legacy_recv_sched;
1543 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue;
1544 }
1545