1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #define ASMC_MAXFANS 6 31 32 struct asmc_softc { 33 device_t sc_dev; 34 struct mtx sc_mtx; 35 int sc_nfan; 36 int16_t sms_rest_x; 37 int16_t sms_rest_y; 38 int16_t sms_rest_z; 39 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 40 struct sysctl_oid *sc_temp_tree; 41 struct sysctl_oid *sc_sms_tree; 42 struct sysctl_oid *sc_light_tree; 43 const struct asmc_model *sc_model; 44 int sc_rid_port; 45 int sc_rid_irq; 46 struct resource *sc_ioport; 47 struct resource *sc_irq; 48 void *sc_cookie; 49 int sc_sms_intrtype; 50 struct taskqueue *sc_sms_tq; 51 struct task sc_sms_task; 52 uint8_t sc_sms_intr_works; 53 }; 54 55 /* 56 * Data port. 57 */ 58 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 59 #define ASMC_DATAPORT_WRITE(sc, val) \ 60 bus_write_1(sc->sc_ioport, 0x00, val) 61 #define ASMC_STATUS_MASK 0x0f 62 63 /* 64 * Command port. 65 */ 66 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 67 #define ASMC_CMDPORT_WRITE(sc, val) \ 68 bus_write_1(sc->sc_ioport, 0x04, val) 69 #define ASMC_CMDREAD 0x10 70 #define ASMC_CMDWRITE 0x11 71 72 /* 73 * Interrupt port. 74 */ 75 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 76 77 /* Number of keys */ 78 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 79 80 /* 81 * Fan control via SMC. 82 */ 83 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 84 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 85 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 86 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 87 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */ 88 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 89 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 90 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 91 92 /* 93 * Sudden Motion Sensor (SMS). 94 */ 95 #define ASMC_SMS_INIT1 0xe0 96 #define ASMC_SMS_INIT2 0xf8 97 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 98 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 99 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 100 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 101 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 102 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 103 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 104 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 105 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 106 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 107 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 108 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 109 110 /* 111 * Light Sensor. 112 */ 113 #define ASMC_ALSL_INT2A 0x2a /* Ambient Light related Interrupt */ 114 115 /* 116 * Keyboard backlight. 117 */ 118 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 119 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 120 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 121 122 /* 123 * Clamshell. 124 */ 125 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 126 127 /* 128 * Interrupt keys. 129 */ 130 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 131 132 /* 133 * Temperatures. 134 * 135 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 136 * fourth the Mac Pro 8-core and finally the MacBook Air. 137 * 138 */ 139 /* maximum array size for temperatures including the last NULL */ 140 #define ASMC_TEMP_MAX 80 141 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 142 "TM0P", NULL } 143 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 144 "northbridge2", "heatsink1", \ 145 "heatsink2", "memory", } 146 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 147 "Northbridge Point 1", \ 148 "Northbridge Point 2", "Heatsink 1", \ 149 "Heatsink 2", "Memory Bank A", } 150 151 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 152 "TM0P", NULL } 153 154 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 155 "heatsink1", "heatsink2", \ 156 "memory", } 157 158 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 159 "Northbridge Point 1", \ 160 "Heatsink 1","Heatsink 2" \ 161 "Memory Bank A", } 162 163 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \ 164 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \ 165 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \ 166 "Ts0P", "Ts0S", NULL } 167 168 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \ 169 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \ 170 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \ 171 "palm_rest", "memory_proximity", } 172 173 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \ 174 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \ 175 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \ 176 "Palm Rest", "Memory Proximity", } 177 178 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 179 "TG0H", "TG0P", "TG0T", NULL } 180 181 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 182 "heatsink2", "memory", "graphics", \ 183 "graphicssink", "unknown", } 184 185 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 186 "Heatsink 1", "Heatsink 2", \ 187 "Memory Controller", \ 188 "Graphics Chip", "Graphics Heatsink", \ 189 "Unknown", } 190 191 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 192 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 193 "TTF0", "TW0P", NULL } 194 195 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 196 "heatsink3", "memory", "graphicssink", \ 197 "graphics", "cpu", "cpu2", "unknown1", \ 198 "unknown2", "wireless", } 199 200 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 201 "Main Heatsink 1", "Main Heatsink 2", \ 202 "Main Heatsink 3", \ 203 "Memory Controller", \ 204 "Graphics Chip Heatsink", \ 205 "Graphics Chip Diode", \ 206 "CPU Temperature Diode", "CPU Point 2", \ 207 "Unknown", "Unknown", \ 208 "Wireless Module", } 209 210 #define ASMC_MBP5_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 211 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 212 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 213 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 214 NULL } 215 216 #define ASMC_MBP5_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 217 "enclosure_bottom_2", "enclosure_bottom_3", \ 218 "cpu_diode", "cpu", \ 219 "cpu_pin", "gpu_diode", \ 220 "gpu", "gpu_heatsink", \ 221 "gpu_pin", "gpu_transistor", \ 222 "gpu_2_heatsink", "northbridge_diode", \ 223 "northbridge_pin", "unknown", \ 224 "heatsink_2", "memory_controller", \ 225 "pci_express_slot_pin", "pci_express_slot_unk" } 226 227 #define ASMC_MBP5_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 228 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 229 "CPU Diode", "CPU ???", \ 230 "CPU Pin", "GPU Diode", \ 231 "GPU ???", "GPU Heatsink", \ 232 "GPU Pin", "GPU Transistor", \ 233 "GPU 2 Heatsink", "Northbridge Diode", \ 234 "Northbridge Pin", "Unknown", \ 235 "Heatsink 2", "Memory Controller", \ 236 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 237 238 #define ASMC_MBP62_TEMPS { "TB0T", "TB1T", "TB2T", \ 239 "TC0C", "TC0D", "TC0P", \ 240 "TC1C", "TG0D", "TG0P", \ 241 "TG0T", "TMCD", "TP0P", \ 242 "TPCD", "Th1H", "Th2H", \ 243 "Tm0P", "Ts0P", "Ts0S" } 244 245 #define ASMC_MBP62_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 246 "enclosure_bottom_2", "cpu0", \ 247 "cpu_diode", "cpu_proximity", \ 248 "cpu1", "gpu_diode", \ 249 "gpu_pin", "gpu_transistor", \ 250 "TMCD", "pch_controller_proximity", \ 251 "pch_die", "heatsink1", \ 252 "heatsink2", "memory-controller", \ 253 "palmrest", "memoryproximity" } 254 255 #define ASMC_MBP62_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 256 "Enclosure Bottom 2", "CPU 0", \ 257 "CPU Diode", "CPU Proximity", \ 258 "CPU 1", "GPU Diode", \ 259 "GPU Pin", "GPU Transistor", \ 260 "TMCD", "PCH Controller Proximity", \ 261 "PCH Die", "Heat Sink 1", \ 262 "Heat Sink 2", "Memory Controller", \ 263 "Palm Rest", "Memory Proximity" } 264 265 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 266 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 267 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 268 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 269 "Ts0S", NULL } 270 271 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 272 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 273 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 274 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \ 275 "Ts0S" } 276 277 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 278 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 279 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 280 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 281 "Ts0S" } 282 283 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 284 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 285 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 286 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 287 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 288 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 289 290 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 291 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 292 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 293 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 294 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 295 "Th2H", "memory", "Ts0P", "Ts0S" } 296 297 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 298 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 299 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 300 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 301 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 302 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 303 304 #define ASMC_MBP91_TEMPS { "TA0P", "TB0T", "TB1T", "TB2T", "TC0E", \ 305 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 306 "TC4C", "TCGC", "TCSA", "TCXC", "TG0D", \ 307 "TG0P", "TG1D", "TG1F", "TG1d", "TGTC", \ 308 "TGTD", "TM0P", "TM0S", "TP0P", "TPCD", \ 309 "Th1H", "Th2H", "Ts0P", "Ts0S", "Tsqf", NULL } 310 311 #define ASMC_MBP91_TEMPNAMES { "ambient", "enclosure_bottom_1", "enclosure_bottom_2", \ 312 "enclosure_bottom_3", "cpu_die_peci_0", "cpu_die_peci_1", \ 313 "cpu_proximity", "cpu_core_1", "cpu_core_2", "cpu_core_3", \ 314 "cpu_core_4", "intel_gpu", "cpu_sys_agent", \ 315 "cpu_core_peci", "gpu_analog", \ 316 "gpu_proximity", "geforce_gpu_digital", "tg1f", \ 317 "gpu_2_die", "tgtc", "tgtd", "memory_proximity", \ 318 "mem_bank_a1", "platform_ctrl_hub", "pch_digital", \ 319 "main_heatsink_r", "main_heatsink_l", "palm_rest", \ 320 "bottom_skin", "tsqf" } 321 322 #define ASMC_MBP91_TEMPDESCS { "Ambient", "Enclosure Bottom 1", "Enclosure Bottom 2", \ 323 "Enclosure Bottom 3", "CPU Die PECI 0", "CPU Die PECI 1", \ 324 "CPU Proximity", "CPU Core 1", "CPU Core 2", \ 325 "CPU Core 3", "CPU Core 4", "Intel GPU", \ 326 "CPU System Agent Core", "CPU Core - PECI", \ 327 "GPU Die - Analog", "GPU Proximity", \ 328 "GeForce GPU Die - Digital", "TG1F", "GPU 2 Die" \ 329 "TGTC", "TGTD", "Memory Proximity", \ 330 "Memory Bank A1", "Platform Controller Hub", "PCH Die - Digital", \ 331 "Main Heatsink Right", "Main Heatsink Left", "Palm Rest", \ 332 "Bottom Skin", "Tsqf" } 333 334 #define ASMC_MBP92_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 335 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 336 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 337 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 338 "TPCD", NULL } 339 340 #define ASMC_MBP92_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 341 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 342 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 343 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 344 "TPCD" } 345 346 #define ASMC_MBP92_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \ 347 "Battery 1", "Battery 2", "Battery TS_MAX", \ 348 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \ 349 "TC0J", "CPU 1 Proximity", "TCFC", \ 350 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \ 351 "GPU Die", "Memory Bank A1", "Memory Module A1", \ 352 "PCH Die" } 353 354 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 355 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 356 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 357 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 358 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 359 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 360 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 361 "Ts1S", NULL } 362 363 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 364 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 365 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 366 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 367 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 368 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 369 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 370 "Ts1S" } 371 372 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 373 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 374 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 375 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 376 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 377 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 378 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 379 "Ts1S" } 380 381 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 382 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 383 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 384 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 385 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 386 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 387 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 388 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 389 "Ts1S", NULL } 390 391 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 392 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 393 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 394 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 395 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 396 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 397 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 398 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 399 "Ts1S" } 400 401 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 402 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 403 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 404 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 405 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 406 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 407 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 408 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 409 "Ts1S" } 410 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 411 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 412 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 413 "Northbridge Point 2" } 414 415 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \ 416 "TC0H", "TC0P", \ 417 "TC1P", "TN0P", \ 418 "TN1P", NULL } 419 420 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \ 421 "cpu_heatsink", "cpu_proximity1", \ 422 "cpu_proximity2", "northbridge_proximity1", \ 423 "northbridge_proximity2", } 424 425 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \ 426 "CPU Die Core Temperature", \ 427 "CPU Heatsink Temperature", \ 428 "CPU Proximity 1 Temperature", \ 429 "CPU Proximity 2 Temperature", \ 430 "Northbridge Proximity 1 Temperature", \ 431 "Northbridge Proximity 2 Temperature", } 432 433 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 434 "TC0P", "TH0P", \ 435 "TN0D", "TN0P", \ 436 "TW0P", NULL } 437 438 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 439 "cpu0_proximity", "hdd_bay", \ 440 "northbridge_die", \ 441 "northbridge_proximity", \ 442 "wireless_proximity", } 443 444 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 445 "CPU0 Heatsink Temperature", \ 446 "CPU0 Proximity Temperature", \ 447 "HDD Bay Temperature", \ 448 "Northbridge Die Core Temperature", \ 449 "Northbridge Proximity Temperature", \ 450 "Wireless Module Proximity Temperature", } 451 452 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 453 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 454 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 455 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 456 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 457 "TW0P", "Tm0P", "Tp0C", NULL } 458 459 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 460 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 461 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 462 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 463 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 464 "TW0P", "Tm0P", "Tp0C", NULL } 465 466 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 467 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 468 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 469 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 470 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 471 "TW0P", "Tm0P", "Tp0C", NULL } 472 473 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \ 474 "TC0D", "TC0P", \ 475 "TG0D", "TG1D", \ 476 "TG0P", "TG0M", \ 477 "TI0P", \ 478 "TM0S", "TMBS", \ 479 "TM0P", "TP0P", \ 480 "TPCD", "Tp0C", \ 481 "TW0P", NULL } 482 483 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 484 "cpu_die", "cpu_proximity", \ 485 "gpu_diode1", "gpu_diode2", \ 486 "gpu_proximity", "gpu_integrated_switcher", \ 487 "thunderbolt_proximity", \ 488 "memory_slot1", "memory_slot2", \ 489 "memory_proximity", "pch_controller_proximity", \ 490 "pch_controller_die", "pwr_supply", \ 491 "wireless_proximity", } 492 493 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \ 494 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 495 "CPU Die Temperature", "CPU Proximity Temperature", \ 496 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \ 497 "GPU Proximity Temperature", \ 498 "Integrated Graphics/GPU Switcher Temperature", \ 499 "Thunderbolt Proximity Temperature", \ 500 "Memory Slot 1 Temperature", \ 501 "Memory Slot 2 Temperature", \ 502 "Memory Slots Proximity Temperature", \ 503 "Platform Controller Hub Proximity Temperature", \ 504 "Platform Controller Hub Die Temperature", \ 505 "Power Supply Temperature", \ 506 "Wireless Module Proximity Temperature", } 507 508 #define ASMC_MM71_TEMPS { "TA0p", "TA1p", \ 509 "TA2p", "TC0c", \ 510 "TC0p", "TC1c", \ 511 "TCGc", "TCSc", \ 512 "TCXC", "TCXR", \ 513 "TM0p", "TPCd", \ 514 "TW0p", "Te0T", \ 515 "Tm0P", NULL } 516 517 #define ASMC_MM71_TEMPNAMES { "ambient_air1", "ambient_air2", \ 518 "ambient_air3", "cpu_core1_peci", \ 519 "cpu_proximity", "cpu_core2_peci", \ 520 "intel_gpu", "cpu_sa_core_peci", \ 521 "cpu_core", "cpu_peci_dts", \ 522 "memory_proximity", "pch_controller_die", \ 523 "wireless_proximity", "thunderbolt_diode", \ 524 "logic_board", } 525 526 #define ASMC_MM71_TEMPDESCS { "Ambient Air Temperature 1", \ 527 "Ambient Air Temperature 2", \ 528 "Ambient Air Temperature 3", \ 529 "CPU Core 1 PECI Temperature", "CPU Proximity Temperature", \ 530 "CPU Core 2 PECI Temperature", "Intel GPU Temperature", \ 531 "CPU System Agent Core PECI Temperature", \ 532 "CPU Core Temperature", "CPU PECI DTS Temperature", \ 533 "Memory Proximity Temperature", \ 534 "Platform Controller Hub Die Temperature", \ 535 "Wireless Module Proximity Temperature", \ 536 "Thunderbolt Diode Temperature", \ 537 "Logic Board temperature", } 538 539 #define ASMC_MP1_TEMPS { "TA0P", \ 540 "TCAH", "TCBH", \ 541 "TC0P", "TC0C", "TC1C", \ 542 "TC2C", "TC3C", "THTG", \ 543 "TH0P", "TH1P", \ 544 "TH2P", "TH3P", \ 545 "TM0P", "TM1P", "TM2P", \ 546 "TM8P", "TM9P", "TMAP", \ 547 "TM0S", "TM1S", "TM2P", "TM3S", \ 548 "TM8S", "TM9S", "TMAS", "TMBS", \ 549 "TN0H", "TS0C", \ 550 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL } 551 552 #define ASMC_MP1_TEMPNAMES { "ambient", \ 553 "cpu_a_heatsink", "cpu_b_heatsink", \ 554 "cpu_a_proximity", "cpu_core0", "cpu_core1", \ 555 "cpu_core2", "cpu_core3", "THTG", \ 556 "hdd_bay0", "hdd_bay1", \ 557 "hdd_bay2", "hdd_bay3", \ 558 "memory_card_a_proximity0", \ 559 "memory_card_a_proximity1", \ 560 "memory_card_a_proximity2", \ 561 "memory_card_b_proximity0", \ 562 "memory_card_b_proximity1", \ 563 "memory_card_b_proximity2", \ 564 "memory_card_a_slot0", \ 565 "memory_card_a_slot1", \ 566 "memory_card_a_slot2", \ 567 "memory_card_a_slot3", \ 568 "memory_card_b_slot0", \ 569 "memory_card_b_slot1", \ 570 "memory_card_b_slot2", \ 571 "memory_card_b_slot3", \ 572 "mch_heatsink", "expansion_slots", \ 573 "power_supply_loc0", "power_supply_loc1", \ 574 "Tv0S", "Tv1S", } 575 576 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \ 577 "CPU A Heatsink", "CPU B Heatsink", \ 578 "CPU A Proximity", \ 579 "CPU Core 1", "CPU Core 2", \ 580 "CPU Core 3", "CPU Core 4", "THTG", \ 581 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 582 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 583 "Memory Riser A, Proximity 1", \ 584 "Memory Riser A, Proximity 2", \ 585 "Memory Riser A, Proximity 3", \ 586 "Memory Riser B, Proximity 1", \ 587 "Memory Riser B, Proximity 2", \ 588 "Memory Riser B, Proximity 3", \ 589 "Memory Riser A, Slot 1", \ 590 "Memory Riser A, Slot 2", \ 591 "Memory Riser A, Slot 3", \ 592 "Memory Riser A, Slot 4", \ 593 "Memory Riser B, Slot 1", \ 594 "Memory Riser B, Slot 2", \ 595 "Memory Riser B, Slot 3", \ 596 "Memory Riser B, Slot 4", \ 597 "MCH Heatsink", "Expansion Slots", \ 598 "Power Supply, Location 1", \ 599 "Power Supply, Location 2", \ 600 "Tv0S", "Tv1S", } 601 602 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 603 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 604 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 605 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 606 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 607 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 608 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 609 NULL } 610 611 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 612 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 613 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 614 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 615 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 616 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 617 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 618 619 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 620 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 621 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 622 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 623 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 624 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 625 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 626 627 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 628 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 629 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 630 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 631 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 632 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 633 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 634 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 635 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 636 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 637 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 638 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 639 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 640 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 641 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 642 NULL } 643 644 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 645 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 646 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 647 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 648 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 649 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 650 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 651 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 652 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 653 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 654 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 655 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 656 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 657 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 658 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 659 660 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 661 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 662 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 663 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 664 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 665 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 666 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 667 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 668 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 669 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 670 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 671 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 672 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 673 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 674 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 675 676 #define ASMC_MP6_TEMPS { "TA0P", "TA1P", "TC0P", "TG0D", "TG0P", \ 677 "TG1D", "TG1P", "TM0P", "TM1P", NULL } 678 679 #define ASMC_MP6_TEMPNAMES { "ambient_air_1", "ambient_air_2", \ 680 "cpu_proximity", "gpu_diode_1", \ 681 "gpu_proximity_1", "gpu_diode_2", \ 682 "gpu_proximity_2", "mem_proximity_1", \ 683 "mem_proximity_2" } 684 685 #define ASMC_MP6_TEMPDESCS { "Ambient Air 1", "Ambient Air 2", \ 686 "CPU Proximity", "GPU Diode 1", \ 687 "GPU Proximity 1", "GPU Diode 2", \ 688 "GPU Proximity 2", "Memory Bank A", \ 689 "Memory Bank B" } 690 691 #define ASMC_MBA_TEMPS { "TB0T", NULL } 692 #define ASMC_MBA_TEMPNAMES { "enclosure" } 693 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 694 695 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 696 "TC0D", "TC0E", "TC0P", NULL } 697 698 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 699 "TC0D", "TC0E", "TC0P" } 700 701 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 702 "TC0D", "TC0E", "TC0P" } 703 704 #define ASMC_MBA4_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 705 "TC0D", "TC0E", "TC0F", "TC0P", \ 706 "TC1C", "TC2C", "TCGC", "TCSA", \ 707 "TH0F", "TH0J", "TH0O", "TH0o", \ 708 "TM0P", "TPCD", "Ta0P", "Th1H", \ 709 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 710 NULL } 711 712 #define ASMC_MBA4_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TC0C", \ 713 "TC0D", "TC0E", "TC0F", "TC0P", \ 714 "TC1C", "TC2C", "TCGC", "TCSA", \ 715 "TH0F", "TH0J", "TH0O", "TH0o", \ 716 "TM0P", "TPCD", "Ta0P", "Th1H", \ 717 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 718 NULL } 719 720 #define ASMC_MBA4_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TC0C", \ 721 "TC0D", "TC0E", "TC0F", "TC0P", \ 722 "TC1C", "TC2C", "TCGC", "TCSA", \ 723 "TH0F", "TH0J", "TH0O", "TH0o", \ 724 "TM0P", "TPCD", "Ta0P", "Th1H", \ 725 "Tm0P", "Tm1P", "Ts0P", "Ts0S", \ 726 NULL } 727 728 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 729 "TC0D", "TC0E", "TC0F", "TC0P", \ 730 "TC1C", "TC2C", "TCGC", "TCSA", \ 731 "TCXC", "THSP", "TM0P", "TPCD", \ 732 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 733 "Ts0P", "Ts0S", NULL } 734 735 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 736 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 737 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 738 "TCXC", "THSP", "memorybank", "pchdie", \ 739 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 740 "palmrest", "memoryproximity" } 741 742 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 743 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 744 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 745 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 746 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 747 "Palm Rest", "Memory Proximity" } 748 749 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \ 750 "TC0E", "TC0F", "TC0P", \ 751 "TC1C", "TC2C", \ 752 "TCGC", "TCSA", "TCXC", \ 753 "THSP", "TM0P", "TPCD", \ 754 "TW0P" "Ta0P", "Th1H", \ 755 "Tm0P", "Ts0P", "Ts0S", NULL } 756 757 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 758 "cputemp1", "cputemp2", "cpuproximity", \ 759 "cpucore1", "cpucore2", \ 760 "pecigpu", "pecisa", "pecicpu", \ 761 "thunderboltproximity", "memorybank", "pchdie", \ 762 "wirelessproximity", "airflowproximity", "heatpipe", \ 763 "mainboardproximity", "palmrest", "memoryproximity" } 764 765 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 766 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 767 "CPU Core 1", "CPU Core 2", \ 768 "PECI GPU", "PECI SA", "PECI CPU", \ 769 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \ 770 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \ 771 "Mainboard Proximity", "Palm Rest", "Memory Proximity" } 772