1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx
31 * southbridges.
32 * Please see the following specifications for the descriptions of the
33 * registers and flags:
34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG)
35 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf
36 * - AMD SB700/710/750 Register Reference Guide (RRG)
37 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf
38 * - AMD SB700/710/750 Register Programming Requirements (RPR)
39 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf
40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG)
41 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf
42 * Please see the following for Watchdog Resource Table specification:
43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT)
44 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx
45 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above
46 * specifications, but the table hasn't been spotted in the wild yet.
47 */
48
49 #include <sys/cdefs.h>
50 #include "opt_amdsbwd.h"
51
52 #include <sys/param.h>
53 #include <sys/eventhandler.h>
54 #include <sys/kernel.h>
55 #include <sys/module.h>
56 #include <sys/systm.h>
57 #include <sys/sysctl.h>
58 #include <sys/bus.h>
59 #include <machine/bus.h>
60 #include <sys/rman.h>
61 #include <machine/cputypes.h>
62 #include <machine/md_var.h>
63 #include <machine/resource.h>
64 #include <sys/watchdog.h>
65
66 #include <dev/pci/pcivar.h>
67 #include <dev/amdsbwd/amd_chipset.h>
68 #include <isa/isavar.h>
69
70 /*
71 * Registers in the Watchdog IO space.
72 * See SB7xx RRG 2.3.4, WDRT.
73 */
74 #define AMDSB_WD_CTRL 0x00
75 #define AMDSB_WD_RUN 0x01
76 #define AMDSB_WD_FIRED 0x02
77 #define AMDSB_WD_SHUTDOWN 0x04
78 #define AMDSB_WD_DISABLE 0x08
79 #define AMDSB_WD_RESERVED 0x70
80 #define AMDSB_WD_RELOAD 0x80
81 #define AMDSB_WD_COUNT 0x04
82 #define AMDSB_WD_COUNT_MASK 0xffff
83 #define AMDSB_WDIO_REG_WIDTH 4
84
85 #define amdsbwd_verbose_printf(dev, ...) \
86 do { \
87 if (bootverbose) \
88 device_printf(dev, __VA_ARGS__);\
89 } while (0)
90
91 struct amdsbwd_softc {
92 device_t dev;
93 eventhandler_tag ev_tag;
94 struct resource *res_ctrl;
95 struct resource *res_count;
96 int rid_ctrl;
97 int rid_count;
98 int ms_per_tick;
99 int max_ticks;
100 int active;
101 unsigned int timeout;
102 };
103
104 static void amdsbwd_identify(driver_t *driver, device_t parent);
105 static int amdsbwd_probe(device_t dev);
106 static int amdsbwd_attach(device_t dev);
107 static int amdsbwd_detach(device_t dev);
108 static int amdsbwd_suspend(device_t dev);
109 static int amdsbwd_resume(device_t dev);
110
111 static device_method_t amdsbwd_methods[] = {
112 DEVMETHOD(device_identify, amdsbwd_identify),
113 DEVMETHOD(device_probe, amdsbwd_probe),
114 DEVMETHOD(device_attach, amdsbwd_attach),
115 DEVMETHOD(device_detach, amdsbwd_detach),
116 DEVMETHOD(device_suspend, amdsbwd_suspend),
117 DEVMETHOD(device_resume, amdsbwd_resume),
118 #if 0
119 DEVMETHOD(device_shutdown, amdsbwd_detach),
120 #endif
121 DEVMETHOD_END
122 };
123
124 static devclass_t amdsbwd_devclass;
125 static driver_t amdsbwd_driver = {
126 "amdsbwd",
127 amdsbwd_methods,
128 sizeof(struct amdsbwd_softc)
129 };
130
131 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL);
132
133 static uint8_t
pmio_read(struct resource * res,uint8_t reg)134 pmio_read(struct resource *res, uint8_t reg)
135 {
136 bus_write_1(res, 0, reg); /* Index */
137 return (bus_read_1(res, 1)); /* Data */
138 }
139
140 static void
pmio_write(struct resource * res,uint8_t reg,uint8_t val)141 pmio_write(struct resource *res, uint8_t reg, uint8_t val)
142 {
143 bus_write_1(res, 0, reg); /* Index */
144 bus_write_1(res, 1, val); /* Data */
145 }
146
147 static uint32_t
wdctrl_read(struct amdsbwd_softc * sc)148 wdctrl_read(struct amdsbwd_softc *sc)
149 {
150 return (bus_read_4(sc->res_ctrl, 0));
151 }
152
153 static void
wdctrl_write(struct amdsbwd_softc * sc,uint32_t val)154 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val)
155 {
156 bus_write_4(sc->res_ctrl, 0, val);
157 }
158
159 static __unused uint32_t
wdcount_read(struct amdsbwd_softc * sc)160 wdcount_read(struct amdsbwd_softc *sc)
161 {
162 return (bus_read_4(sc->res_count, 0));
163 }
164
165 static void
wdcount_write(struct amdsbwd_softc * sc,uint32_t val)166 wdcount_write(struct amdsbwd_softc *sc, uint32_t val)
167 {
168 bus_write_4(sc->res_count, 0, val);
169 }
170
171 static void
amdsbwd_tmr_enable(struct amdsbwd_softc * sc)172 amdsbwd_tmr_enable(struct amdsbwd_softc *sc)
173 {
174 uint32_t val;
175
176 val = wdctrl_read(sc);
177 val |= AMDSB_WD_RUN;
178 wdctrl_write(sc, val);
179 sc->active = 1;
180 amdsbwd_verbose_printf(sc->dev, "timer enabled\n");
181 }
182
183 static void
amdsbwd_tmr_disable(struct amdsbwd_softc * sc)184 amdsbwd_tmr_disable(struct amdsbwd_softc *sc)
185 {
186 uint32_t val;
187
188 val = wdctrl_read(sc);
189 val &= ~AMDSB_WD_RUN;
190 wdctrl_write(sc, val);
191 sc->active = 0;
192 amdsbwd_verbose_printf(sc->dev, "timer disabled\n");
193 }
194
195 static void
amdsbwd_tmr_reload(struct amdsbwd_softc * sc)196 amdsbwd_tmr_reload(struct amdsbwd_softc *sc)
197 {
198 uint32_t val;
199
200 val = wdctrl_read(sc);
201 val |= AMDSB_WD_RELOAD;
202 wdctrl_write(sc, val);
203 }
204
205 static void
amdsbwd_tmr_set(struct amdsbwd_softc * sc,uint16_t timeout)206 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout)
207 {
208
209 timeout &= AMDSB_WD_COUNT_MASK;
210 wdcount_write(sc, timeout);
211 sc->timeout = timeout;
212 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout);
213 }
214
215 static void
amdsbwd_event(void * arg,unsigned int cmd,int * error)216 amdsbwd_event(void *arg, unsigned int cmd, int *error)
217 {
218 struct amdsbwd_softc *sc = arg;
219 uint64_t timeout;
220
221 if (cmd != 0) {
222 timeout = 0;
223 cmd &= WD_INTERVAL;
224 if (cmd >= WD_TO_1MS) {
225 timeout = (uint64_t)1 << (cmd - WD_TO_1MS);
226 timeout = timeout / sc->ms_per_tick;
227 }
228 /* For a too short timeout use 1 tick. */
229 if (timeout == 0)
230 timeout = 1;
231 /* For a too long timeout stop the timer. */
232 if (timeout > sc->max_ticks)
233 timeout = 0;
234 } else {
235 timeout = 0;
236 }
237
238 if (timeout != 0) {
239 if (timeout != sc->timeout)
240 amdsbwd_tmr_set(sc, timeout);
241 if (!sc->active)
242 amdsbwd_tmr_enable(sc);
243 amdsbwd_tmr_reload(sc);
244 *error = 0;
245 } else {
246 if (sc->active)
247 amdsbwd_tmr_disable(sc);
248 }
249 }
250
251 static void
amdsbwd_identify(driver_t * driver,device_t parent)252 amdsbwd_identify(driver_t *driver, device_t parent)
253 {
254 device_t child;
255 device_t smb_dev;
256
257 if (resource_disabled("amdsbwd", 0))
258 return;
259 if (device_find_child(parent, "amdsbwd", -1) != NULL)
260 return;
261
262 /*
263 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device
264 * that should be present at bus 0, device 20, function 0.
265 */
266 smb_dev = pci_find_bsf(0, 20, 0);
267 if (smb_dev == NULL)
268 return;
269 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID &&
270 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID &&
271 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID &&
272 pci_get_devid(smb_dev) != HYGONCZ_SMBUS_DEVID)
273 return;
274
275 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1);
276 if (child == NULL)
277 device_printf(parent, "add amdsbwd child failed\n");
278 }
279
280 static void
amdsbwd_probe_sb7xx(device_t dev,struct resource * pmres,uint32_t * addr)281 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr)
282 {
283 uint8_t val;
284 int i;
285
286 /* Report cause of previous reset for user's convenience. */
287 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
288 if (val != 0)
289 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
290 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
291 if (val != 0)
292 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
293 if ((val & AMDSB_WD_RST_STS) != 0)
294 device_printf(dev, "Previous Reset was caused by Watchdog\n");
295
296 /* Find base address of memory mapped WDT registers. */
297 for (*addr = 0, i = 0; i < 4; i++) {
298 *addr <<= 8;
299 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i);
300 }
301 *addr &= ~0x07u;
302
303 /* Set watchdog timer tick to 1s. */
304 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
305 val &= ~AMDSB_WDT_RES_MASK;
306 val |= AMDSB_WDT_RES_1S;
307 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
308
309 /* Enable watchdog device (in stopped state). */
310 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
311 val &= ~AMDSB_WDT_DISABLE;
312 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
313
314 /*
315 * XXX TODO: Ensure that watchdog decode is enabled
316 * (register 0x41, bit 3).
317 */
318 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer");
319 }
320
321 static void
amdsbwd_probe_sb8xx(device_t dev,struct resource * pmres,uint32_t * addr)322 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
323 {
324 uint32_t val;
325 int i;
326
327 /* Report cause of previous reset for user's convenience. */
328
329 val = pmio_read(pmres, AMDSB8_PM_RESET_CTRL);
330 if ((val & AMDSB8_RST_STS_DIS) != 0) {
331 val &= ~AMDSB8_RST_STS_DIS;
332 pmio_write(pmres, AMDSB8_PM_RESET_CTRL, val);
333 }
334 val = 0;
335 for (i = 3; i >= 0; i--) {
336 val <<= 8;
337 val |= pmio_read(pmres, AMDSB8_PM_RESET_STATUS + i);
338 }
339 if (val != 0)
340 amdsbwd_verbose_printf(dev, "ResetStatus = 0x%08x\n", val);
341 if ((val & AMDSB8_WD_RST_STS) != 0)
342 device_printf(dev, "Previous Reset was caused by Watchdog\n");
343
344 /* Find base address of memory mapped WDT registers. */
345 for (*addr = 0, i = 0; i < 4; i++) {
346 *addr <<= 8;
347 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i);
348 }
349 *addr &= ~0x07u;
350
351 /* Set watchdog timer tick to 1s. */
352 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
353 val &= ~AMDSB8_WDT_RES_MASK;
354 val |= AMDSB8_WDT_1HZ;
355 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
356 #ifdef AMDSBWD_DEBUG
357 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
358 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val);
359 #endif
360
361 /*
362 * Enable watchdog device (in stopped state)
363 * and decoding of its address.
364 */
365 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
366 val &= ~AMDSB8_WDT_DISABLE;
367 val |= AMDSB8_WDT_DEC_EN;
368 pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
369 #ifdef AMDSBWD_DEBUG
370 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
371 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val);
372 #endif
373 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer");
374 }
375
376 static void
amdsbwd_probe_fch41(device_t dev,struct resource * pmres,uint32_t * addr)377 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr)
378 {
379 uint8_t val;
380 char buf[36];
381
382 /*
383 * Enable decoding of watchdog MMIO address.
384 */
385 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
386 val |= AMDFCH41_WDT_EN;
387 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
388 #ifdef AMDSBWD_DEBUG
389 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
390 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", val);
391 #endif
392
393 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
394 if ((val & AMDFCH41_MMIO_EN) != 0) {
395 /* Fixed offset for the watchdog within ACPI MMIO range. */
396 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n");
397 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF;
398 } else {
399 /* Special fixed MMIO range for the watchdog. */
400 *addr = AMDFCH41_WDT_FIXED_ADDR;
401 }
402
403 /*
404 * Set watchdog timer tick to 1s and
405 * enable the watchdog device (in stopped state).
406 */
407 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
408 val &= ~AMDFCH41_WDT_RES_MASK;
409 val |= AMDFCH41_WDT_RES_1S;
410 val &= ~AMDFCH41_WDT_EN_MASK;
411 val |= AMDFCH41_WDT_ENABLE;
412 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val);
413 #ifdef AMDSBWD_DEBUG
414 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
415 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n",
416 val);
417 #endif
418 snprintf(buf, sizeof(buf), "%s FCH Rev 41h+ Watchdog Timer",
419 cpu_vendor_id == CPU_VENDOR_HYGON ? "Hygon" : "AMD");
420 device_set_desc_copy(dev, buf);
421 }
422
423 static int
amdsbwd_probe(device_t dev)424 amdsbwd_probe(device_t dev)
425 {
426 struct resource *res;
427 device_t smb_dev;
428 uint32_t addr;
429 int rid;
430 int rc;
431 uint32_t devid;
432 uint8_t revid;
433
434 /* Do not claim some ISA PnP device by accident. */
435 if (isa_get_logicalid(dev) != 0)
436 return (ENXIO);
437
438 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
439 AMDSB_PMIO_WIDTH);
440 if (rc != 0) {
441 device_printf(dev, "bus_set_resource for IO failed\n");
442 return (ENXIO);
443 }
444 rid = 0;
445 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
446 RF_ACTIVE | RF_SHAREABLE);
447 if (res == NULL) {
448 device_printf(dev, "bus_alloc_resource for IO failed\n");
449 return (ENXIO);
450 }
451
452 smb_dev = pci_find_bsf(0, 20, 0);
453 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n"));
454 devid = pci_get_devid(smb_dev);
455 revid = pci_get_revid(smb_dev);
456 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID)
457 amdsbwd_probe_sb7xx(dev, res, &addr);
458 else if (devid == AMDSB_SMBUS_DEVID ||
459 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
460 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID))
461 amdsbwd_probe_sb8xx(dev, res, &addr);
462 else
463 amdsbwd_probe_fch41(dev, res, &addr);
464
465 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
466 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
467
468 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr);
469 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL,
470 AMDSB_WDIO_REG_WIDTH);
471 if (rc != 0) {
472 device_printf(dev, "bus_set_resource for control failed\n");
473 return (ENXIO);
474 }
475 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT,
476 AMDSB_WDIO_REG_WIDTH);
477 if (rc != 0) {
478 device_printf(dev, "bus_set_resource for count failed\n");
479 return (ENXIO);
480 }
481
482 return (0);
483 }
484
485 static int
amdsbwd_attach_sb(device_t dev,struct amdsbwd_softc * sc)486 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc)
487 {
488
489 sc->max_ticks = UINT16_MAX;
490 sc->rid_ctrl = 0;
491 sc->rid_count = 1;
492
493 sc->ms_per_tick = 1000;
494
495 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
496 &sc->rid_ctrl, RF_ACTIVE);
497 if (sc->res_ctrl == NULL) {
498 device_printf(dev, "bus_alloc_resource for ctrl failed\n");
499 return (ENXIO);
500 }
501 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
502 &sc->rid_count, RF_ACTIVE);
503 if (sc->res_count == NULL) {
504 device_printf(dev, "bus_alloc_resource for count failed\n");
505 return (ENXIO);
506 }
507 return (0);
508 }
509
510 static int
amdsbwd_attach(device_t dev)511 amdsbwd_attach(device_t dev)
512 {
513 struct amdsbwd_softc *sc;
514 int rc;
515
516 sc = device_get_softc(dev);
517 sc->dev = dev;
518
519 rc = amdsbwd_attach_sb(dev, sc);
520 if (rc != 0)
521 goto fail;
522
523 #ifdef AMDSBWD_DEBUG
524 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc));
525 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc));
526 #endif
527
528 /* Setup initial state of Watchdog Control. */
529 wdctrl_write(sc, AMDSB_WD_FIRED);
530
531 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) {
532 device_printf(dev, "watchdog hardware is disabled\n");
533 goto fail;
534 }
535
536 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc,
537 EVENTHANDLER_PRI_ANY);
538
539 return (0);
540
541 fail:
542 amdsbwd_detach(dev);
543 return (ENXIO);
544 }
545
546 static int
amdsbwd_detach(device_t dev)547 amdsbwd_detach(device_t dev)
548 {
549 struct amdsbwd_softc *sc;
550
551 sc = device_get_softc(dev);
552 if (sc->ev_tag != NULL)
553 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
554
555 if (sc->active)
556 amdsbwd_tmr_disable(sc);
557
558 if (sc->res_ctrl != NULL)
559 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl,
560 sc->res_ctrl);
561
562 if (sc->res_count != NULL)
563 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count,
564 sc->res_count);
565
566 return (0);
567 }
568
569 static int
amdsbwd_suspend(device_t dev)570 amdsbwd_suspend(device_t dev)
571 {
572 struct amdsbwd_softc *sc;
573 uint32_t val;
574
575 sc = device_get_softc(dev);
576 val = wdctrl_read(sc);
577 val &= ~AMDSB_WD_RUN;
578 wdctrl_write(sc, val);
579 return (0);
580 }
581
582 static int
amdsbwd_resume(device_t dev)583 amdsbwd_resume(device_t dev)
584 {
585 struct amdsbwd_softc *sc;
586
587 sc = device_get_softc(dev);
588 wdctrl_write(sc, AMDSB_WD_FIRED);
589 if (sc->active) {
590 amdsbwd_tmr_set(sc, sc->timeout);
591 amdsbwd_tmr_enable(sc);
592 amdsbwd_tmr_reload(sc);
593 }
594 return (0);
595 }
596