1 /*-
2 * Interface for the 93C66/56/46/26/06 serial eeprom parts.
3 *
4 * Copyright (c) 1995, 1996 Daniel M. Eischen
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL").
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $
32 */
33
34 /*
35 * The instruction set of the 93C66/56/46/26/06 chips are as follows:
36 *
37 * Start OP *
38 * Function Bit Code Address** Data Description
39 * -------------------------------------------------------------------
40 * READ 1 10 A5 - A0 Reads data stored in memory,
41 * starting at specified address
42 * EWEN 1 00 11XXXX Write enable must precede
43 * all programming modes
44 * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0
45 * WRITE 1 01 A5 - A0 D15 - D0 Writes register
46 * ERAL 1 00 10XXXX Erase all registers
47 * WRAL 1 00 01XXXX D15 - D0 Writes to all registers
48 * EWDS 1 00 00XXXX Disables all programming
49 * instructions
50 * *Note: A value of X for address is a don't care condition.
51 * **Note: There are 8 address bits for the 93C56/66 chips unlike
52 * the 93C46/26/06 chips which have 6 address bits.
53 *
54 * The 93C46 has a four wire interface: clock, chip select, data in, and
55 * data out. In order to perform one of the above functions, you need
56 * to enable the chip select for a clock period (typically a minimum of
57 * 1 usec, with the clock high and low a minimum of 750 and 250 nsec
58 * respectively). While the chip select remains high, you can clock in
59 * the instructions (above) starting with the start bit, followed by the
60 * OP code, Address, and Data (if needed). For the READ instruction, the
61 * requested 16-bit register contents is read from the data out line but
62 * is preceded by an initial zero (leading 0, followed by 16-bits, MSB
63 * first). The clock cycling from low to high initiates the next data
64 * bit to be sent from the chip.
65 */
66
67 #ifdef __linux__
68 #include "aic7xxx_osm.h"
69 #include "aic7xxx_inline.h"
70 #include "aic7xxx_93cx6.h"
71 #else
72 #include <sys/cdefs.h>
73 #include <dev/aic7xxx/aic7xxx_osm.h>
74 #include <dev/aic7xxx/aic7xxx_inline.h>
75 #include <dev/aic7xxx/aic7xxx_93cx6.h>
76 #endif
77
78 /*
79 * Right now, we only have to read the SEEPROM. But we make it easier to
80 * add other 93Cx6 functions.
81 */
82 struct seeprom_cmd {
83 uint8_t len;
84 uint8_t bits[11];
85 };
86
87 /* Short opcodes for the c46 */
88 static struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
89 static struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
90
91 /* Long opcodes for the C56/C66 */
92 static struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
93 static struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
94
95 /* Common opcodes */
96 static struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
97 static struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
98
99 /*
100 * Wait for the SEERDY to go high; about 800 ns.
101 */
102 #define CLOCK_PULSE(sd, rdy) \
103 while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \
104 ; /* Do nothing */ \
105 } \
106 (void)SEEPROM_INB(sd); /* Clear clock */
107
108 /*
109 * Send a START condition and the given command
110 */
111 static void
send_seeprom_cmd(struct seeprom_descriptor * sd,struct seeprom_cmd * cmd)112 send_seeprom_cmd(struct seeprom_descriptor *sd, struct seeprom_cmd *cmd)
113 {
114 uint8_t temp;
115 int i = 0;
116
117 /* Send chip select for one clock cycle. */
118 temp = sd->sd_MS ^ sd->sd_CS;
119 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
120 CLOCK_PULSE(sd, sd->sd_RDY);
121
122 for (i = 0; i < cmd->len; i++) {
123 if (cmd->bits[i] != 0)
124 temp ^= sd->sd_DO;
125 SEEPROM_OUTB(sd, temp);
126 CLOCK_PULSE(sd, sd->sd_RDY);
127 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
128 CLOCK_PULSE(sd, sd->sd_RDY);
129 if (cmd->bits[i] != 0)
130 temp ^= sd->sd_DO;
131 }
132 }
133
134 /*
135 * Clear CS put the chip in the reset state, where it can wait for new commands.
136 */
137 static void
reset_seeprom(struct seeprom_descriptor * sd)138 reset_seeprom(struct seeprom_descriptor *sd)
139 {
140 uint8_t temp;
141
142 temp = sd->sd_MS;
143 SEEPROM_OUTB(sd, temp);
144 CLOCK_PULSE(sd, sd->sd_RDY);
145 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
146 CLOCK_PULSE(sd, sd->sd_RDY);
147 SEEPROM_OUTB(sd, temp);
148 CLOCK_PULSE(sd, sd->sd_RDY);
149 }
150
151 /*
152 * Read the serial EEPROM and returns 1 if successful and 0 if
153 * not successful.
154 */
155 int
ahc_read_seeprom(struct seeprom_descriptor * sd,uint16_t * buf,u_int start_addr,u_int count)156 ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
157 u_int start_addr, u_int count)
158 {
159 int i = 0;
160 u_int k = 0;
161 uint16_t v;
162 uint8_t temp;
163
164 /*
165 * Read the requested registers of the seeprom. The loop
166 * will range from 0 to count-1.
167 */
168 for (k = start_addr; k < count + start_addr; k++) {
169 /*
170 * Now we're ready to send the read command followed by the
171 * address of the 16-bit register we want to read.
172 */
173 send_seeprom_cmd(sd, &seeprom_read);
174
175 /* Send the 6 or 8 bit address (MSB first, LSB last). */
176 temp = sd->sd_MS ^ sd->sd_CS;
177 for (i = (sd->sd_chip - 1); i >= 0; i--) {
178 if ((k & (1 << i)) != 0)
179 temp ^= sd->sd_DO;
180 SEEPROM_OUTB(sd, temp);
181 CLOCK_PULSE(sd, sd->sd_RDY);
182 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
183 CLOCK_PULSE(sd, sd->sd_RDY);
184 if ((k & (1 << i)) != 0)
185 temp ^= sd->sd_DO;
186 }
187
188 /*
189 * Now read the 16 bit register. An initial 0 precedes the
190 * register contents which begins with bit 15 (MSB) and ends
191 * with bit 0 (LSB). The initial 0 will be shifted off the
192 * top of our word as we let the loop run from 0 to 16.
193 */
194 v = 0;
195 for (i = 16; i >= 0; i--) {
196 SEEPROM_OUTB(sd, temp);
197 CLOCK_PULSE(sd, sd->sd_RDY);
198 v <<= 1;
199 if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
200 v |= 1;
201 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
202 CLOCK_PULSE(sd, sd->sd_RDY);
203 }
204
205 buf[k - start_addr] = v;
206
207 /* Reset the chip select for the next command cycle. */
208 reset_seeprom(sd);
209 }
210 #ifdef AHC_DUMP_EEPROM
211 printf("\nSerial EEPROM:\n\t");
212 for (k = 0; k < count; k = k + 1) {
213 if (((k % 8) == 0) && (k != 0)) {
214 printf ("\n\t");
215 }
216 printf (" 0x%x", buf[k]);
217 }
218 printf ("\n");
219 #endif
220 return (1);
221 }
222
223 /*
224 * Write the serial EEPROM and return 1 if successful and 0 if
225 * not successful.
226 */
227 int
ahc_write_seeprom(struct seeprom_descriptor * sd,uint16_t * buf,u_int start_addr,u_int count)228 ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
229 u_int start_addr, u_int count)
230 {
231 struct seeprom_cmd *ewen, *ewds;
232 uint16_t v;
233 uint8_t temp;
234 int i, k;
235
236 /* Place the chip into write-enable mode */
237 if (sd->sd_chip == C46) {
238 ewen = &seeprom_ewen;
239 ewds = &seeprom_ewds;
240 } else if (sd->sd_chip == C56_66) {
241 ewen = &seeprom_long_ewen;
242 ewds = &seeprom_long_ewds;
243 } else {
244 printf("ahc_write_seeprom: unsupported seeprom type %d\n",
245 sd->sd_chip);
246 return (0);
247 }
248
249 send_seeprom_cmd(sd, ewen);
250 reset_seeprom(sd);
251
252 /* Write all requested data out to the seeprom. */
253 temp = sd->sd_MS ^ sd->sd_CS;
254 for (k = start_addr; k < count + start_addr; k++) {
255 /* Send the write command */
256 send_seeprom_cmd(sd, &seeprom_write);
257
258 /* Send the 6 or 8 bit address (MSB first). */
259 for (i = (sd->sd_chip - 1); i >= 0; i--) {
260 if ((k & (1 << i)) != 0)
261 temp ^= sd->sd_DO;
262 SEEPROM_OUTB(sd, temp);
263 CLOCK_PULSE(sd, sd->sd_RDY);
264 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
265 CLOCK_PULSE(sd, sd->sd_RDY);
266 if ((k & (1 << i)) != 0)
267 temp ^= sd->sd_DO;
268 }
269
270 /* Write the 16 bit value, MSB first */
271 v = buf[k - start_addr];
272 for (i = 15; i >= 0; i--) {
273 if ((v & (1 << i)) != 0)
274 temp ^= sd->sd_DO;
275 SEEPROM_OUTB(sd, temp);
276 CLOCK_PULSE(sd, sd->sd_RDY);
277 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
278 CLOCK_PULSE(sd, sd->sd_RDY);
279 if ((v & (1 << i)) != 0)
280 temp ^= sd->sd_DO;
281 }
282
283 /* Wait for the chip to complete the write */
284 temp = sd->sd_MS;
285 SEEPROM_OUTB(sd, temp);
286 CLOCK_PULSE(sd, sd->sd_RDY);
287 temp = sd->sd_MS ^ sd->sd_CS;
288 do {
289 SEEPROM_OUTB(sd, temp);
290 CLOCK_PULSE(sd, sd->sd_RDY);
291 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
292 CLOCK_PULSE(sd, sd->sd_RDY);
293 } while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0);
294
295 reset_seeprom(sd);
296 }
297
298 /* Put the chip back into write-protect mode */
299 send_seeprom_cmd(sd, ewds);
300 reset_seeprom(sd);
301
302 return (1);
303 }
304
305 int
ahc_verify_cksum(struct seeprom_config * sc)306 ahc_verify_cksum(struct seeprom_config *sc)
307 {
308 int i;
309 int maxaddr;
310 uint32_t checksum;
311 uint16_t *scarray;
312
313 maxaddr = (sizeof(*sc)/2) - 1;
314 checksum = 0;
315 scarray = (uint16_t *)sc;
316
317 for (i = 0; i < maxaddr; i++)
318 checksum = checksum + scarray[i];
319 if (checksum == 0
320 || (checksum & 0xFFFF) != sc->checksum) {
321 return (0);
322 } else {
323 return(1);
324 }
325 }
326