1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018-2021 Emmanuel Vadot <manu@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/rman.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <machine/bus.h>
36
37 #include <dev/fdt/simplebus.h>
38
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41
42 #include <dev/extres/clk/clk_div.h>
43 #include <dev/extres/clk/clk_fixed.h>
44 #include <dev/extres/clk/clk_mux.h>
45
46 #include <arm64/rockchip/clk/rk_cru.h>
47
48 #define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4)
49
50 /* Registers */
51 #define RK3328_GRF_SOC_CON4 0x410
52 #define RK3328_GRF_MAC_CON1 0x904
53 #define RK3328_GRF_MAC_CON2 0x908
54
55 /* Exported clocks */
56
57 #define PLL_APLL 1
58 #define PLL_DPLL 2
59 #define PLL_CPLL 3
60 #define PLL_GPLL 4
61 #define PLL_NPLL 5
62 #define ARMCLK 6
63
64 /* SCLK */
65 #define SCLK_RTC32K 30
66 #define SCLK_SDMMC_EXT 31
67 #define SCLK_SPI 32
68 #define SCLK_SDMMC 33
69 #define SCLK_SDIO 34
70 #define SCLK_EMMC 35
71 #define SCLK_TSADC 36
72 #define SCLK_SARADC 37
73 #define SCLK_UART0 38
74 #define SCLK_UART1 39
75 #define SCLK_UART2 40
76 #define SCLK_I2S0 41
77 #define SCLK_I2S1 42
78 #define SCLK_I2S2 43
79 #define SCLK_I2S1_OUT 44
80 #define SCLK_I2S2_OUT 45
81 #define SCLK_SPDIF 46
82 #define SCLK_TIMER0 47
83 #define SCLK_TIMER1 48
84 #define SCLK_TIMER2 49
85 #define SCLK_TIMER3 50
86 #define SCLK_TIMER4 51
87 #define SCLK_TIMER5 52
88 #define SCLK_WIFI 53
89 #define SCLK_CIF_OUT 54
90 #define SCLK_I2C0 55
91 #define SCLK_I2C1 56
92 #define SCLK_I2C2 57
93 #define SCLK_I2C3 58
94 #define SCLK_CRYPTO 59
95 #define SCLK_PWM 60
96 #define SCLK_PDM 61
97 #define SCLK_EFUSE 62
98 #define SCLK_OTP 63
99 #define SCLK_DDRCLK 64
100 #define SCLK_VDEC_CABAC 65
101 #define SCLK_VDEC_CORE 66
102 #define SCLK_VENC_DSP 67
103 #define SCLK_VENC_CORE 68
104 #define SCLK_RGA 69
105 #define SCLK_HDMI_SFC 70
106 #define SCLK_HDMI_CEC 71 /* Unused ? */
107 #define SCLK_USB3_REF 72
108 #define SCLK_USB3_SUSPEND 73
109 #define SCLK_SDMMC_DRV 74
110 #define SCLK_SDIO_DRV 75
111 #define SCLK_EMMC_DRV 76
112 #define SCLK_SDMMC_EXT_DRV 77
113 #define SCLK_SDMMC_SAMPLE 78
114 #define SCLK_SDIO_SAMPLE 79
115 #define SCLK_EMMC_SAMPLE 80
116 #define SCLK_SDMMC_EXT_SAMPLE 81
117 #define SCLK_VOP 82
118 #define SCLK_MAC2PHY_RXTX 83
119 #define SCLK_MAC2PHY_SRC 84
120 #define SCLK_MAC2PHY_REF 85
121 #define SCLK_MAC2PHY_OUT 86
122 #define SCLK_MAC2IO_RX 87
123 #define SCLK_MAC2IO_TX 88
124 #define SCLK_MAC2IO_REFOUT 89
125 #define SCLK_MAC2IO_REF 90
126 #define SCLK_MAC2IO_OUT 91
127 #define SCLK_TSP 92
128 #define SCLK_HSADC_TSP 93
129 #define SCLK_USB3PHY_REF 94
130 #define SCLK_REF_USB3OTG 95
131 #define SCLK_USB3OTG_REF 96
132 #define SCLK_USB3OTG_SUSPEND 97
133 #define SCLK_REF_USB3OTG_SRC 98
134 #define SCLK_MAC2IO_SRC 99
135 #define SCLK_MAC2IO 100
136 #define SCLK_MAC2PHY 101
137 #define SCLK_MAC2IO_EXT 102
138
139 /* DCLK */
140 #define DCLK_LCDC 120
141 #define DCLK_HDMIPHY 121
142 #define HDMIPHY 122
143 #define USB480M 123
144 #define DCLK_LCDC_SRC 124
145
146 /* ACLK */
147 #define ACLK_AXISRAM 130 /* Unused */
148 #define ACLK_VOP_PRE 131
149 #define ACLK_USB3OTG 132
150 #define ACLK_RGA_PRE 133
151 #define ACLK_DMAC 134 /* Unused */
152 #define ACLK_GPU 135
153 #define ACLK_BUS_PRE 136
154 #define ACLK_PERI_PRE 137
155 #define ACLK_RKVDEC_PRE 138
156 #define ACLK_RKVDEC 139
157 #define ACLK_RKVENC 140
158 #define ACLK_VPU_PRE 141
159 #define ACLK_VIO_PRE 142
160 #define ACLK_VPU 143
161 #define ACLK_VIO 144
162 #define ACLK_VOP 145
163 #define ACLK_GMAC 146
164 #define ACLK_H265 147
165 #define ACLK_H264 148
166 #define ACLK_MAC2PHY 149
167 #define ACLK_MAC2IO 150
168 #define ACLK_DCF 151
169 #define ACLK_TSP 152
170 #define ACLK_PERI 153
171 #define ACLK_RGA 154
172 #define ACLK_IEP 155
173 #define ACLK_CIF 156
174 #define ACLK_HDCP 157
175
176 /* PCLK */
177 #define PCLK_GPIO0 200
178 #define PCLK_GPIO1 201
179 #define PCLK_GPIO2 202
180 #define PCLK_GPIO3 203
181 #define PCLK_GRF 204
182 #define PCLK_I2C0 205
183 #define PCLK_I2C1 206
184 #define PCLK_I2C2 207
185 #define PCLK_I2C3 208
186 #define PCLK_SPI 209
187 #define PCLK_UART0 210
188 #define PCLK_UART1 211
189 #define PCLK_UART2 212
190 #define PCLK_TSADC 213
191 #define PCLK_PWM 214
192 #define PCLK_TIMER 215
193 #define PCLK_BUS_PRE 216
194 #define PCLK_PERI_PRE 217 /* Unused */
195 #define PCLK_HDMI_CTRL 218 /* Unused */
196 #define PCLK_HDMI_PHY 219 /* Unused */
197 #define PCLK_GMAC 220
198 #define PCLK_H265 221
199 #define PCLK_MAC2PHY 222
200 #define PCLK_MAC2IO 223
201 #define PCLK_USB3PHY_OTG 224
202 #define PCLK_USB3PHY_PIPE 225
203 #define PCLK_USB3_GRF 226
204 #define PCLK_USB2_GRF 227
205 #define PCLK_HDMIPHY 228
206 #define PCLK_DDR 229
207 #define PCLK_PERI 230
208 #define PCLK_HDMI 231
209 #define PCLK_HDCP 232
210 #define PCLK_DCF 233
211 #define PCLK_SARADC 234
212 #define PCLK_ACODECPHY 235
213 #define PCLK_WDT 236 /* Controlled from the secure GRF */
214
215 /* HCLK */
216 #define HCLK_PERI 308
217 #define HCLK_TSP 309
218 #define HCLK_GMAC 310 /* Unused */
219 #define HCLK_I2S0_8CH 311
220 #define HCLK_I2S1_8CH 312
221 #define HCLK_I2S2_2CH 313
222 #define HCLK_SPDIF_8CH 314
223 #define HCLK_VOP 315
224 #define HCLK_NANDC 316 /* Unused */
225 #define HCLK_SDMMC 317
226 #define HCLK_SDIO 318
227 #define HCLK_EMMC 319
228 #define HCLK_SDMMC_EXT 320
229 #define HCLK_RKVDEC_PRE 321
230 #define HCLK_RKVDEC 322
231 #define HCLK_RKVENC 323
232 #define HCLK_VPU_PRE 324
233 #define HCLK_VIO_PRE 325
234 #define HCLK_VPU 326
235 /* 327 doesn't exists */
236 #define HCLK_BUS_PRE 328
237 #define HCLK_PERI_PRE 329 /* Unused */
238 #define HCLK_H264 330
239 #define HCLK_CIF 331
240 #define HCLK_OTG_PMU 332
241 #define HCLK_OTG 333
242 #define HCLK_HOST0 334
243 #define HCLK_HOST0_ARB 335
244 #define HCLK_CRYPTO_MST 336
245 #define HCLK_CRYPTO_SLV 337
246 #define HCLK_PDM 338
247 #define HCLK_IEP 339
248 #define HCLK_RGA 340
249 #define HCLK_HDCP 341
250
251 static struct rk_cru_gate rk3328_gates[] = {
252 /* CRU_CLKGATE_CON0 */
253 CRU_GATE(0, "core_apll_clk", "apll", 0x200, 0)
254 CRU_GATE(0, "core_dpll_clk", "dpll", 0x200, 1)
255 CRU_GATE(0, "core_gpll_clk", "gpll", 0x200, 2)
256 /* Bit 3 bus_src_clk_en */
257 /* Bit 4 clk_ddrphy_src_en */
258 /* Bit 5 clk_ddrpd_src_en */
259 /* Bit 6 clk_ddrmon_en */
260 /* Bit 7-8 unused */
261 /* Bit 9 testclk_en */
262 CRU_GATE(SCLK_WIFI, "sclk_wifi", "sclk_wifi_c", 0x200, 10)
263 CRU_GATE(SCLK_RTC32K, "clk_rtc32k", "clk_rtc32k_c", 0x200, 11)
264 CRU_GATE(0, "core_npll_clk", "npll", 0x200, 12)
265 /* Bit 13-15 unused */
266
267 /* CRU_CLKGATE_CON1 */
268 /* Bit 0 unused */
269 CRU_GATE(0, "clk_i2s0_div", "clk_i2s0_div_c", 0x204, 1)
270 CRU_GATE(0, "clk_i2s0_frac", "clk_i2s0_frac_f", 0x204, 2)
271 CRU_GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 0x204, 3)
272 CRU_GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 0x204, 4)
273 CRU_GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_f", 0x204, 5)
274 CRU_GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", 0x204, 6)
275 CRU_GATE(0, "clk_i2s1_out", "clk_i2s1_mux", 0x204, 7)
276 CRU_GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 0x204, 8)
277 CRU_GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_f", 0x204, 9)
278 CRU_GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", 0x204, 10)
279 CRU_GATE(0, "clk_i2s2_out", "clk_i2s2_mux", 0x204, 11)
280 CRU_GATE(0, "clk_spdif_div", "clk_spdif_div_c", 0x204, 12)
281 CRU_GATE(0, "clk_spdif_frac", "clk_spdif_frac_f", 0x204, 13)
282 CRU_GATE(0, "clk_uart0_div", "clk_uart0_div_c", 0x204, 14)
283 CRU_GATE(0, "clk_uart0_frac", "clk_uart0_frac_f", 0x204, 15)
284
285 /* CRU_CLKGATE_CON2 */
286 CRU_GATE(0, "clk_uart1_div", "clk_uart1_div_c", 0x208, 0)
287 CRU_GATE(0, "clk_uart1_frac", "clk_uart1_frac_f", 0x208, 1)
288 CRU_GATE(0, "clk_uart2_div", "clk_uart2_div_c", 0x208, 2)
289 CRU_GATE(0, "clk_uart2_frac", "clk_uart2_frac_f", 0x208, 3)
290 CRU_GATE(SCLK_CRYPTO, "clk_crypto", "clk_crypto_c", 0x208, 4)
291 CRU_GATE(SCLK_TSP, "clk_tsp", "clk_tsp_c", 0x208, 5)
292 CRU_GATE(SCLK_TSADC, "clk_tsadc_src", "clk_tsadc_c", 0x208, 6)
293 CRU_GATE(SCLK_SPI, "clk_spi", "clk_spi_c", 0x208, 7)
294 CRU_GATE(SCLK_PWM, "clk_pwm", "clk_pwm_c", 0x208, 8)
295 CRU_GATE(SCLK_I2C0, "clk_i2c0_src", "clk_i2c0_c", 0x208, 9)
296 CRU_GATE(SCLK_I2C1, "clk_i2c1_src", "clk_i2c1_c", 0x208, 10)
297 CRU_GATE(SCLK_I2C2, "clk_i2c2_src", "clk_i2c2_c", 0x208, 11)
298 CRU_GATE(SCLK_I2C3, "clk_i2c3_src", "clk_i2c3_c", 0x208, 12)
299 CRU_GATE(SCLK_EFUSE, "clk_efuse", "clk_efuse_c", 0x208, 13)
300 CRU_GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 0x208, 14)
301 CRU_GATE(SCLK_PDM, "clk_pdm", "clk_pdm_c", 0x208, 15)
302
303 /* CRU_CLKGATE_CON3 */
304 CRU_GATE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", "clk_mac2phy_src_c", 0x20c, 0)
305 CRU_GATE(SCLK_MAC2IO_SRC, "clk_mac2io_src", "clk_mac2io_src_c", 0x20c, 1)
306 CRU_GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_c", 0x20c, 2)
307 /* Bit 3 gmac_gpll_src_en Unused ? */
308 /* Bit 4 gmac_vpll_src_en Unused ? */
309 CRU_GATE(SCLK_MAC2IO_OUT, "clk_mac2io_out", "clk_mac2io_out_c", 0x20c, 5)
310 /* Bit 6-7 unused */
311 CRU_GATE(SCLK_OTP, "clk_otp", "clk_otp_c", 0x20c, 8)
312 /* Bit 9-15 unused */
313
314 /* CRU_CLKGATE_CON4 */
315 CRU_GATE(0, "periph_gclk_src", "gpll", 0x210, 0)
316 CRU_GATE(0, "periph_cclk_src", "cpll", 0x210, 1)
317 CRU_GATE(0, "hdmiphy_peri", "hdmiphy", 0x210, 2)
318 CRU_GATE(SCLK_SDMMC, "clk_mmc0_src", "clk_sdmmc_c", 0x210, 3)
319 CRU_GATE(SCLK_SDIO, "clk_sdio_src", "clk_sdio_c", 0x210, 4)
320 CRU_GATE(SCLK_EMMC, "clk_emmc_src", "clk_emmc_c", 0x210, 5)
321 CRU_GATE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", "clk_ref_usb3otg_src_c", 0x210, 6)
322 CRU_GATE(SCLK_USB3OTG_REF, "clk_usb3_otg0_ref", "xin24m", 0x210, 7)
323 CRU_GATE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", "clk_usb3otg_suspend_c", 0x210, 8)
324 /* Bit 9 clk_usb3phy_ref_25m_en */
325 CRU_GATE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", "clk_sdmmc_ext_c", 0x210, 10)
326 /* Bit 11-15 unused */
327
328 /* CRU_CLKGATE_CON5 */
329 CRU_GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_c", 0x214, 0)
330 CRU_GATE(SCLK_RGA, "sclk_rga", "sclk_rga_c", 0x214, 0)
331 CRU_GATE(ACLK_VIO_PRE, "aclk_vio_pre", "aclk_vio_pre_c", 0x214, 2)
332 CRU_GATE(SCLK_CIF_OUT, "clk_cif_src", "clk_cif_src_c", 0x214, 3)
333 CRU_GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 0x214, 4)
334 CRU_GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 0x214, 5)
335 CRU_GATE(DCLK_LCDC_SRC, "vop_dclk_src", "vop_dclk_src_c", 0x214, 6)
336 /* Bit 7-15 unused */
337
338 /* CRU_CLKGATE_CON6 */
339 CRU_GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_c", 0x218, 0)
340 CRU_GATE(SCLK_VDEC_CABAC, "sclk_cabac", "sclk_cabac_c", 0x218, 1)
341 CRU_GATE(SCLK_VDEC_CORE, "sclk_vdec_core", "sclk_vdec_core_c", 0x218, 2)
342 CRU_GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_c", 0x218, 3)
343 CRU_GATE(SCLK_VENC_CORE, "sclk_venc", "sclk_venc_c", 0x218, 4)
344 CRU_GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 0x218, 5)
345 CRU_GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 0x218, 6)
346 CRU_GATE(SCLK_VENC_DSP, "sclk_venc_dsp", "sclk_venc_dsp_c", 0x218, 7)
347 /* Bit 8-15 unused */
348
349 /* CRU_CLKGATE_CON7 */
350 /* Bit 0 aclk_core_en */
351 /* Bit 1 clk_core_periph_en */
352 /* Bit 2 clk_jtag_en */
353 /* Bit 3 unused */
354 /* Bit 4 pclk_ddr_en */
355 /* Bit 5-15 unused */
356
357 /* CRU_CLKGATE_CON8 */
358 CRU_GATE(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_pre_c", 0x220, 0)
359 CRU_GATE(HCLK_BUS_PRE, "hclk_bus_pre", "hclk_bus_pre_c", 0x220, 1)
360 CRU_GATE(PCLK_BUS_PRE, "pclk_bus_pre", "pclk_bus_pre_c", 0x220, 2)
361 CRU_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3)
362 CRU_GATE(0, "pclk_phy", "pclk_bus_pre", 0x220, 4)
363 CRU_GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0x220, 5)
364 CRU_GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0x220, 6)
365 CRU_GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0x220, 7)
366 CRU_GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0x220, 8)
367 CRU_GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0x220, 9)
368 CRU_GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0x220, 10)
369 /* Bit 11-15 unused */
370
371 /* CRU_CLKGATE_CON9 */
372 CRU_GATE(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0x224, 0)
373 CRU_GATE(SCLK_MAC2PHY_RXTX, "clk_gmac2phy_rx", "clk_mac2phy", 0x224, 1)
374 CRU_GATE(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy_out_c", 0x224, 2)
375 CRU_GATE(SCLK_MAC2PHY_REF, "clk_gmac2phy_ref", "clk_mac2phy", 0x224, 3)
376 CRU_GATE(SCLK_MAC2IO_RX, "clk_gmac2io_rx", "clk_mac2io", 0x224, 4)
377 CRU_GATE(SCLK_MAC2IO_TX, "clk_gmac2io_tx", "clk_mac2io", 0x224, 5)
378 CRU_GATE(SCLK_MAC2IO_REFOUT, "clk_gmac2io_refout", "clk_mac2io", 0x224, 6)
379 CRU_GATE(SCLK_MAC2IO_REF, "clk_gmac2io_ref", "clk_mac2io", 0x224, 7)
380 /* Bit 8-15 unused */
381
382 /* CRU_CLKGATE_CON10 */
383 CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0)
384 CRU_GATE(HCLK_PERI, "hclk_peri", "hclk_peri_c", 0x228, 1)
385 CRU_GATE(PCLK_PERI, "pclk_peri", "pclk_peri_c", 0x228, 2)
386 /* Bit 3-15 unused */
387
388 /* CRU_CLKGATE_CON11 */
389 CRU_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0x22C, 0)
390 /* Bit 1-3 unused */
391 CRU_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0x22C, 4)
392 /* Bit 5-7 unused */
393 CRU_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0x22C, 8)
394 /* Bit 9-15 unused */
395
396 /* CRU_CLKGATE_CON12 */
397 /* unused */
398
399 /* CRU_CLKGATE_CON13 */
400 /* Bit 0 aclk_core_niu_en */
401 /* Bit 1 aclk_gic400_en */
402 /* Bit 2-15 unused */
403
404 /* CRU_CLKGATE_CON14 */
405 CRU_GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0x238, 0)
406 CRU_GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0x238, 1)
407 /* Bit 2-15 unused */
408
409 /* CRU_CLKGATE_CON15*/
410 /* Bit 0 aclk_intmem_en Unused */
411 /* Bit 1 aclk_dmac_bus_en Unused */
412 /* Bit 2 hclk_rom_en Unused */
413 CRU_GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0x23C, 3)
414 CRU_GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0x23C, 4)
415 CRU_GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0x23C, 5)
416 CRU_GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0x23C, 6)
417 CRU_GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0x23C, 7)
418 CRU_GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0x23C, 8)
419 CRU_GATE(0, "pclk_efuse", "pclk_bus", 0x23C, 9)
420 CRU_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0x23C, 10)
421 CRU_GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0x23C, 11)
422 CRU_GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0x23C, 12)
423 CRU_GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0x23C, 13)
424 CRU_GATE(0, "pclk_bus_niu", "pclk_bus_pre", 0x23C, 14)
425 CRU_GATE(0, "pclk_phy_niu", "pclk_phy", 0x23C, 14)
426 /* Bit 15 pclk_phy_niu_en */
427
428 /* CRU_CLKGATE_CON16 */
429 CRU_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0x240, 0)
430 CRU_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0x240, 1)
431 CRU_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0x240, 2)
432 CRU_GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0x240, 3)
433 CRU_GATE(0, "pclk_stimer", "pclk_bus", 0x240, 4)
434 CRU_GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0x240, 5)
435 CRU_GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 0x240, 6)
436 CRU_GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0x240, 7)
437 CRU_GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0x240, 8)
438 CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0x240, 9)
439 CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0x240, 10)
440 CRU_GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0x240, 11)
441 CRU_GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0x240, 12)
442 CRU_GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0x240, 13)
443 CRU_GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0x240, 14)
444 CRU_GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0x240, 15)
445
446 /* CRU_CLKGATE_CON17 */
447 CRU_GATE(PCLK_GRF, "pclk_grf", "pclk_bus", 0x244, 0)
448 /* Bit 1 unused */
449 CRU_GATE(PCLK_USB3_GRF, "pclk_usb3grf", "pclk_phy", 0x244, 2)
450 CRU_GATE(0, "pclk_ddrphy", "pclk_phy", 0x244, 3)
451 CRU_GATE(0, "pclk_cru", "pclk_bus", 0x244, 4)
452 CRU_GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy", 0x244, 5)
453 CRU_GATE(0, "pclk_sgrf", "pclk_bus", 0x244, 6)
454 CRU_GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy", 0x244, 7)
455 CRU_GATE(0, "pclk_vdacphy", "pclk_bus", 0x244, 8)
456 /* Bit 9 unused */
457 CRU_GATE(0, "pclk_sim", "pclk_bus", 0x244, 10)
458 CRU_GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0x244, 11)
459 CRU_GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0x244, 12)
460 /* Bit 13 clk_hsadc_0_tsp_en Depend on a gpio clock ? */
461 CRU_GATE(PCLK_USB2_GRF, "pclk_usb2grf", "pclk_phy", 0x244, 14)
462 CRU_GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0x244, 15)
463
464 /* CRU_CLKGATE_CON18 */
465 /* Bit 0 unused */
466 /* Bit 1 pclk_ddr_upctl_en */
467 /* Bit 2 pclk_ddr_msch_en */
468 /* Bit 3 pclk_ddr_mon_en */
469 /* Bit 4 aclk_ddr_upctl_en */
470 /* Bit 5 clk_ddr_upctl_en */
471 /* Bit 6 clk_ddr_msch_en */
472 /* Bit 7 pclk_ddrstdby_en */
473 /* Bit 8-15 unused */
474
475 /* CRU_CLKGATE_CON19 */
476 CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0)
477 CRU_GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24C, 1)
478 CRU_GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24C, 2)
479 /* Bit 3-5 unused */
480 CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0x24C, 6)
481 CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arg", "hclk_peri", 0x24C, 7)
482 CRU_GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0x24C, 8)
483 CRU_GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0x24C, 9)
484 /* Bit 10 unused */
485 CRU_GATE(0, "aclk_peri_niu", "aclk_peri", 0x24C, 11)
486 CRU_GATE(0, "hclk_peri_niu", "hclk_peri", 0x24C, 12)
487 CRU_GATE(0, "pclk_peri_niu", "hclk_peri", 0x24C, 13)
488 CRU_GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0x24C, 14)
489 CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15)
490
491 /* CRU_CLKGATE_CON20 */
492 /* unused */
493
494 /* CRU_CLKGATE_CON21 */
495 /* Bit 0-1 unused */
496 CRU_GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0x254, 2)
497 CRU_GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0x254, 3)
498 CRU_GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0x254, 4)
499 CRU_GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0x254, 5)
500 CRU_GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0x254, 6)
501 CRU_GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0x254, 7)
502 CRU_GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0x254, 8)
503 CRU_GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0x254, 9)
504 CRU_GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0x254, 10)
505 CRU_GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0x254, 11)
506 CRU_GATE(0, "hclk_ahb1tom", "hclk_vio_pre", 0x254, 12)
507 CRU_GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0x254, 13)
508 CRU_GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0x254, 14)
509 CRU_GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0x254, 15)
510
511 /* CRU_CLKGATE_CON22 */
512 CRU_GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0x258, 0)
513 CRU_GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0x258, 1)
514 CRU_GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0x258, 2)
515 CRU_GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0x258, 3)
516 CRU_GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0x258, 4)
517 CRU_GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0x258, 5)
518 /* Bit 6-15 unused */
519
520 /* CRU_CLKGATE_CON23 */
521 CRU_GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0x25C, 0)
522 CRU_GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0x25C, 1)
523 CRU_GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0x25C, 2)
524 CRU_GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0x25C, 3)
525 /* Bit 4-15 unused */
526
527 /* CRU_CLKGATE_CON24 */
528 CRU_GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0x260, 0)
529 CRU_GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0x260, 1)
530 CRU_GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0x260, 2)
531 CRU_GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0x260, 3)
532 /* Bit 4-15 unused */
533
534 /* CRU_CLKGATE_CON25 */
535 CRU_GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0x264, 0)
536 CRU_GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0x264, 1)
537 CRU_GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0x264, 2)
538 CRU_GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0x264, 3)
539 CRU_GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0x264, 4)
540 CRU_GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0x264, 5)
541 CRU_GATE(0, "aclk_axisram", "hclk_rkvenc", 0x264, 6)
542 /* Bit 7-15 unused */
543
544 /* CRU_CLKGATE_CON26 */
545 CRU_GATE(ACLK_MAC2PHY, "aclk_gmac2phy", "aclk_gmac", 0x268, 0)
546 CRU_GATE(PCLK_MAC2PHY, "pclk_gmac2phy", "pclk_gmac", 0x268, 1)
547 CRU_GATE(ACLK_MAC2IO, "aclk_gmac2io", "aclk_gmac", 0x268, 2)
548 CRU_GATE(PCLK_MAC2IO, "pclk_gmac2io", "pclk_gmac", 0x268, 3)
549 CRU_GATE(0, "aclk_gmac_niu", "aclk_gmac", 0x268, 4)
550 CRU_GATE(0, "pclk_gmac_niu", "pclk_gmac", 0x268, 5)
551 /* Bit 6-15 unused */
552
553 /* CRU_CLKGATE_CON27 */
554 /* Bit 0 clk_ddrphy_en */
555 /* Bit 1 clk4x_ddrphy_en */
556
557 /* CRU_CLKGATE_CON28 */
558 CRU_GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0x270, 0)
559 CRU_GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy", 0x270, 1)
560 CRU_GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy", 0x270, 2)
561 CRU_GATE(0, "pclk_pmu", "pclk_bus", 0x270, 3)
562 CRU_GATE(0, "pclk_otp", "pclk_bus", 0x270, 4)
563 /* Bit 5-15 unused */
564 };
565
566 /*
567 * PLLs
568 */
569
570 #define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd, _frac) \
571 { \
572 .freq = _hz, \
573 .refdiv = _ref, \
574 .fbdiv = _fb, \
575 .postdiv1 = _post1, \
576 .postdiv2 = _post2, \
577 .dsmpd = _dspd, \
578 .frac = _frac, \
579 }
580
581 static struct rk_clk_pll_rate rk3328_pll_rates[] = {
582 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
583 PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
584 PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
585 PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
586 PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
587 PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
588 PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
589 PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
590 PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
591 PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
592 PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
593 PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
594 PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
595 PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
596 PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
597 PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
598 PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
599 PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
600 PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
601 PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
602 PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
603 PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
604 PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
605 PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
606 PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
607 PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
608 PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
609 PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
610 PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
611 PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
612 PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
613 PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
614 PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
615 PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
616 PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
617 PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
618 PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
619 PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
620 PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
621 PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
622 PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
623 PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
624 PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
625 {},
626 };
627
628 static struct rk_clk_pll_rate rk3328_pll_frac_rates[] = {
629 PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217),
630 PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088),
631 PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088),
632 PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088),
633 PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894),
634 PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329),
635 {},
636 };
637
638 /* Clock parents */
639 #define PLIST(_name) static const char *_name[]
640
641 PLIST(pll_src_p) = {"xin24m"};
642 PLIST(xin24m_rtc32k_p) = {"xin24m", "clk_rtc32k"};
643
644 PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};
645 PLIST(pll_src_cpll_gpll_apll_p) = {"cpll", "gpll", "apll"};
646 PLIST(pll_src_cpll_gpll_xin24m_p) = {"cpll", "gpll", "xin24m", "xin24m" /* Dummy */};
647 PLIST(pll_src_cpll_gpll_usb480m_p) = {"cpll", "gpll", "usb480m"};
648 PLIST(pll_src_cpll_gpll_hdmiphy_p) = {"cpll", "gpll", "hdmi_phy"};
649 PLIST(pll_src_cpll_gpll_hdmiphy_usb480m_p) = {"cpll", "gpll", "hdmi_phy", "usb480m"};
650 PLIST(pll_src_apll_gpll_dpll_npll_p) = {"apll", "gpll", "dpll", "npll"};
651 PLIST(pll_src_cpll_gpll_xin24m_usb480m_p) = {"cpll", "gpll", "xin24m", "usb480m"};
652 PLIST(mux_ref_usb3otg_p) = { "xin24m", "clk_usb3_otg0_ref" };
653 PLIST(mux_mac2io_p) = { "clk_mac2io_src", "gmac_clkin" };
654 PLIST(mux_mac2io_ext_p) = { "clk_mac2io", "gmac_clkin" };
655 PLIST(mux_mac2phy_p) = { "clk_mac2phy_src", "phy_50m_out" };
656 PLIST(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", "xin12m", "xin12m" };
657 PLIST(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s1", "xin12m" };
658 PLIST(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s2", "xin12m" };
659 PLIST(mux_dclk_lcdc_p) = {"hdmiphy", "vop_dclk_src"};
660 PLIST(mux_hdmiphy_p) = {"hdmi_phy", "xin24m"};
661 PLIST(mux_usb480m_p) = {"usb480m_phy", "xin24m"};
662 PLIST(mux_uart0_p) = {"clk_uart0_div", "clk_uart0_frac", "xin24m", "xin24m"};
663 PLIST(mux_uart1_p) = {"clk_uart1_div", "clk_uart1_frac", "xin24m", "xin24m"};
664 PLIST(mux_uart2_p) = {"clk_uart2_div", "clk_uart2_frac", "xin24m", "xin24m"};
665 PLIST(mux_spdif_p) = {"clk_spdif_div", "clk_spdif_frac", "xin12m", "xin12m"};
666 PLIST(mux_cif_p) = {"clk_cif_pll", "xin24m"};
667
668 static struct rk_clk_pll_def apll = {
669 .clkdef = {
670 .id = PLL_APLL,
671 .name = "apll",
672 .parent_names = pll_src_p,
673 .parent_cnt = nitems(pll_src_p),
674 },
675 .base_offset = 0x00,
676 .gate_offset = 0x200,
677 .gate_shift = 0,
678 .mode_reg = 0x80,
679 .mode_shift = 1,
680 .flags = RK_CLK_PLL_HAVE_GATE,
681 .frac_rates = rk3328_pll_frac_rates,
682 };
683
684 static struct rk_clk_pll_def dpll = {
685 .clkdef = {
686 .id = PLL_DPLL,
687 .name = "dpll",
688 .parent_names = pll_src_p,
689 .parent_cnt = nitems(pll_src_p),
690 },
691 .base_offset = 0x20,
692 .gate_offset = 0x200,
693 .gate_shift = 1,
694 .mode_reg = 0x80,
695 .mode_shift = 4,
696 .flags = RK_CLK_PLL_HAVE_GATE,
697 };
698
699 static struct rk_clk_pll_def cpll = {
700 .clkdef = {
701 .id = PLL_CPLL,
702 .name = "cpll",
703 .parent_names = pll_src_p,
704 .parent_cnt = nitems(pll_src_p),
705 },
706 .base_offset = 0x40,
707 .mode_reg = 0x80,
708 .mode_shift = 8,
709 .rates = rk3328_pll_rates,
710 };
711
712 static struct rk_clk_pll_def gpll = {
713 .clkdef = {
714 .id = PLL_GPLL,
715 .name = "gpll",
716 .parent_names = pll_src_p,
717 .parent_cnt = nitems(pll_src_p),
718 },
719 .base_offset = 0x60,
720 .gate_offset = 0x200,
721 .gate_shift = 2,
722 .mode_reg = 0x80,
723 .mode_shift = 12,
724 .flags = RK_CLK_PLL_HAVE_GATE,
725 .frac_rates = rk3328_pll_frac_rates,
726 };
727
728 static struct rk_clk_pll_def npll = {
729 .clkdef = {
730 .id = PLL_NPLL,
731 .name = "npll",
732 .parent_names = pll_src_p,
733 .parent_cnt = nitems(pll_src_p),
734 },
735 .base_offset = 0xa0,
736 .gate_offset = 0x200,
737 .gate_shift = 12,
738 .mode_reg = 0x80,
739 .mode_shift = 1,
740 .flags = RK_CLK_PLL_HAVE_GATE,
741 .rates = rk3328_pll_rates,
742 };
743
744 static struct rk_clk_armclk_rates rk3328_armclk_rates[] = {
745 {
746 .freq = 1296000000,
747 .div = 1,
748 },
749 {
750 .freq = 1200000000,
751 .div = 1,
752 },
753 {
754 .freq = 1104000000,
755 .div = 1,
756 },
757 {
758 .freq = 1008000000,
759 .div = 1,
760 },
761 {
762 .freq = 912000000,
763 .div = 1,
764 },
765 {
766 .freq = 816000000,
767 .div = 1,
768 },
769 {
770 .freq = 696000000,
771 .div = 1,
772 },
773 {
774 .freq = 600000000,
775 .div = 1,
776 },
777 {
778 .freq = 408000000,
779 .div = 1,
780 },
781 {
782 .freq = 312000000,
783 .div = 1,
784 },
785 {
786 .freq = 216000000,
787 .div = 1,
788 },
789 {
790 .freq = 96000000,
791 .div = 1,
792 },
793 };
794
795 static struct rk_clk_armclk_def armclk = {
796 .clkdef = {
797 .id = ARMCLK,
798 .name = "armclk",
799 .parent_names = pll_src_apll_gpll_dpll_npll_p,
800 .parent_cnt = nitems(pll_src_apll_gpll_dpll_npll_p),
801 },
802 .muxdiv_offset = 0x100,
803 .mux_shift = 6,
804 .mux_width = 2,
805
806 .div_shift = 0,
807 .div_width = 5,
808
809 .flags = RK_CLK_COMPOSITE_HAVE_MUX,
810 .main_parent = 3, /* npll */
811 .alt_parent = 0, /* apll */
812
813 .rates = rk3328_armclk_rates,
814 .nrates = nitems(rk3328_armclk_rates),
815 };
816
817 static struct rk_clk rk3328_clks[] = {
818 /* External clocks */
819 LINK("xin24m"),
820 LINK("gmac_clkin"),
821 LINK("hdmi_phy"),
822 LINK("usb480m_phy"),
823 FRATE(0, "xin12m", 12000000),
824 FRATE(0, "phy_50m_out", 50000000),
825 FRATE(0, "clkin_i2s1", 0),
826 FRATE(0, "clkin_i2s2", 0),
827
828 /* PLLs */
829 {
830 .type = RK3328_CLK_PLL,
831 .clk.pll = &apll
832 },
833 {
834 .type = RK3328_CLK_PLL,
835 .clk.pll = &dpll
836 },
837 {
838 .type = RK3328_CLK_PLL,
839 .clk.pll = &cpll
840 },
841 {
842 .type = RK3328_CLK_PLL,
843 .clk.pll = &gpll
844 },
845 {
846 .type = RK3328_CLK_PLL,
847 .clk.pll = &npll
848 },
849
850 {
851 .type = RK_CLK_ARMCLK,
852 .clk.armclk = &armclk,
853 },
854
855 /* CRU_CRU_MISC */
856 MUXRAW(HDMIPHY, "hdmiphy", mux_hdmiphy_p, 0, 0x84, 13, 1),
857 MUXRAW(USB480M, "usb480m", mux_usb480m_p, 0, 0x84, 15, 1),
858
859 /* CRU_CLKSEL_CON0 */
860 /* COMP clk_core_div_con core_clk_pll_sel */
861 COMP(0, "aclk_bus_pre_c", pll_src_cpll_gpll_hdmiphy_p, 0, 0, 8, 5, 13, 2),
862
863 /* CRU_CLKSEL_CON1 */
864 /* CDIV clk_core_dbg_div_con */
865 /* CDIV aclk_core_div_con */
866 CDIV(0, "hclk_bus_pre_c", "aclk_bus_pre", 0, 1, 8, 2),
867 CDIV(0, "pclk_bus_pre_c", "aclk_bus_pre", 0, 1, 12, 2),
868
869 /* CRU_CLKSEL_CON2 */
870 /* CDIV test_div_con */
871 /* CDIV func_24m_div_con */
872
873 /* CRU_CLKSEL_CON3 */
874 /* COMP ddr_div_cnt ddr_clk_pll_sel */
875
876 /* CRU_CLKSEL_CON4 */
877 COMP(0, "clk_otp_c", pll_src_cpll_gpll_xin24m_p, 0, 4, 0, 6, 6, 2),
878 /* COMP pd_ddr_div_con ddrpdclk_clk_pll_sel */
879
880 /* CRU_CLKSEL_CON5 */
881 COMP(0, "clk_efuse_c", pll_src_cpll_gpll_xin24m_p, 0, 5, 8, 5, 14, 2),
882
883 /* CRU_CLKSEL_CON6 */
884 MUX(0, "clk_i2s0_mux", mux_i2s0_p, RK_CLK_MUX_REPARENT, 6, 8, 2),
885 COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0, 6, 0, 7, 15, 1),
886
887 /* CRU_CLKSEL_CON7 */
888 FRACT(0, "clk_i2s0_frac_f", "clk_i2s0_div", 0, 7),
889
890 /* CRU_CLKSEL_CON8 */
891 MUX(0, "clk_i2s1_mux", mux_i2s1_p, RK_CLK_MUX_REPARENT, 8, 8, 2),
892 COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0, 8, 0, 7, 15, 1),
893 /* MUX i2s1_out_sel */
894
895 /* CRU_CLKSEL_CON9 */
896 FRACT(0, "clk_i2s1_frac_f", "clk_i2s1_div", 0, 9),
897
898 /* CRU_CLKSEL_CON10 */
899 MUX(0, "clk_i2s2_mux", mux_i2s2_p, RK_CLK_MUX_REPARENT, 10, 8, 2),
900 COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0, 10, 0, 7, 15, 1),
901 /* MUX i2s2_out_sel */
902
903 /* CRU_CLKSEL_CON11 */
904 FRACT(0, "clk_i2s2_frac_f", "clk_i2s2_div", 0, 11),
905
906 /* CRU_CLKSEL_CON12 */
907 MUX(0, "clk_spdif_pll", pll_src_cpll_gpll_p, 0, 12, 15, 1),
908 MUX(SCLK_SPDIF, "clk_spdif", mux_spdif_p, 0, 12, 8, 2),
909 CDIV(0, "clk_spdif_div_c", "clk_spdif_pll", 0, 12, 0, 7),
910
911 /* CRU_CLKSEL_CON13 */
912 FRACT(0, "clk_spdif_frac_f", "clk_spdif", 0, 13),
913
914 /* CRU_CLKSEL_CON14 */
915 MUX(0, "clk_uart0_pll", pll_src_cpll_gpll_usb480m_p, 0, 14, 12, 2),
916 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, 0, 14, 8, 2),
917 CDIV(0, "clk_uart0_div_c", "clk_uart0_pll", 0, 14, 0, 7),
918
919 /* CRU_CLKSEL_CON15 */
920 FRACT(0, "clk_uart0_frac_f", "clk_uart0_pll", 0, 15),
921
922 /* CRU_CLKSEL_CON16 */
923 MUX(0, "clk_uart1_pll", pll_src_cpll_gpll_usb480m_p, 0, 16, 12, 2),
924 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, 0, 16, 8, 2),
925 CDIV(0, "clk_uart1_div_c", "clk_uart1_pll", 0, 16, 0, 7),
926
927 /* CRU_CLKSEL_CON17 */
928 FRACT(0, "clk_uart1_frac_f", "clk_uart1_pll", 0, 17),
929
930 /* CRU_CLKSEL_CON18 */
931 MUX(0, "clk_uart2_pll", pll_src_cpll_gpll_usb480m_p, 0, 18, 12, 2),
932 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, 0, 18, 8, 2),
933 CDIV(0, "clk_uart2_div_c", "clk_uart2_pll", 0, 18, 0, 7),
934
935 /* CRU_CLKSEL_CON19 */
936 FRACT(0, "clk_uart2_frac_f", "clk_uart2_pll", 0, 19),
937
938 /* CRU_CLKSEL_CON20 */
939 COMP(0, "clk_pdm_c", pll_src_cpll_gpll_apll_p, 0, 20, 8, 5, 14, 2),
940 COMP(0, "clk_crypto_c", pll_src_cpll_gpll_p, 0, 20, 0, 5, 7, 1),
941
942 /* CRU_CLKSEL_CON21 */
943 COMP(0, "clk_tsp_c", pll_src_cpll_gpll_p, 0, 21, 8, 5, 15, 1),
944
945 /* CRU_CLKSEL_CON22 */
946 CDIV(0, "clk_tsadc_c", "xin24m", 0, 22, 0, 10),
947
948 /* CRU_CLKSEL_CON23 */
949 CDIV(0, "clk_saradc_c", "xin24m", 0, 23, 0, 10),
950
951 /* CRU_CLKSEL_CON24 */
952 COMP(0, "clk_pwm_c", pll_src_cpll_gpll_p, 0, 24, 8, 7, 15, 1),
953 COMP(0, "clk_spi_c", pll_src_cpll_gpll_p, 0, 24, 0, 7, 7, 1),
954
955 /* CRU_CLKSEL_CON25 */
956 COMP(0, "aclk_gmac_c", pll_src_cpll_gpll_p, 0, 35, 0, 5, 6, 2),
957 CDIV(0, "pclk_gmac_c", "pclk_gmac", 0, 25, 8, 3),
958
959 /* CRU_CLKSEL_CON26 */
960 CDIV(0, "clk_mac2phy_out_c", "clk_mac2phy", 0, 26, 8, 2),
961 COMP(0, "clk_mac2phy_src_c", pll_src_cpll_gpll_p, 0, 26, 0, 5, 7, 1),
962
963 /* CRU_CLKSEL_CON27 */
964 COMP(0, "clk_mac2io_src_c", pll_src_cpll_gpll_p, 0, 27, 0, 5, 7, 1),
965 COMP(0, "clk_mac2io_out_c", pll_src_cpll_gpll_p, 0, 27, 8, 5, 15, 1),
966
967 /* CRU_CLKSEL_CON28 */
968 COMP(ACLK_PERI_PRE, "aclk_peri_pre", pll_src_cpll_gpll_hdmiphy_p, 0, 28, 0, 5, 6, 2),
969
970 /* CRU_CLKSEL_CON29 */
971 CDIV(0, "pclk_peri_c", "aclk_peri_pre", 0, 29, 0, 2),
972 CDIV(0, "hclk_peri_c", "aclk_peri_pre", 0, 29, 4, 3),
973
974 /* CRU_CLKSEL_CON30 */
975 COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 30, 0, 8, 8, 2),
976
977 /* CRU_CLKSEL_CON31 */
978 COMP(0, "clk_sdio_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 31, 0, 8, 8, 2),
979
980 /* CRU_CLKSEL_CON32 */
981 COMP(0, "clk_emmc_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 32, 0, 8, 8, 2),
982
983 /* CRU_CLKSEL_CON33 */
984 COMP(0, "clk_usb3otg_suspend_c", xin24m_rtc32k_p, 0, 33, 0, 10, 15, 1),
985
986 /* CRU_CLKSEL_CON34 */
987 COMP(0, "clk_i2c0_c", pll_src_cpll_gpll_p, 0, 34, 0, 7, 7, 1),
988 COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0, 34, 8, 7, 15, 1),
989
990 /* CRU_CLKSEL_CON35 */
991 COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0, 35, 0, 7, 7, 1),
992 COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0, 35, 8, 7, 15, 1),
993
994 /* CRU_CLKSEL_CON36 */
995 COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 8, 5, 14, 2),
996 COMP(0, "sclk_rga_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 0, 5, 6, 2),
997
998 /* CRU_CLKSEL_CON37 */
999 COMP(0, "aclk_vio_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 37, 0, 5, 6, 2),
1000 CDIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0, 37, 8, 5),
1001
1002 /* CRU_CLKSEL_CON38 */
1003 COMP(0, "clk_rtc32k_c", pll_src_cpll_gpll_xin24m_p, 0, 38, 0, 14, 14, 2),
1004
1005 /* CRU_CLKSEL_CON39 */
1006 COMP(0, "aclk_vop_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 39, 0, 5, 6, 2),
1007
1008 /* CRU_CLKSEL_CON40 */
1009 COMP(0, "vop_dclk_src_c", pll_src_cpll_gpll_p, 0, 40, 8, 8, 0, 1),
1010 CDIV(DCLK_HDMIPHY, "hdmiphy_div", "vop_dclk_src", 0, 40, 3, 3),
1011 /* MUX vop_dclk_frac_sel */
1012 MUX(DCLK_LCDC, "vop_dclk", mux_dclk_lcdc_p, 0, 40, 1, 1),
1013
1014 /* CRU_CLKSEL_CON41 */
1015 /* FRACT dclk_vop_frac_div_con */
1016
1017 /* CRU_CLKSEL_CON42 */
1018 MUX(0, "clk_cif_pll", pll_src_cpll_gpll_p, 0, 42, 7, 1),
1019 COMP(0, "clk_cif_src_c", mux_cif_p, 0, 42, 0, 5, 5, 1),
1020
1021 /* CRU_CLKSEL_CON43 */
1022 COMP(0, "clk_sdmmc_ext_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 43, 0, 8, 8, 2),
1023
1024 /* CRU_CLKSEL_CON44 */
1025 COMP(0, "aclk_gpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 44, 0, 5, 6, 2),
1026
1027 /* CRU_CLKSEL_CON45 */
1028 MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_p, 0, 45, 8, 1),
1029 COMP(0, "clk_ref_usb3otg_src_c", pll_src_cpll_gpll_p, 0, 45, 0, 7, 7, 1),
1030
1031 /* CRU_CLKSEL_CON46 */
1032 /* Unused */
1033
1034 /* CRU_CLKSEL_CON47 */
1035 /* Unused */
1036
1037 /* CRU_CLKSEL_CON48 */
1038 COMP(0, "sclk_cabac_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 8, 5, 14, 2),
1039 COMP(0, "aclk_rkvdec_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 0, 5, 6, 2),
1040
1041 /* CRU_CLKSEL_CON49 */
1042 COMP(0, "sclk_vdec_core_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 49, 0, 5, 6, 2),
1043
1044 /* CRU_CLKSEL_CON50 */
1045 COMP(0, "aclk_vpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 50, 0, 5, 6, 2),
1046
1047 /* CRU_CLKSEL_CON51 */
1048 COMP(0, "sclk_venc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2),
1049 COMP(0, "aclk_rkvenc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 0, 5, 6, 2),
1050
1051 /* CRU_CLKSEL_CON52 */
1052 COMP(0, "sclk_venc_dsp_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2),
1053 COMP(0, "sclk_wifi_c", pll_src_cpll_gpll_usb480m_p, 0, 51, 0, 6, 6, 2),
1054
1055 /* GRF_SOC_CON4 */
1056 MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, 0, RK3328_GRF_SOC_CON4, 14, 1),
1057
1058 /* GRF_MAC_CON1 */
1059 MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_p, 0, RK3328_GRF_MAC_CON1, 10, 1),
1060
1061 /* GRF_MAC_CON2 */
1062 MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_p, 0, RK3328_GRF_MAC_CON2, 10, 1),
1063
1064 /*
1065 * This clock is controlled in the secure world
1066 */
1067 FFACT(PCLK_WDT, "pclk_wdt", "pclk_bus", 1, 1),
1068 };
1069
1070 static int
rk3328_cru_probe(device_t dev)1071 rk3328_cru_probe(device_t dev)
1072 {
1073
1074 if (!ofw_bus_status_okay(dev))
1075 return (ENXIO);
1076
1077 if (ofw_bus_is_compatible(dev, "rockchip,rk3328-cru")) {
1078 device_set_desc(dev, "Rockchip RK3328 Clock and Reset Unit");
1079 return (BUS_PROBE_DEFAULT);
1080 }
1081
1082 return (ENXIO);
1083 }
1084
1085 static int
rk3328_cru_attach(device_t dev)1086 rk3328_cru_attach(device_t dev)
1087 {
1088 struct rk_cru_softc *sc;
1089
1090 sc = device_get_softc(dev);
1091 sc->dev = dev;
1092
1093 sc->gates = rk3328_gates;
1094 sc->ngates = nitems(rk3328_gates);
1095
1096 sc->clks = rk3328_clks;
1097 sc->nclks = nitems(rk3328_clks);
1098
1099 sc->reset_offset = 0x300;
1100 sc->reset_num = 184;
1101
1102 return (rk_cru_attach(dev));
1103 }
1104
1105 static device_method_t rk3328_cru_methods[] = {
1106 /* Device interface */
1107 DEVMETHOD(device_probe, rk3328_cru_probe),
1108 DEVMETHOD(device_attach, rk3328_cru_attach),
1109
1110 DEVMETHOD_END
1111 };
1112
1113 static devclass_t rk3328_cru_devclass;
1114
1115 DEFINE_CLASS_1(rk3328_cru, rk3328_cru_driver, rk3328_cru_methods,
1116 sizeof(struct rk_cru_softc), rk_cru_driver);
1117
1118 EARLY_DRIVER_MODULE(rk3328_cru, simplebus, rk3328_cru_driver,
1119 rk3328_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1120