1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
6 * Copyright (c) 2012 Semihalf.
7 * All rights reserved.
8 *
9 * Developed by Semihalf.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
32 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30
33 */
34
35 #include <sys/cdefs.h>
36 #include "opt_platform.h"
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/bus.h>
41 #include <sys/kernel.h>
42 #include <sys/cpuset.h>
43 #include <sys/ktr.h>
44 #include <sys/kdb.h>
45 #include <sys/module.h>
46 #include <sys/lock.h>
47 #include <sys/mutex.h>
48 #include <sys/rman.h>
49 #include <sys/proc.h>
50 #include <sys/smp.h>
51
52 #include <machine/bus.h>
53 #include <machine/intr.h>
54 #include <machine/smp.h>
55
56 #include <arm/mv/mvvar.h>
57 #include <arm/mv/mvreg.h>
58
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61 #include <dev/fdt/fdt_common.h>
62
63 #include "pic_if.h"
64
65 #ifdef DEBUG
66 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
67 printf(fmt,##args); } while (0)
68 #else
69 #define debugf(fmt, args...)
70 #endif
71
72 #define MPIC_INT_LOCAL 3
73 #define MPIC_INT_ERR 4
74 #define MPIC_INT_MSI 96
75
76 #define MPIC_IRQ_MASK 0x3ff
77
78 #define MPIC_CTRL 0x0
79 #define MPIC_SOFT_INT 0x4
80 #define MPIC_SOFT_INT_DRBL1 (1 << 5)
81 #define MPIC_ERR_CAUSE 0x20
82 #define MPIC_ISE 0x30
83 #define MPIC_ICE 0x34
84 #define MPIC_INT_CTL(irq) (0x100 + (irq)*4)
85
86 #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid))
87 #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff)
88
89 #define MPIC_IN_DRBL 0x08
90 #define MPIC_IN_DRBL_MASK 0x0c
91 #define MPIC_PPI_CAUSE 0x10
92 #define MPIC_CTP 0x40
93 #define MPIC_IIACK 0x44
94 #define MPIC_ISM 0x48
95 #define MPIC_ICM 0x4c
96 #define MPIC_ERR_MASK 0x50
97 #define MPIC_LOCAL_MASK 0x54
98 #define MPIC_CPU(n) (n) * 0x100
99
100 #define MPIC_PPI 32
101
102 struct mv_mpic_irqsrc {
103 struct intr_irqsrc mmi_isrc;
104 u_int mmi_irq;
105 };
106
107 struct mv_mpic_softc {
108 device_t sc_dev;
109 struct resource * mpic_res[4];
110 bus_space_tag_t mpic_bst;
111 bus_space_handle_t mpic_bsh;
112 bus_space_tag_t cpu_bst;
113 bus_space_handle_t cpu_bsh;
114 bus_space_tag_t drbl_bst;
115 bus_space_handle_t drbl_bsh;
116 struct mtx mtx;
117 struct mv_mpic_irqsrc * mpic_isrcs;
118 int nirqs;
119 void * intr_hand;
120 };
121
122 static struct resource_spec mv_mpic_spec[] = {
123 { SYS_RES_MEMORY, 0, RF_ACTIVE },
124 { SYS_RES_MEMORY, 1, RF_ACTIVE },
125 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
126 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL },
127 { -1, 0 }
128 };
129
130 static struct ofw_compat_data compat_data[] = {
131 {"mrvl,mpic", true},
132 {"marvell,mpic", true},
133 {NULL, false}
134 };
135
136 static struct mv_mpic_softc *mv_mpic_sc = NULL;
137
138 void mpic_send_ipi(int cpus, u_int ipi);
139
140 static int mv_mpic_probe(device_t);
141 static int mv_mpic_attach(device_t);
142 uint32_t mv_mpic_get_cause(void);
143 uint32_t mv_mpic_get_cause_err(void);
144 uint32_t mv_mpic_get_msi(void);
145 static void mpic_unmask_irq(uintptr_t nb);
146 static void mpic_mask_irq(uintptr_t nb);
147 static void mpic_mask_irq_err(uintptr_t nb);
148 static void mpic_unmask_irq_err(uintptr_t nb);
149 static boolean_t mpic_irq_is_percpu(uintptr_t);
150 static int mpic_intr(void *arg);
151 static void mpic_unmask_msi(void);
152 void mpic_init_secondary(device_t);
153 void mpic_ipi_send(device_t, struct intr_irqsrc*, cpuset_t, u_int);
154 int mpic_ipi_read(int);
155 void mpic_ipi_clear(int);
156
157 #define MPIC_WRITE(softc, reg, val) \
158 bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val))
159 #define MPIC_READ(softc, reg) \
160 bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg))
161
162 #define MPIC_CPU_WRITE(softc, reg, val) \
163 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))
164 #define MPIC_CPU_READ(softc, reg) \
165 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg))
166
167 #define MPIC_DRBL_WRITE(softc, reg, val) \
168 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val))
169 #define MPIC_DRBL_READ(softc, reg) \
170 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg))
171
172 static int
mv_mpic_probe(device_t dev)173 mv_mpic_probe(device_t dev)
174 {
175
176 if (!ofw_bus_status_okay(dev))
177 return (ENXIO);
178
179 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
180 return (ENXIO);
181
182 device_set_desc(dev, "Marvell Integrated Interrupt Controller");
183 return (0);
184 }
185
186 static int
mv_mpic_register_isrcs(struct mv_mpic_softc * sc)187 mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
188 {
189 int error;
190 uint32_t irq;
191 struct intr_irqsrc *isrc;
192 const char *name;
193
194 sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF,
195 M_WAITOK | M_ZERO);
196
197 name = device_get_nameunit(sc->sc_dev);
198 for (irq = 0; irq < sc->nirqs; irq++) {
199 sc->mpic_isrcs[irq].mmi_irq = irq;
200
201 isrc = &sc->mpic_isrcs[irq].mmi_isrc;
202 if (irq < MPIC_PPI) {
203 error = intr_isrc_register(isrc, sc->sc_dev,
204 INTR_ISRCF_PPI, "%s", name);
205 } else {
206 error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s",
207 name);
208 }
209 if (error != 0) {
210 /* XXX call intr_isrc_deregister() */
211 device_printf(sc->sc_dev, "%s failed", __func__);
212 return (error);
213 }
214 }
215 return (0);
216 }
217
218 static int
mv_mpic_attach(device_t dev)219 mv_mpic_attach(device_t dev)
220 {
221 struct mv_mpic_softc *sc;
222 int error;
223 uint32_t val;
224 int cpu;
225
226 sc = (struct mv_mpic_softc *)device_get_softc(dev);
227
228 if (mv_mpic_sc != NULL)
229 return (ENXIO);
230 mv_mpic_sc = sc;
231
232 sc->sc_dev = dev;
233
234 mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN);
235
236 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
237 if (error) {
238 device_printf(dev, "could not allocate resources\n");
239 return (ENXIO);
240 }
241 if (sc->mpic_res[3] == NULL)
242 device_printf(dev, "No interrupt to use.\n");
243 else
244 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,
245 mpic_intr, NULL, sc, &sc->intr_hand);
246
247 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
248 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
249
250 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
251 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);
252
253 if (sc->mpic_res[2] != NULL) {
254 /* This is required only if MSIs are used. */
255 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
256 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
257 }
258
259 MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1);
260 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
261
262 val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
263 sc->nirqs = MPIC_CTRL_NIRQS(val);
264
265 if (mv_mpic_register_isrcs(sc) != 0) {
266 device_printf(dev, "could not register PIC ISRCs\n");
267 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
268 return (ENXIO);
269 }
270
271 OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);
272
273 if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) {
274 device_printf(dev, "could not register PIC\n");
275 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
276 return (ENXIO);
277 }
278
279 mpic_unmask_msi();
280
281 /* Unmask CPU performance counters overflow irq */
282 for (cpu = 0; cpu < mp_ncpus; cpu++)
283 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK,
284 (1 << cpu) | MPIC_CPU_READ(mv_mpic_sc,
285 MPIC_CPU(cpu) + MPIC_LOCAL_MASK));
286
287 return (0);
288 }
289
290 static int
mpic_intr(void * arg)291 mpic_intr(void *arg)
292 {
293 struct mv_mpic_softc *sc;
294 uint32_t cause, irqsrc;
295 unsigned int irq;
296 u_int cpuid;
297
298 sc = arg;
299 cpuid = PCPU_GET(cpuid);
300 irq = 0;
301
302 for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0;
303 cause >>= 1, irq++) {
304 if (cause & 1) {
305 irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq));
306 if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0)
307 continue;
308 if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc,
309 curthread->td_intr_frame) != 0) {
310 mpic_mask_irq(irq);
311 device_printf(sc->sc_dev, "Stray irq %u "
312 "disabled\n", irq);
313 }
314 }
315 }
316
317 return (FILTER_HANDLED);
318 }
319
320 static void
mpic_disable_intr(device_t dev,struct intr_irqsrc * isrc)321 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
322 {
323 u_int irq;
324
325 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq;
326 mpic_mask_irq(irq);
327 }
328
329 static void
mpic_enable_intr(device_t dev,struct intr_irqsrc * isrc)330 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
331 {
332 u_int irq;
333
334 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq;
335 mpic_unmask_irq(irq);
336 }
337
338 static int
mpic_map_intr(device_t dev,struct intr_map_data * data,struct intr_irqsrc ** isrcp)339 mpic_map_intr(device_t dev, struct intr_map_data *data,
340 struct intr_irqsrc **isrcp)
341 {
342 struct intr_map_data_fdt *daf;
343 struct mv_mpic_softc *sc;
344
345 if (data->type != INTR_MAP_DATA_FDT)
346 return (ENOTSUP);
347
348 sc = device_get_softc(dev);
349 daf = (struct intr_map_data_fdt *)data;
350
351 if (daf->ncells !=1 || daf->cells[0] >= sc->nirqs)
352 return (EINVAL);
353
354 *isrcp = &sc->mpic_isrcs[daf->cells[0]].mmi_isrc;
355 return (0);
356 }
357
358 static void
mpic_pre_ithread(device_t dev,struct intr_irqsrc * isrc)359 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
360 {
361
362 mpic_disable_intr(dev, isrc);
363 }
364
365 static void
mpic_post_ithread(device_t dev,struct intr_irqsrc * isrc)366 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
367 {
368
369 mpic_enable_intr(dev, isrc);
370 }
371
372 static void
mpic_post_filter(device_t dev,struct intr_irqsrc * isrc)373 mpic_post_filter(device_t dev, struct intr_irqsrc *isrc)
374 {
375 }
376
377 static device_method_t mv_mpic_methods[] = {
378 DEVMETHOD(device_probe, mv_mpic_probe),
379 DEVMETHOD(device_attach, mv_mpic_attach),
380
381 DEVMETHOD(pic_disable_intr, mpic_disable_intr),
382 DEVMETHOD(pic_enable_intr, mpic_enable_intr),
383 DEVMETHOD(pic_map_intr, mpic_map_intr),
384 DEVMETHOD(pic_post_filter, mpic_post_filter),
385 DEVMETHOD(pic_post_ithread, mpic_post_ithread),
386 DEVMETHOD(pic_pre_ithread, mpic_pre_ithread),
387 DEVMETHOD(pic_init_secondary, mpic_init_secondary),
388 DEVMETHOD(pic_ipi_send, mpic_ipi_send),
389 { 0, 0 }
390 };
391
392 static driver_t mv_mpic_driver = {
393 "mpic",
394 mv_mpic_methods,
395 sizeof(struct mv_mpic_softc),
396 };
397
398 static devclass_t mv_mpic_devclass;
399
400 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0,
401 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
402
403 static void
mpic_unmask_msi(void)404 mpic_unmask_msi(void)
405 {
406
407 mpic_unmask_irq(MPIC_INT_MSI);
408 }
409
410 static void
mpic_unmask_irq_err(uintptr_t nb)411 mpic_unmask_irq_err(uintptr_t nb)
412 {
413 uint32_t mask;
414 uint8_t bit_off;
415
416 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, MPIC_INT_ERR);
417 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR);
418
419 bit_off = nb - ERR_IRQ;
420 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
421 mask |= (1 << bit_off);
422 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
423 }
424
425 static void
mpic_mask_irq_err(uintptr_t nb)426 mpic_mask_irq_err(uintptr_t nb)
427 {
428 uint32_t mask;
429 uint8_t bit_off;
430
431 bit_off = nb - ERR_IRQ;
432 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
433 mask &= ~(1 << bit_off);
434 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
435 }
436
437 static boolean_t
mpic_irq_is_percpu(uintptr_t nb)438 mpic_irq_is_percpu(uintptr_t nb)
439 {
440 if (nb < MPIC_PPI)
441 return TRUE;
442
443 return FALSE;
444 }
445
446 static void
mpic_unmask_irq(uintptr_t nb)447 mpic_unmask_irq(uintptr_t nb)
448 {
449
450 #ifdef SMP
451 int cpu;
452
453 if (nb == MPIC_INT_LOCAL) {
454 for (cpu = 0; cpu < mp_ncpus; cpu++)
455 MPIC_CPU_WRITE(mv_mpic_sc,
456 MPIC_CPU(cpu) + MPIC_ICM, nb);
457 return;
458 }
459 #endif
460 if (mpic_irq_is_percpu(nb))
461 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb);
462 else if (nb < ERR_IRQ)
463 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb);
464 else if (nb < MSI_IRQ)
465 mpic_unmask_irq_err(nb);
466
467 if (nb == 0)
468 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff);
469 }
470
471 static void
mpic_mask_irq(uintptr_t nb)472 mpic_mask_irq(uintptr_t nb)
473 {
474
475 #ifdef SMP
476 int cpu;
477
478 if (nb == MPIC_INT_LOCAL) {
479 for (cpu = 0; cpu < mp_ncpus; cpu++)
480 MPIC_CPU_WRITE(mv_mpic_sc,
481 MPIC_CPU(cpu) + MPIC_ISM, nb);
482 return;
483 }
484 #endif
485 if (mpic_irq_is_percpu(nb))
486 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb);
487 else if (nb < ERR_IRQ)
488 MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb);
489 else if (nb < MSI_IRQ)
490 mpic_mask_irq_err(nb);
491 }
492
493 uint32_t
mv_mpic_get_cause(void)494 mv_mpic_get_cause(void)
495 {
496
497 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK));
498 }
499
500 uint32_t
mv_mpic_get_cause_err(void)501 mv_mpic_get_cause_err(void)
502 {
503 uint32_t err_cause;
504 uint8_t bit_off;
505
506 err_cause = MPIC_READ(mv_mpic_sc, MPIC_ERR_CAUSE);
507
508 if (err_cause)
509 bit_off = ffs(err_cause) - 1;
510 else
511 return (-1);
512
513 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause);
514 return (ERR_IRQ + bit_off);
515 }
516
517 uint32_t
mv_mpic_get_msi(void)518 mv_mpic_get_msi(void)
519 {
520 uint32_t cause;
521 uint8_t bit_off;
522
523 KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi"));
524 cause = MPIC_DRBL_READ(mv_mpic_sc, 0);
525
526 if (cause)
527 bit_off = ffs(cause) - 1;
528 else
529 return (-1);
530
531 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause);
532
533 cause &= ~(1 << bit_off);
534 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause);
535
536 return (MSI_IRQ + bit_off);
537 }
538
539 int
mv_msi_data(int irq,uint64_t * addr,uint32_t * data)540 mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
541 {
542 u_long phys, base, size;
543 phandle_t node;
544 int error;
545
546 node = ofw_bus_get_node(mv_mpic_sc->sc_dev);
547
548 /* Get physical address of register space */
549 error = fdt_get_range(OF_parent(node), 0, &phys, &size);
550 if (error) {
551 printf("%s: Cannot get register physical address, err:%d",
552 __func__, error);
553 return (error);
554 }
555
556 /* Get offset of MPIC register space */
557 error = fdt_regsize(node, &base, &size);
558 if (error) {
559 printf("%s: Cannot get MPIC register offset, err:%d",
560 __func__, error);
561 return (error);
562 }
563
564 *addr = phys + base + MPIC_SOFT_INT;
565 *data = MPIC_SOFT_INT_DRBL1 | irq;
566
567 return (0);
568 }
569
570 void
mpic_init_secondary(device_t dev)571 mpic_init_secondary(device_t dev)
572 {
573 }
574
575 void
mpic_ipi_send(device_t dev,struct intr_irqsrc * isrc,cpuset_t cpus,u_int ipi)576 mpic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, u_int ipi)
577 {
578 uint32_t val, i;
579
580 val = 0x00000000;
581 for (i = 0; i < MAXCPU; i++)
582 if (CPU_ISSET(i, &cpus))
583 val |= (1 << (8 + i));
584 val |= ipi;
585 MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val);
586 }
587
588 int
mpic_ipi_read(int i __unused)589 mpic_ipi_read(int i __unused)
590 {
591 uint32_t val;
592 int ipi;
593
594 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);
595 if (val) {
596 ipi = ffs(val) - 1;
597 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi));
598 return (ipi);
599 }
600
601 return (0x3ff);
602 }
603
604 void
mpic_ipi_clear(int ipi)605 mpic_ipi_clear(int ipi)
606 {
607 }
608