1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/rman.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <machine/bus.h>
36
37 #include <dev/fdt/simplebus.h>
38
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41
42 #if defined(__aarch64__)
43 #include "opt_soc.h"
44 #endif
45
46 #include <dev/extres/clk/clk_div.h>
47 #include <dev/extres/clk/clk_fixed.h>
48 #include <dev/extres/clk/clk_mux.h>
49
50 #include <arm/allwinner/clkng/aw_ccung.h>
51
52 #include <dt-bindings/clock/sun8i-r-ccu.h>
53 #include <dt-bindings/reset/sun8i-r-ccu.h>
54
55 /* Non-exported clocks */
56 #define CLK_AHB0 1
57 #define CLK_APB0 2
58
59 static struct aw_ccung_reset ccu_sun8i_r_resets[] = {
60 CCU_RESET(RST_APB0_IR, 0xb0, 1)
61 CCU_RESET(RST_APB0_TIMER, 0xb0, 2)
62 CCU_RESET(RST_APB0_RSB, 0xb0, 3)
63 CCU_RESET(RST_APB0_UART, 0xb0, 4)
64 CCU_RESET(RST_APB0_I2C, 0xb0, 6)
65 };
66
67 static struct aw_ccung_gate ccu_sun8i_r_gates[] = {
68 CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x28, 0)
69 CCU_GATE(CLK_APB0_IR, "apb0-ir", "apb0", 0x28, 1)
70 CCU_GATE(CLK_APB0_TIMER, "apb0-timer", "apb0", 0x28, 2)
71 CCU_GATE(CLK_APB0_RSB, "apb0-rsb", "apb0", 0x28, 3)
72 CCU_GATE(CLK_APB0_UART, "apb0-uart", "apb0", 0x28, 4)
73 CCU_GATE(CLK_APB0_I2C, "apb0-i2c", "apb0", 0x28, 6)
74 CCU_GATE(CLK_APB0_TWD, "apb0-twd", "apb0", 0x28, 7)
75 };
76
77 static const char *ar100_parents[] = {"osc32k", "osc24M", "pll_periph0", "iosc"};
78 static const char *a83t_ar100_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "osc16M"};
79 PREDIV_CLK(ar100_clk, CLK_AR100, /* id */
80 "ar100", ar100_parents, /* name, parents */
81 0x00, /* offset */
82 16, 2, /* mux */
83 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
84 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
85 16, 2, 2); /* prediv condition */
86 PREDIV_CLK(a83t_ar100_clk, CLK_AR100, /* id */
87 "ar100", a83t_ar100_parents, /* name, parents */
88 0x00, /* offset */
89 16, 2, /* mux */
90 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
91 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
92 16, 2, 2); /* prediv condition */
93
94 static const char *ahb0_parents[] = {"ar100"};
95 FIXED_CLK(ahb0_clk,
96 CLK_AHB0, /* id */
97 "ahb0", /* name */
98 ahb0_parents, /* parent */
99 0, /* freq */
100 1, /* mult */
101 1, /* div */
102 0); /* flags */
103
104 static const char *apb0_parents[] = {"ahb0"};
105 DIV_CLK(apb0_clk,
106 CLK_APB0, /* id */
107 "apb0", apb0_parents, /* name, parents */
108 0x0c, /* offset */
109 0, 2, /* shift, width */
110 0, NULL); /* flags, div table */
111
112 static const char *r_ccu_ir_parents[] = {"osc32k", "osc24M"};
113 NM_CLK(r_ccu_ir_clk,
114 CLK_IR, /* id */
115 "ir", r_ccu_ir_parents, /* names, parents */
116 0x54, /* offset */
117 0, 4, 0, 0, /* N factor */
118 16, 2, 0, 0, /* M factor */
119 24, 2, /* mux */
120 31, /* gate */
121 AW_CLK_HAS_MUX | AW_CLK_REPARENT | AW_CLK_HAS_GATE);/* flags */
122
123 static const char *a83t_ir_parents[] = {"osc16M", "osc24M"};
124 static struct aw_clk_nm_def a83t_ir_clk = {
125 .clkdef = {
126 .id = CLK_IR,
127 .name = "ir",
128 .parent_names = a83t_ir_parents,
129 .parent_cnt = nitems(a83t_ir_parents),
130 },
131 .offset = 0x54,
132 .n = {.shift = 0, .width = 4, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
133 .m = {.shift = 16, .width = 2},
134 .prediv = {
135 .cond_shift = 24,
136 .cond_width = 2,
137 .cond_value = 0,
138 .value = 16
139 },
140 .mux_shift = 24,
141 .mux_width = 2,
142 .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_PREDIV,
143 };
144
145 static struct aw_ccung_clk clks[] = {
146 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ar100_clk},
147 { .type = AW_CLK_DIV, .clk.div = &apb0_clk},
148 { .type = AW_CLK_FIXED, .clk.fixed = &ahb0_clk},
149 { .type = AW_CLK_NM, .clk.nm = &r_ccu_ir_clk},
150 };
151
152 static struct aw_ccung_clk a83t_clks[] = {
153 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &a83t_ar100_clk},
154 { .type = AW_CLK_DIV, .clk.div = &apb0_clk},
155 { .type = AW_CLK_FIXED, .clk.fixed = &ahb0_clk},
156 { .type = AW_CLK_NM, .clk.nm = &a83t_ir_clk},
157 };
158
159 static struct ofw_compat_data compat_data[] = {
160 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
161 { "allwinner,sun8i-h3-r-ccu", 1 },
162 #endif
163 #if defined(SOC_ALLWINNER_A64)
164 { "allwinner,sun50i-a64-r-ccu", 1 },
165 #endif
166 { NULL, 0},
167 };
168
169 static int
ccu_sun8i_r_probe(device_t dev)170 ccu_sun8i_r_probe(device_t dev)
171 {
172
173 if (!ofw_bus_status_okay(dev))
174 return (ENXIO);
175
176 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
177 return (ENXIO);
178
179 device_set_desc(dev, "Allwinner SUN8I_R Clock Control Unit NG");
180 return (BUS_PROBE_DEFAULT);
181 }
182
183 static int
ccu_sun8i_r_attach(device_t dev)184 ccu_sun8i_r_attach(device_t dev)
185 {
186 struct aw_ccung_softc *sc;
187
188 sc = device_get_softc(dev);
189
190 sc->resets = ccu_sun8i_r_resets;
191 sc->nresets = nitems(ccu_sun8i_r_resets);
192 sc->gates = ccu_sun8i_r_gates;
193 sc->ngates = nitems(ccu_sun8i_r_gates);
194 sc->clks = clks;
195 sc->nclks = nitems(clks);
196
197 return (aw_ccung_attach(dev));
198 }
199
200 static device_method_t ccu_sun8i_r_methods[] = {
201 /* Device interface */
202 DEVMETHOD(device_probe, ccu_sun8i_r_probe),
203 DEVMETHOD(device_attach, ccu_sun8i_r_attach),
204
205 DEVMETHOD_END
206 };
207
208 static devclass_t ccu_sun8i_r_devclass;
209
210 DEFINE_CLASS_1(ccu_sun8i_r, ccu_sun8i_r_driver, ccu_sun8i_r_methods,
211 sizeof(struct aw_ccung_softc), aw_ccung_driver);
212
213 EARLY_DRIVER_MODULE(ccu_sun8i_r, simplebus, ccu_sun8i_r_driver,
214 ccu_sun8i_r_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
215
216 static int
ccu_a83t_r_probe(device_t dev)217 ccu_a83t_r_probe(device_t dev)
218 {
219
220 if (!ofw_bus_status_okay(dev))
221 return (ENXIO);
222
223 if (!ofw_bus_is_compatible(dev, "allwinner,sun8i-a83t-r-ccu"))
224 return (ENXIO);
225
226 device_set_desc(dev, "Allwinner A83T_R Clock Control Unit NG");
227 return (BUS_PROBE_DEFAULT);
228 }
229
230 static int
ccu_a83t_r_attach(device_t dev)231 ccu_a83t_r_attach(device_t dev)
232 {
233 struct aw_ccung_softc *sc;
234
235 sc = device_get_softc(dev);
236
237 sc->resets = ccu_sun8i_r_resets;
238 sc->nresets = nitems(ccu_sun8i_r_resets);
239 sc->gates = ccu_sun8i_r_gates;
240 sc->ngates = nitems(ccu_sun8i_r_gates);
241 sc->clks = a83t_clks;
242 sc->nclks = nitems(a83t_clks);
243
244 return (aw_ccung_attach(dev));
245 }
246
247 static device_method_t ccu_a83t_r_methods[] = {
248 /* Device interface */
249 DEVMETHOD(device_probe, ccu_a83t_r_probe),
250 DEVMETHOD(device_attach, ccu_a83t_r_attach),
251
252 DEVMETHOD_END
253 };
254
255 static devclass_t ccu_a83t_r_devclass;
256
257 DEFINE_CLASS_1(ccu_a83t_r, ccu_a83t_r_driver, ccu_a83t_r_methods,
258 sizeof(struct aw_ccung_softc), aw_ccung_driver);
259
260 EARLY_DRIVER_MODULE(ccu_a83t_r, simplebus, ccu_a83t_r_driver,
261 ccu_a83t_r_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
262