1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2006 Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: stable/12/sys/sparc64/sparc64/upa.c 332310 2018-04-08 22:59:34Z gonzo $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/resource.h>
38 #include <sys/rman.h>
39
40 #include <dev/ofw/ofw_bus.h>
41 #include <dev/ofw/ofw_bus_subr.h>
42 #include <dev/ofw/openfirm.h>
43
44 #include <machine/bus.h>
45 #include <machine/bus_common.h>
46 #include <machine/intr_machdep.h>
47 #include <machine/resource.h>
48
49 #define UPA_NREG 3
50
51 #define UPA_CFG 0
52 #define UPA_IMR1 1
53 #define UPA_IMR2 2
54
55 /* UPA_CFG bank */
56 #define UPA_CFG_UPA0 0x00 /* UPA0 config register */
57 #define UPA_CFG_UPA1 0x08 /* UPA1 config register */
58 #define UPA_CFG_IF 0x10 /* interface config register */
59 #define UPA_CFG_IF_RST 0x00
60 #define UPA_CFG_IF_POK_RST 0x02
61 #define UPA_CFG_IF_POK 0x03
62 #define UPA_CFG_ESTAR 0x18 /* Estar config register */
63 #define UPA_CFG_ESTAR_SPEED_FULL 0x01
64 #define UPA_CFG_ESTAR_SPEED_1_2 0x02
65 #define UPA_CFG_ESTAR_SPEED_1_64 0x40
66
67 #define UPA_INO_BASE 0x2a
68 #define UPA_INO_MAX 0x2b
69
70 struct upa_regs {
71 uint64_t phys;
72 uint64_t size;
73 };
74
75 struct upa_ranges {
76 uint64_t child;
77 uint64_t parent;
78 uint64_t size;
79 };
80
81 struct upa_devinfo {
82 struct ofw_bus_devinfo udi_obdinfo;
83 struct resource_list udi_rl;
84 };
85
86 struct upa_softc {
87 struct resource *sc_res[UPA_NREG];
88 bus_space_tag_t sc_bt[UPA_NREG];
89 bus_space_handle_t sc_bh[UPA_NREG];
90
91 uint32_t sc_ign;
92
93 int sc_nrange;
94 struct upa_ranges *sc_ranges;
95 };
96
97 #define UPA_READ(sc, reg, off) \
98 bus_space_read_8((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off))
99 #define UPA_WRITE(sc, reg, off, val) \
100 bus_space_write_8((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off), (val))
101
102 static device_probe_t upa_probe;
103 static device_attach_t upa_attach;
104 static bus_print_child_t upa_print_child;
105 static bus_probe_nomatch_t upa_probe_nomatch;
106 static bus_alloc_resource_t upa_alloc_resource;
107 static bus_adjust_resource_t upa_adjust_resource;
108 static bus_setup_intr_t upa_setup_intr;
109 static bus_get_resource_list_t upa_get_resource_list;
110 static ofw_bus_get_devinfo_t upa_get_devinfo;
111
112 static void upa_intr_enable(void *);
113 static void upa_intr_disable(void *);
114 static void upa_intr_assign(void *);
115 static struct upa_devinfo *upa_setup_dinfo(device_t, struct upa_softc *,
116 phandle_t, uint32_t);
117 static void upa_destroy_dinfo(struct upa_devinfo *);
118 static int upa_print_res(struct upa_devinfo *);
119
120 static device_method_t upa_methods[] = {
121 /* Device interface */
122 DEVMETHOD(device_probe, upa_probe),
123 DEVMETHOD(device_attach, upa_attach),
124 DEVMETHOD(device_shutdown, bus_generic_shutdown),
125 DEVMETHOD(device_suspend, bus_generic_suspend),
126 DEVMETHOD(device_resume, bus_generic_resume),
127
128 /* Bus interface */
129 DEVMETHOD(bus_print_child, upa_print_child),
130 DEVMETHOD(bus_probe_nomatch, upa_probe_nomatch),
131 DEVMETHOD(bus_read_ivar, bus_generic_read_ivar),
132 DEVMETHOD(bus_write_ivar, bus_generic_write_ivar),
133 DEVMETHOD(bus_alloc_resource, upa_alloc_resource),
134 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
135 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
136 DEVMETHOD(bus_adjust_resource, upa_adjust_resource),
137 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
138 DEVMETHOD(bus_setup_intr, upa_setup_intr),
139 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
140 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
141 DEVMETHOD(bus_get_resource_list, upa_get_resource_list),
142 DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str),
143
144 /* ofw_bus interface */
145 DEVMETHOD(ofw_bus_get_devinfo, upa_get_devinfo),
146 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
147 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
148 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
149 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
150 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
151
152 DEVMETHOD_END
153 };
154
155 static devclass_t upa_devclass;
156
157 DEFINE_CLASS_0(upa, upa_driver, upa_methods, sizeof(struct upa_softc));
158 EARLY_DRIVER_MODULE(upa, nexus, upa_driver, upa_devclass, 0, 0, BUS_PASS_BUS);
159
160 static const struct intr_controller upa_ic = {
161 upa_intr_enable,
162 upa_intr_disable,
163 upa_intr_assign,
164 /* The interrupts are pulse type and thus automatically cleared. */
165 NULL
166 };
167
168 struct upa_icarg {
169 struct upa_softc *uica_sc;
170 u_int uica_imr;
171 };
172
173 static int
upa_probe(device_t dev)174 upa_probe(device_t dev)
175 {
176 const char* compat;
177
178 compat = ofw_bus_get_compat(dev);
179 if (compat != NULL && strcmp(ofw_bus_get_name(dev), "upa") == 0 &&
180 strcmp(compat, "upa64s") == 0) {
181 device_set_desc(dev, "UPA bridge");
182 return (BUS_PROBE_DEFAULT);
183 }
184 return (ENXIO);
185 }
186
187 static int
upa_attach(device_t dev)188 upa_attach(device_t dev)
189 {
190 struct upa_devinfo *udi;
191 struct upa_icarg *uica;
192 struct upa_softc *sc;
193 phandle_t child, node;
194 device_t cdev;
195 uint32_t portid;
196 int i, imr, j, rid;
197 #if 1
198 device_t *children, schizo;
199 rman_res_t scount, sstart, ucount, ustart;
200 int nchildren;
201 #endif
202
203 sc = device_get_softc(dev);
204 node = ofw_bus_get_node(dev);
205 for (i = UPA_CFG; i <= UPA_IMR2; i++) {
206 rid = i;
207 /*
208 * The UPA_IMR{1,2} resources are shared with that of the
209 * Schizo PCI bus B CSR bank.
210 */
211 #if 0
212 sc->sc_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
213 &rid, ((i == UPA_IMR1 || i == UPA_IMR2) ? RF_SHAREABLE :
214 0) | RF_ACTIVE);
215 if (sc->sc_res[i] == NULL) {
216 device_printf(dev,
217 "could not allocate resource %d\n", i);
218 goto fail;
219 }
220 sc->sc_bt[i] = rman_get_bustag(sc->sc_res[i]);
221 sc->sc_bh[i] = rman_get_bushandle(sc->sc_res[i]);
222 #else
223 /*
224 * Workaround for the fact that rman(9) only allows to
225 * share resources of the same size.
226 */
227 if (i == UPA_IMR1 || i == UPA_IMR2) {
228 if (bus_get_resource(dev, SYS_RES_MEMORY, i, &ustart,
229 &ucount) != 0) {
230 device_printf(dev,
231 "could not determine UPA resource\n");
232 goto fail;
233 }
234 if (device_get_children(device_get_parent(dev),
235 &children, &nchildren) != 0) {
236 device_printf(dev, "could not get children\n");
237 goto fail;
238 }
239 schizo = NULL;
240 for (j = 0; j < nchildren; j++) {
241 if (ofw_bus_get_type(children[j]) != NULL &&
242 strcmp(ofw_bus_get_type(children[j]),
243 "pci") == 0 &&
244 ofw_bus_get_compat(children[j]) != NULL &&
245 strcmp(ofw_bus_get_compat(children[j]),
246 "pci108e,8001") == 0 &&
247 ((bus_get_resource_start(children[j],
248 SYS_RES_MEMORY, 0) >> 20) & 1) == 1) {
249 schizo = children[j];
250 break;
251 }
252 }
253 free(children, M_TEMP);
254 if (schizo == NULL) {
255 device_printf(dev, "could not find Schizo\n");
256 goto fail;
257 }
258 if (bus_get_resource(schizo, SYS_RES_MEMORY, 0,
259 &sstart, &scount) != 0) {
260 device_printf(dev,
261 "could not determine Schizo resource\n");
262 goto fail;
263 }
264 sc->sc_res[i] = bus_alloc_resource(dev, SYS_RES_MEMORY,
265 &rid, sstart, sstart + scount - 1, scount,
266 RF_SHAREABLE | RF_ACTIVE);
267 } else
268 sc->sc_res[i] = bus_alloc_resource_any(dev,
269 SYS_RES_MEMORY, &rid, RF_ACTIVE);
270 if (sc->sc_res[i] == NULL) {
271 device_printf(dev,
272 "could not allocate resource %d\n", i);
273 goto fail;
274 }
275 sc->sc_bt[i] = rman_get_bustag(sc->sc_res[i]);
276 sc->sc_bh[i] = rman_get_bushandle(sc->sc_res[i]);
277 if (i == UPA_IMR1 || i == UPA_IMR2)
278 bus_space_subregion(sc->sc_bt[i], sc->sc_bh[i],
279 ustart - sstart, ucount, &sc->sc_bh[i]);
280 #endif
281 }
282
283 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) {
284 device_printf(dev, "could not determine IGN\n");
285 goto fail;
286 }
287
288 sc->sc_nrange = OF_getprop_alloc_multi(node, "ranges", sizeof(*sc->sc_ranges),
289 (void **)&sc->sc_ranges);
290 if (sc->sc_nrange == -1) {
291 device_printf(dev, "could not determine ranges\n");
292 goto fail;
293 }
294
295 /*
296 * Hunt through all the interrupt mapping regs and register our
297 * interrupt controller for the corresponding interrupt vectors.
298 * We do this early in order to be able to catch stray interrupts.
299 */
300 for (i = UPA_INO_BASE; i <= UPA_INO_MAX; i++) {
301 imr = 0;
302 for (j = UPA_IMR1; j <= UPA_IMR2; j++) {
303 if (INTVEC(UPA_READ(sc, j, 0x0)) ==
304 INTMAP_VEC(sc->sc_ign, i)) {
305 imr = j;
306 break;
307 }
308 }
309 if (imr == 0)
310 continue;
311 uica = malloc(sizeof(*uica), M_DEVBUF, M_NOWAIT);
312 if (uica == NULL)
313 panic("%s: could not allocate interrupt controller "
314 "argument", __func__);
315 uica->uica_sc = sc;
316 uica->uica_imr = imr;
317 #ifdef UPA_DEBUG
318 device_printf(dev, "intr map (INO %d) IMR%d: %#lx\n",
319 i, imr, (u_long)UPA_READ(sc, imr, 0x0));
320 #endif
321 j = intr_controller_register(INTMAP_VEC(sc->sc_ign, i),
322 &upa_ic, uica);
323 if (j != 0)
324 device_printf(dev, "could not register interrupt "
325 "controller for INO %d (%d)\n", i, j);
326 }
327
328 /* Make sure the power level is appropriate for normal operation. */
329 if (UPA_READ(sc, UPA_CFG, UPA_CFG_IF) != UPA_CFG_IF_POK) {
330 if (bootverbose)
331 device_printf(dev, "applying power\n");
332 UPA_WRITE(sc, UPA_CFG, UPA_CFG_ESTAR, UPA_CFG_ESTAR_SPEED_1_2);
333 UPA_WRITE(sc, UPA_CFG, UPA_CFG_ESTAR, UPA_CFG_ESTAR_SPEED_FULL);
334 (void)UPA_READ(sc, UPA_CFG, UPA_CFG_ESTAR);
335 UPA_WRITE(sc, UPA_CFG, UPA_CFG_IF, UPA_CFG_IF_POK_RST);
336 (void)UPA_READ(sc, UPA_CFG, UPA_CFG_IF);
337 DELAY(20000);
338 UPA_WRITE(sc, UPA_CFG, UPA_CFG_IF, UPA_CFG_IF_POK);
339 (void)UPA_READ(sc, UPA_CFG, UPA_CFG_IF);
340 }
341
342 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
343 /*
344 * The `upa-portid' properties of the children are used as
345 * index for the interrupt mapping registers.
346 * The `upa-portid' properties are also used to make up the
347 * INOs of the children as the values contained in their
348 * `interrupts' properties are bogus.
349 */
350 if (OF_getprop(child, "upa-portid", &portid,
351 sizeof(portid)) == -1) {
352 device_printf(dev,
353 "could not determine upa-portid of child 0x%lx\n",
354 (unsigned long)child);
355 continue;
356 }
357 if (portid > 1) {
358 device_printf(dev,
359 "upa-portid %d of child 0x%lx invalid\n", portid,
360 (unsigned long)child);
361 continue;
362 }
363 if ((udi = upa_setup_dinfo(dev, sc, child, portid)) == NULL)
364 continue;
365 if ((cdev = device_add_child(dev, NULL, -1)) == NULL) {
366 device_printf(dev, "<%s>: device_add_child failed\n",
367 udi->udi_obdinfo.obd_name);
368 upa_destroy_dinfo(udi);
369 continue;
370 }
371 device_set_ivars(cdev, udi);
372 }
373
374 return (bus_generic_attach(dev));
375
376 fail:
377 for (i = UPA_CFG; i <= UPA_IMR2 && sc->sc_res[i] != NULL; i++)
378 bus_release_resource(dev, SYS_RES_MEMORY,
379 rman_get_rid(sc->sc_res[i]), sc->sc_res[i]);
380 return (ENXIO);
381 }
382
383 static int
upa_print_child(device_t dev,device_t child)384 upa_print_child(device_t dev, device_t child)
385 {
386 int rv;
387
388 rv = bus_print_child_header(dev, child);
389 rv += upa_print_res(device_get_ivars(child));
390 rv += bus_print_child_footer(dev, child);
391 return (rv);
392 }
393
394 static void
upa_probe_nomatch(device_t dev,device_t child)395 upa_probe_nomatch(device_t dev, device_t child)
396 {
397 const char *type;
398
399 device_printf(dev, "<%s>", ofw_bus_get_name(child));
400 upa_print_res(device_get_ivars(child));
401 type = ofw_bus_get_type(child);
402 printf(" type %s (no driver attached)\n",
403 type != NULL ? type : "unknown");
404 }
405
406 static struct resource *
upa_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)407 upa_alloc_resource(device_t dev, device_t child, int type, int *rid,
408 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
409 {
410 struct resource_list *rl;
411 struct resource_list_entry *rle;
412 struct upa_softc *sc;
413 struct resource *rv;
414 bus_addr_t cend, cstart;
415 int i, isdefault, passthrough;
416
417 isdefault = RMAN_IS_DEFAULT_RANGE(start, end);
418 passthrough = (device_get_parent(child) != dev);
419 sc = device_get_softc(dev);
420 rl = BUS_GET_RESOURCE_LIST(dev, child);
421 rle = NULL;
422 switch (type) {
423 case SYS_RES_IRQ:
424 return (resource_list_alloc(rl, dev, child, type, rid, start,
425 end, count, flags));
426 case SYS_RES_MEMORY:
427 if (!passthrough) {
428 rle = resource_list_find(rl, type, *rid);
429 if (rle == NULL)
430 return (NULL);
431 if (rle->res != NULL)
432 panic("%s: resource entry is busy", __func__);
433 if (isdefault) {
434 start = rle->start;
435 count = ulmax(count, rle->count);
436 end = ulmax(rle->end, start + count - 1);
437 }
438 }
439 for (i = 0; i < sc->sc_nrange; i++) {
440 cstart = sc->sc_ranges[i].child;
441 cend = cstart + sc->sc_ranges[i].size - 1;
442 if (start < cstart || start > cend)
443 continue;
444 if (end < cstart || end > cend)
445 return (NULL);
446 start += sc->sc_ranges[i].parent - cstart;
447 end += sc->sc_ranges[i].parent - cstart;
448 rv = bus_generic_alloc_resource(dev, child, type, rid,
449 start, end, count, flags);
450 if (!passthrough)
451 rle->res = rv;
452 return (rv);
453 }
454 /* FALLTHROUGH */
455 default:
456 return (NULL);
457 }
458 }
459
460 static void
upa_intr_enable(void * arg)461 upa_intr_enable(void *arg)
462 {
463 struct intr_vector *iv = arg;
464 struct upa_icarg *uica = iv->iv_icarg;
465
466 UPA_WRITE(uica->uica_sc, uica->uica_imr, 0x0,
467 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
468 (void)UPA_READ(uica->uica_sc, uica->uica_imr, 0x0);
469 }
470
471 static void
upa_intr_disable(void * arg)472 upa_intr_disable(void *arg)
473 {
474 struct intr_vector *iv = arg;
475 struct upa_icarg *uica = iv->iv_icarg;
476
477 UPA_WRITE(uica->uica_sc, uica->uica_imr, 0x0, iv->iv_vec);
478 (void)UPA_READ(uica->uica_sc, uica->uica_imr, 0x0);
479 }
480
481 static void
upa_intr_assign(void * arg)482 upa_intr_assign(void *arg)
483 {
484 struct intr_vector *iv = arg;
485 struct upa_icarg *uica = iv->iv_icarg;
486
487 UPA_WRITE(uica->uica_sc, uica->uica_imr, 0x0, INTMAP_TID(
488 UPA_READ(uica->uica_sc, uica->uica_imr, 0x0), iv->iv_mid));
489 (void)UPA_READ(uica->uica_sc, uica->uica_imr, 0x0);
490 }
491
492 static int
upa_setup_intr(device_t dev,device_t child,struct resource * ires,int flags,driver_filter_t * filt,driver_intr_t * func,void * arg,void ** cookiep)493 upa_setup_intr(device_t dev, device_t child, struct resource *ires, int flags,
494 driver_filter_t *filt, driver_intr_t *func, void *arg, void **cookiep)
495 {
496 struct upa_softc *sc;
497 u_long vec;
498
499 sc = device_get_softc(dev);
500 /*
501 * Make sure the vector is fully specified and we registered
502 * our interrupt controller for it.
503 */
504 vec = rman_get_start(ires);
505 if (INTIGN(vec) != sc->sc_ign || intr_vectors[vec].iv_ic != &upa_ic) {
506 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
507 return (EINVAL);
508 }
509 return (bus_generic_setup_intr(dev, child, ires, flags, filt, func,
510 arg, cookiep));
511 }
512
513 static int
upa_adjust_resource(device_t bus __unused,device_t child __unused,int type __unused,struct resource * r __unused,rman_res_t start __unused,rman_res_t end __unused)514 upa_adjust_resource(device_t bus __unused, device_t child __unused,
515 int type __unused, struct resource *r __unused, rman_res_t start __unused,
516 rman_res_t end __unused)
517 {
518
519 return (ENXIO);
520 }
521
522 static struct resource_list *
upa_get_resource_list(device_t dev,device_t child)523 upa_get_resource_list(device_t dev, device_t child)
524 {
525 struct upa_devinfo *udi;
526
527 udi = device_get_ivars(child);
528 return (&udi->udi_rl);
529 }
530
531 static const struct ofw_bus_devinfo *
upa_get_devinfo(device_t dev,device_t child)532 upa_get_devinfo(device_t dev, device_t child)
533 {
534 struct upa_devinfo *udi;
535
536 udi = device_get_ivars(child);
537 return (&udi->udi_obdinfo);
538 }
539
540 static struct upa_devinfo *
upa_setup_dinfo(device_t dev,struct upa_softc * sc,phandle_t node,uint32_t portid)541 upa_setup_dinfo(device_t dev, struct upa_softc *sc, phandle_t node,
542 uint32_t portid)
543 {
544 struct upa_devinfo *udi;
545 struct upa_regs *reg;
546 uint32_t intr;
547 int i, nreg;
548
549 udi = malloc(sizeof(*udi), M_DEVBUF, M_WAITOK | M_ZERO);
550 if (ofw_bus_gen_setup_devinfo(&udi->udi_obdinfo, node) != 0) {
551 free(udi, M_DEVBUF);
552 return (NULL);
553 }
554 resource_list_init(&udi->udi_rl);
555
556 nreg = OF_getprop_alloc_multi(node, "reg", sizeof(*reg), (void **)®);
557 if (nreg == -1) {
558 device_printf(dev, "<%s>: incomplete\n",
559 udi->udi_obdinfo.obd_name);
560 goto fail;
561 }
562 for (i = 0; i < nreg; i++)
563 resource_list_add(&udi->udi_rl, SYS_RES_MEMORY, i, reg[i].phys,
564 reg[i].phys + reg[i].size - 1, reg[i].size);
565 OF_prop_free(reg);
566
567 intr = INTMAP_VEC(sc->sc_ign, (UPA_INO_BASE + portid));
568 resource_list_add(&udi->udi_rl, SYS_RES_IRQ, 0, intr, intr, 1);
569
570 return (udi);
571
572 fail:
573 upa_destroy_dinfo(udi);
574 return (NULL);
575 }
576
577 static void
upa_destroy_dinfo(struct upa_devinfo * dinfo)578 upa_destroy_dinfo(struct upa_devinfo *dinfo)
579 {
580
581 resource_list_free(&dinfo->udi_rl);
582 ofw_bus_gen_destroy_devinfo(&dinfo->udi_obdinfo);
583 free(dinfo, M_DEVBUF);
584 }
585
586 static int
upa_print_res(struct upa_devinfo * udi)587 upa_print_res(struct upa_devinfo *udi)
588 {
589 int rv;
590
591 rv = 0;
592 rv += resource_list_print_type(&udi->udi_rl, "mem", SYS_RES_MEMORY,
593 "%#jx");
594 rv += resource_list_print_type(&udi->udi_rl, "irq", SYS_RES_IRQ,
595 "%jd");
596 return (rv);
597 }
598