1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/12/sys/sparc64/include/dcr.h 326262 2017-11-27 15:10:39Z pfg $ 29 */ 30 31 #ifndef _MACHINE_DCR_H_ 32 #define _MACHINE_DCR_H_ 33 34 /* 35 * Definitions for the UltraSPARC-III Depatch Control Register (ASR 18). 36 */ 37 #define DCR_MS (1UL << 0) 38 #define DCR_IFPOE (1UL << 1) 39 #define DCR_SI (1UL << 3) 40 #define DCR_RPE (1UL << 4) 41 #define DCR_BPE (1UL << 5) 42 43 #define DCR_OBSDATA_SHIFT 6 44 #define DCR_OBSDATA_CT_BITS 8 45 #define DCR_OBSDATA_CT_MASK \ 46 (((1UL << DCR_OBSDATA_CT_BITS) - 1) << DCR_OBSDATA_SHIFT) 47 48 /* The following bits are valid for the UltraSPARC-III++/IV+ only. */ 49 #define DCR_IPE (1UL << 2) 50 51 #define DCR_OBSDATA_CTP_BITS 6 52 #define DCR_OBSDATA_CTP_MASK \ 53 (((1UL << DCR_OBSDATA_CTP_BITS) - 1) << DCR_OBSDATA_SHIFT) 54 55 #define DCR_DPE (1UL << 12) 56 57 /* The following bits are valid for the UltraSPARC-IV+ only. */ 58 #define DCR_BPM_SHIFT 13 59 #define DCR_BPM_BITS 2 60 #define DCR_BPM_MASK \ 61 (((1UL << DCR_BPM_BITS) - 1) << DCR_BPM_SHIFT) 62 #define DCR_BPM_1HIST_GSHARE (0UL << DCR_BPM_SHIFT) 63 #define DCR_BPM_2HIST_GSHARE (1UL << DCR_BPM_SHIFT) 64 #define DCR_BPM_PC (2UL << DCR_BPM_SHIFT) 65 #define DCR_BPM_2HIST_MIXED (3UL << DCR_BPM_SHIFT) 66 67 #define DCR_JPE (1UL << 15) 68 #define DCR_ITPE (1UL << 16) 69 #define DCR_DTPE (1UL << 17) 70 #define DCR_PPE (1UL << 18) 71 72 #endif /* _MACHINE_DCR_H_ */ 73