1 /*-
2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31 /*-
32 * Copyright (C) 2001 Benno Rice
33 * All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 *
44 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
49 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
55 */
56
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD: stable/12/sys/powerpc/aim/aim_machdep.c 372438 2022-08-21 11:31:16Z dim $");
59
60 #include "opt_ddb.h"
61 #include "opt_kstack_pages.h"
62 #include "opt_platform.h"
63
64 #include <sys/param.h>
65 #include <sys/proc.h>
66 #include <sys/systm.h>
67 #include <sys/bio.h>
68 #include <sys/buf.h>
69 #include <sys/bus.h>
70 #include <sys/cons.h>
71 #include <sys/cpu.h>
72 #include <sys/eventhandler.h>
73 #include <sys/exec.h>
74 #include <sys/imgact.h>
75 #include <sys/kdb.h>
76 #include <sys/kernel.h>
77 #include <sys/ktr.h>
78 #include <sys/linker.h>
79 #include <sys/lock.h>
80 #include <sys/malloc.h>
81 #include <sys/mbuf.h>
82 #include <sys/msgbuf.h>
83 #include <sys/mutex.h>
84 #include <sys/ptrace.h>
85 #include <sys/reboot.h>
86 #include <sys/rwlock.h>
87 #include <sys/signalvar.h>
88 #include <sys/syscallsubr.h>
89 #include <sys/sysctl.h>
90 #include <sys/sysent.h>
91 #include <sys/sysproto.h>
92 #include <sys/ucontext.h>
93 #include <sys/uio.h>
94 #include <sys/vmmeter.h>
95 #include <sys/vnode.h>
96
97 #include <net/netisr.h>
98
99 #include <vm/vm.h>
100 #include <vm/vm_extern.h>
101 #include <vm/vm_kern.h>
102 #include <vm/vm_page.h>
103 #include <vm/vm_map.h>
104 #include <vm/vm_object.h>
105 #include <vm/vm_pager.h>
106
107 #include <machine/altivec.h>
108 #ifndef __powerpc64__
109 #include <machine/bat.h>
110 #endif
111 #include <machine/cpu.h>
112 #include <machine/elf.h>
113 #include <machine/fpu.h>
114 #include <machine/hid.h>
115 #include <machine/kdb.h>
116 #include <machine/md_var.h>
117 #include <machine/metadata.h>
118 #include <machine/mmuvar.h>
119 #include <machine/pcb.h>
120 #include <machine/reg.h>
121 #include <machine/sigframe.h>
122 #include <machine/spr.h>
123 #include <machine/trap.h>
124 #include <machine/vmparam.h>
125 #include <machine/ofw_machdep.h>
126
127 #include <ddb/ddb.h>
128
129 #include <dev/ofw/openfirm.h>
130
131 #ifdef __powerpc64__
132 #include "mmu_oea64.h"
133 #endif
134
135 #ifndef __powerpc64__
136 struct bat battable[16];
137 #endif
138
139 #ifndef __powerpc64__
140 /* Bits for running on 64-bit systems in 32-bit mode. */
141 extern void *testppc64, *testppc64size;
142 extern void *restorebridge, *restorebridgesize;
143 extern void *rfid_patch, *rfi_patch1, *rfi_patch2;
144 extern void *trapcode64;
145
146 extern Elf_Addr _GLOBAL_OFFSET_TABLE_[];
147 #endif
148
149 extern void *rstcode, *rstcodeend;
150 extern void *trapcode, *trapcodeend;
151 extern void *hypertrapcode, *hypertrapcodeend;
152 extern void *generictrap, *generictrap64;
153 extern void *alitrap, *aliend;
154 extern void *dsitrap, *dsiend;
155 extern void *decrint, *decrsize;
156 extern void *extint, *extsize;
157 extern void *dblow, *dbend;
158 extern void *imisstrap, *imisssize;
159 extern void *dlmisstrap, *dlmisssize;
160 extern void *dsmisstrap, *dsmisssize;
161
162 extern void *ap_pcpu;
163 extern void __restartkernel(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr);
164
165 void aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry,
166 void *mdp, uint32_t mdp_cookie);
167 void aim_cpu_init(vm_offset_t toc);
168
169 void
aim_early_init(vm_offset_t fdt,vm_offset_t toc,vm_offset_t ofentry,void * mdp,uint32_t mdp_cookie)170 aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp,
171 uint32_t mdp_cookie)
172 {
173 register_t scratch;
174
175 /*
176 * If running from an FDT, make sure we are in real mode to avoid
177 * tromping on firmware page tables. Everything in the kernel assumes
178 * 1:1 mappings out of firmware, so this won't break anything not
179 * already broken. This doesn't work if there is live OF, since OF
180 * may internally use non-1:1 mappings.
181 */
182 if (ofentry == 0)
183 mtmsr(mfmsr() & ~(PSL_IR | PSL_DR));
184
185 #ifdef __powerpc64__
186 /*
187 * If in real mode, relocate to high memory so that the kernel
188 * can execute from the direct map.
189 */
190 if (!(mfmsr() & PSL_DR) &&
191 (vm_offset_t)&aim_early_init < DMAP_BASE_ADDRESS)
192 __restartkernel(fdt, 0, ofentry, mdp, mdp_cookie,
193 DMAP_BASE_ADDRESS, mfmsr());
194 #endif
195
196 /* Various very early CPU fix ups */
197 switch (mfpvr() >> 16) {
198 /*
199 * PowerPC 970 CPUs have a misfeature requested by Apple that
200 * makes them pretend they have a 32-byte cacheline. Turn this
201 * off before we measure the cacheline size.
202 */
203 case IBM970:
204 case IBM970FX:
205 case IBM970MP:
206 case IBM970GX:
207 scratch = mfspr(SPR_HID5);
208 scratch &= ~HID5_970_DCBZ_SIZE_HI;
209 mtspr(SPR_HID5, scratch);
210 break;
211 #ifdef __powerpc64__
212 case IBMPOWER7:
213 case IBMPOWER7PLUS:
214 case IBMPOWER8:
215 case IBMPOWER8E:
216 case IBMPOWER8NVL:
217 case IBMPOWER9:
218 /* XXX: get from ibm,slb-size in device tree */
219 n_slbs = 32;
220 break;
221 #endif
222 }
223 }
224
225 void
aim_cpu_init(vm_offset_t toc)226 aim_cpu_init(vm_offset_t toc)
227 {
228 size_t trap_offset, trapsize;
229 vm_offset_t trap;
230 register_t msr;
231 uint8_t *cache_check;
232 int cacheline_warn;
233 #ifndef __powerpc64__
234 register_t scratch;
235 int ppc64;
236 #endif
237
238 trap_offset = 0;
239 cacheline_warn = 0;
240
241 /* General setup for AIM CPUs */
242 psl_kernset = PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI;
243
244 #ifdef __powerpc64__
245 psl_kernset |= PSL_SF;
246 if (mfmsr() & PSL_HV)
247 psl_kernset |= PSL_HV;
248 #endif
249 psl_userset = psl_kernset | PSL_PR;
250 #ifdef __powerpc64__
251 psl_userset32 = psl_userset & ~PSL_SF;
252 #endif
253
254 /* Bits that users aren't allowed to change */
255 psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1);
256 /*
257 * Mask bits from the SRR1 that aren't really the MSR:
258 * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64)
259 */
260 psl_userstatic &= ~0x783f0000UL;
261
262 /*
263 * Initialize the interrupt tables and figure out our cache line
264 * size and whether or not we need the 64-bit bridge code.
265 */
266
267 /*
268 * Disable translation in case the vector area hasn't been
269 * mapped (G5). Note that no OFW calls can be made until
270 * translation is re-enabled.
271 */
272
273 msr = mfmsr();
274 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI);
275
276 /*
277 * Measure the cacheline size using dcbz
278 *
279 * Use EXC_PGM as a playground. We are about to overwrite it
280 * anyway, we know it exists, and we know it is cache-aligned.
281 */
282
283 cache_check = (void *)EXC_PGM;
284
285 for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++)
286 cache_check[cacheline_size] = 0xff;
287
288 __asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory");
289
290 /* Find the first byte dcbz did not zero to get the cache line size */
291 for (cacheline_size = 0; cacheline_size < 0x100 &&
292 cache_check[cacheline_size] == 0; cacheline_size++);
293
294 /* Work around psim bug */
295 if (cacheline_size == 0) {
296 cacheline_warn = 1;
297 cacheline_size = 32;
298 }
299
300 #ifndef __powerpc64__
301 /*
302 * Figure out whether we need to use the 64 bit PMAP. This works by
303 * executing an instruction that is only legal on 64-bit PPC (mtmsrd),
304 * and setting ppc64 = 0 if that causes a trap.
305 */
306
307 ppc64 = 1;
308
309 bcopy(&testppc64, (void *)EXC_PGM, (size_t)&testppc64size);
310 __syncicache((void *)EXC_PGM, (size_t)&testppc64size);
311
312 __asm __volatile("\
313 mfmsr %0; \
314 mtsprg2 %1; \
315 \
316 mtmsrd %0; \
317 mfsprg2 %1;"
318 : "=r"(scratch), "=r"(ppc64));
319
320 if (ppc64)
321 cpu_features |= PPC_FEATURE_64;
322
323 /*
324 * Now copy restorebridge into all the handlers, if necessary,
325 * and set up the trap tables.
326 */
327
328 if (cpu_features & PPC_FEATURE_64) {
329 /* Patch the two instances of rfi -> rfid */
330 bcopy(&rfid_patch,&rfi_patch1,4);
331 #ifdef KDB
332 /* rfi_patch2 is at the end of dbleave */
333 bcopy(&rfid_patch,&rfi_patch2,4);
334 #endif
335 }
336 #else /* powerpc64 */
337 cpu_features |= PPC_FEATURE_64;
338 #endif
339
340 trapsize = (size_t)&trapcodeend - (size_t)&trapcode;
341
342 /*
343 * Copy generic handler into every possible trap. Special cases will get
344 * different ones in a minute.
345 */
346 for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20)
347 bcopy(&trapcode, (void *)trap, trapsize);
348
349 #ifndef __powerpc64__
350 if (cpu_features & PPC_FEATURE_64) {
351 /*
352 * Copy a code snippet to restore 32-bit bridge mode
353 * to the top of every non-generic trap handler
354 */
355
356 trap_offset += (size_t)&restorebridgesize;
357 bcopy(&restorebridge, (void *)EXC_RST, trap_offset);
358 bcopy(&restorebridge, (void *)EXC_DSI, trap_offset);
359 bcopy(&restorebridge, (void *)EXC_ALI, trap_offset);
360 bcopy(&restorebridge, (void *)EXC_PGM, trap_offset);
361 bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset);
362 bcopy(&restorebridge, (void *)EXC_TRC, trap_offset);
363 bcopy(&restorebridge, (void *)EXC_BPT, trap_offset);
364 } else {
365
366 /*
367 * Use an IBAT and a DBAT to map the bottom 256M segment.
368 *
369 * It is very important to do it *now* to avoid taking a
370 * fault in .text / .data before the MMU is bootstrapped,
371 * because until then, the translation data has not been
372 * copied over from OpenFirmware, so our DSI/ISI will fail
373 * to find a match.
374 */
375
376 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
377 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
378
379 __asm (".balign 32; \n"
380 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
381 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
382 :: "r"(battable[0].batu), "r"(battable[0].batl));
383 }
384 #else
385 trapsize = (size_t)&hypertrapcodeend - (size_t)&hypertrapcode;
386 bcopy(&hypertrapcode, (void *)(EXC_HEA + trap_offset), trapsize);
387 bcopy(&hypertrapcode, (void *)(EXC_HMI + trap_offset), trapsize);
388 bcopy(&hypertrapcode, (void *)(EXC_HVI + trap_offset), trapsize);
389 #endif
390
391 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend -
392 (size_t)&rstcode);
393
394 #ifdef KDB
395 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbend -
396 (size_t)&dblow);
397 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbend -
398 (size_t)&dblow);
399 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbend -
400 (size_t)&dblow);
401 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend -
402 (size_t)&dblow);
403 #endif
404 bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&aliend -
405 (size_t)&alitrap);
406 bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsiend -
407 (size_t)&dsitrap);
408
409 #ifdef __powerpc64__
410 /* Set TOC base so that the interrupt code can get at it */
411 *((void **)TRAP_GENTRAP) = &generictrap;
412 *((register_t *)TRAP_TOCBASE) = toc;
413 #else
414 /* Set branch address for trap code */
415 if (cpu_features & PPC_FEATURE_64)
416 *((void **)TRAP_GENTRAP) = &generictrap64;
417 else
418 *((void **)TRAP_GENTRAP) = &generictrap;
419 *((void **)TRAP_TOCBASE) = _GLOBAL_OFFSET_TABLE_;
420
421 /* G2-specific TLB miss helper handlers */
422 bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize);
423 bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize);
424 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize);
425 #endif
426 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD);
427
428 /*
429 * Restore MSR
430 */
431 mtmsr(msr);
432
433 /* Warn if cachline size was not determined */
434 if (cacheline_warn == 1) {
435 printf("WARNING: cacheline size undetermined, setting to 32\n");
436 }
437
438 /*
439 * Initialise virtual memory. Use BUS_PROBE_GENERIC priority
440 * in case the platform module had a better idea of what we
441 * should do.
442 */
443 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00)
444 pmap_mmu_install(MMU_TYPE_P9H, BUS_PROBE_GENERIC);
445 else if (cpu_features & PPC_FEATURE_64)
446 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC);
447 else
448 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC);
449 }
450
451 /*
452 * Shutdown the CPU as much as possible.
453 */
454 void
cpu_halt(void)455 cpu_halt(void)
456 {
457
458 OF_exit();
459 }
460
461 int
ptrace_single_step(struct thread * td)462 ptrace_single_step(struct thread *td)
463 {
464 struct trapframe *tf;
465
466 tf = td->td_frame;
467 tf->srr1 |= PSL_SE;
468
469 return (0);
470 }
471
472 int
ptrace_clear_single_step(struct thread * td)473 ptrace_clear_single_step(struct thread *td)
474 {
475 struct trapframe *tf;
476
477 tf = td->td_frame;
478 tf->srr1 &= ~PSL_SE;
479
480 return (0);
481 }
482
483 void
kdb_cpu_clear_singlestep(void)484 kdb_cpu_clear_singlestep(void)
485 {
486
487 kdb_frame->srr1 &= ~PSL_SE;
488 }
489
490 void
kdb_cpu_set_singlestep(void)491 kdb_cpu_set_singlestep(void)
492 {
493
494 kdb_frame->srr1 |= PSL_SE;
495 }
496
497 /*
498 * Initialise a struct pcpu.
499 */
500 void
cpu_pcpu_init(struct pcpu * pcpu,int cpuid,size_t sz)501 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
502 {
503 #ifdef __powerpc64__
504 /* Copy the SLB contents from the current CPU */
505 memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb));
506 #endif
507 }
508
509 #ifndef __powerpc64__
510 uint64_t
va_to_vsid(pmap_t pm,vm_offset_t va)511 va_to_vsid(pmap_t pm, vm_offset_t va)
512 {
513 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
514 }
515
516 #endif
517
518 /*
519 * These functions need to provide addresses that both (a) work in real mode
520 * (or whatever mode/circumstances the kernel is in in early boot (now)) and
521 * (b) can still, in principle, work once the kernel is going. Because these
522 * rely on existing mappings/real mode, unmap is a no-op.
523 */
524 vm_offset_t
pmap_early_io_map(vm_paddr_t pa,vm_size_t size)525 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
526 {
527 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!"));
528
529 /*
530 * If we have the MMU up in early boot, assume it is 1:1. Otherwise,
531 * try to get the address in a memory region compatible with the
532 * direct map for efficiency later.
533 */
534 if (mfmsr() & PSL_DR)
535 return (pa);
536 else
537 return (DMAP_BASE_ADDRESS + pa);
538 }
539
540 void
pmap_early_io_unmap(vm_offset_t va,vm_size_t size)541 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
542 {
543
544 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!"));
545 }
546
547 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */
548 void
flush_disable_caches(void)549 flush_disable_caches(void)
550 {
551 register_t msr;
552 register_t msscr0;
553 register_t cache_reg;
554 volatile uint32_t *memp;
555 uint32_t temp;
556 int i;
557 int x;
558
559 msr = mfmsr();
560 powerpc_sync();
561 mtmsr(msr & ~(PSL_EE | PSL_DR));
562 msscr0 = mfspr(SPR_MSSCR0);
563 msscr0 &= ~MSSCR0_L2PFE;
564 mtspr(SPR_MSSCR0, msscr0);
565 powerpc_sync();
566 isync();
567 __asm__ __volatile__("dssall; sync");
568 powerpc_sync();
569 isync();
570 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
571 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
572 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
573
574 /* Lock the L1 Data cache. */
575 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF);
576 powerpc_sync();
577 isync();
578
579 mtspr(SPR_LDSTCR, 0);
580
581 /*
582 * Perform this in two stages: Flush the cache starting in RAM, then do it
583 * from ROM.
584 */
585 memp = (volatile uint32_t *)0x00000000;
586 for (i = 0; i < 128 * 1024; i++) {
587 temp = *memp;
588 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
589 memp += 32/sizeof(*memp);
590 }
591
592 memp = (volatile uint32_t *)0xfff00000;
593 x = 0xfe;
594
595 for (; x != 0xff;) {
596 mtspr(SPR_LDSTCR, x);
597 for (i = 0; i < 128; i++) {
598 temp = *memp;
599 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
600 memp += 32/sizeof(*memp);
601 }
602 x = ((x << 1) | 1) & 0xff;
603 }
604 mtspr(SPR_LDSTCR, 0);
605
606 cache_reg = mfspr(SPR_L2CR);
607 if (cache_reg & L2CR_L2E) {
608 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450);
609 mtspr(SPR_L2CR, cache_reg);
610 powerpc_sync();
611 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF);
612 while (mfspr(SPR_L2CR) & L2CR_L2HWF)
613 ; /* Busy wait for cache to flush */
614 powerpc_sync();
615 cache_reg &= ~L2CR_L2E;
616 mtspr(SPR_L2CR, cache_reg);
617 powerpc_sync();
618 mtspr(SPR_L2CR, cache_reg | L2CR_L2I);
619 powerpc_sync();
620 while (mfspr(SPR_L2CR) & L2CR_L2I)
621 ; /* Busy wait for L2 cache invalidate */
622 powerpc_sync();
623 }
624
625 cache_reg = mfspr(SPR_L3CR);
626 if (cache_reg & L3CR_L3E) {
627 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO);
628 mtspr(SPR_L3CR, cache_reg);
629 powerpc_sync();
630 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF);
631 while (mfspr(SPR_L3CR) & L3CR_L3HWF)
632 ; /* Busy wait for cache to flush */
633 powerpc_sync();
634 cache_reg &= ~L3CR_L3E;
635 mtspr(SPR_L3CR, cache_reg);
636 powerpc_sync();
637 mtspr(SPR_L3CR, cache_reg | L3CR_L3I);
638 powerpc_sync();
639 while (mfspr(SPR_L3CR) & L3CR_L3I)
640 ; /* Busy wait for L3 cache invalidate */
641 powerpc_sync();
642 }
643
644 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE);
645 powerpc_sync();
646 isync();
647
648 mtmsr(msr);
649 }
650
651 void
cpu_sleep(void)652 cpu_sleep(void)
653 {
654 static u_quad_t timebase = 0;
655 static register_t sprgs[4];
656 static register_t srrs[2];
657
658 jmp_buf resetjb;
659 struct thread *fputd;
660 struct thread *vectd;
661 register_t hid0;
662 register_t msr;
663 register_t saved_msr;
664
665 ap_pcpu = pcpup;
666
667 PCPU_SET(restore, &resetjb);
668
669 saved_msr = mfmsr();
670 fputd = PCPU_GET(fputhread);
671 vectd = PCPU_GET(vecthread);
672 if (fputd != NULL)
673 save_fpu(fputd);
674 if (vectd != NULL)
675 save_vec(vectd);
676 if (setjmp(resetjb) == 0) {
677 sprgs[0] = mfspr(SPR_SPRG0);
678 sprgs[1] = mfspr(SPR_SPRG1);
679 sprgs[2] = mfspr(SPR_SPRG2);
680 sprgs[3] = mfspr(SPR_SPRG3);
681 srrs[0] = mfspr(SPR_SRR0);
682 srrs[1] = mfspr(SPR_SRR1);
683 timebase = mftb();
684 powerpc_sync();
685 flush_disable_caches();
686 hid0 = mfspr(SPR_HID0);
687 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP;
688 powerpc_sync();
689 isync();
690 msr = mfmsr() | PSL_POW;
691 mtspr(SPR_HID0, hid0);
692 powerpc_sync();
693
694 while (1)
695 mtmsr(msr);
696 }
697 platform_smp_timebase_sync(timebase, 0);
698 PCPU_SET(curthread, curthread);
699 PCPU_SET(curpcb, curthread->td_pcb);
700 pmap_activate(curthread);
701 powerpc_sync();
702 mtspr(SPR_SPRG0, sprgs[0]);
703 mtspr(SPR_SPRG1, sprgs[1]);
704 mtspr(SPR_SPRG2, sprgs[2]);
705 mtspr(SPR_SPRG3, sprgs[3]);
706 mtspr(SPR_SRR0, srrs[0]);
707 mtspr(SPR_SRR1, srrs[1]);
708 mtmsr(saved_msr);
709 if (fputd == curthread)
710 enable_fpu(curthread);
711 if (vectd == curthread)
712 enable_vec(curthread);
713 powerpc_sync();
714 }
715
716