1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009, Oleksandr Tymoshenko
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: stable/12/sys/mips/atheros/if_arge.c 326259 2017-11-27 15:07:26Z pfg $");
32
33 /*
34 * AR71XX gigabit ethernet driver
35 */
36 #ifdef HAVE_KERNEL_OPTION_HEADERS
37 #include "opt_device_polling.h"
38 #endif
39
40 #include "opt_arge.h"
41
42 #include <sys/param.h>
43 #include <sys/endian.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
46 #include <sys/lock.h>
47 #include <sys/mbuf.h>
48 #include <sys/malloc.h>
49 #include <sys/mutex.h>
50 #include <sys/kernel.h>
51 #include <sys/module.h>
52 #include <sys/socket.h>
53 #include <sys/taskqueue.h>
54 #include <sys/sysctl.h>
55
56 #include <net/if.h>
57 #include <net/if_var.h>
58 #include <net/if_media.h>
59 #include <net/ethernet.h>
60 #include <net/if_types.h>
61
62 #include <net/bpf.h>
63
64 #include <machine/bus.h>
65 #include <machine/cache.h>
66 #include <machine/resource.h>
67 #include <vm/vm_param.h>
68 #include <vm/vm.h>
69 #include <vm/pmap.h>
70 #include <sys/bus.h>
71 #include <sys/rman.h>
72
73 #include <dev/mii/mii.h>
74 #include <dev/mii/miivar.h>
75
76 #include <dev/pci/pcireg.h>
77 #include <dev/pci/pcivar.h>
78
79 #include "opt_arge.h"
80
81 #if defined(ARGE_MDIO)
82 #include <dev/mdio/mdio.h>
83 #include <dev/etherswitch/miiproxy.h>
84 #include "mdio_if.h"
85 #endif
86
87
88 MODULE_DEPEND(arge, ether, 1, 1, 1);
89 MODULE_DEPEND(arge, miibus, 1, 1, 1);
90 MODULE_VERSION(arge, 1);
91
92 #include "miibus_if.h"
93
94 #include <net/ethernet.h>
95
96 #include <mips/atheros/ar71xxreg.h>
97 #include <mips/atheros/ar934xreg.h> /* XXX tsk! */
98 #include <mips/atheros/qca953xreg.h> /* XXX tsk! */
99 #include <mips/atheros/qca955xreg.h> /* XXX tsk! */
100 #include <mips/atheros/if_argevar.h>
101 #include <mips/atheros/ar71xx_setup.h>
102 #include <mips/atheros/ar71xx_cpudef.h>
103 #include <mips/atheros/ar71xx_macaddr.h>
104
105 typedef enum {
106 ARGE_DBG_MII = 0x00000001,
107 ARGE_DBG_INTR = 0x00000002,
108 ARGE_DBG_TX = 0x00000004,
109 ARGE_DBG_RX = 0x00000008,
110 ARGE_DBG_ERR = 0x00000010,
111 ARGE_DBG_RESET = 0x00000020,
112 ARGE_DBG_PLL = 0x00000040,
113 ARGE_DBG_ANY = 0xffffffff,
114 } arge_debug_flags;
115
116 static const char * arge_miicfg_str[] = {
117 "NONE",
118 "GMII",
119 "MII",
120 "RGMII",
121 "RMII",
122 "SGMII"
123 };
124
125 #ifdef ARGE_DEBUG
126 #define ARGEDEBUG(_sc, _m, ...) \
127 do { \
128 if (((_m) & (_sc)->arge_debug) || ((_m) == ARGE_DBG_ANY)) \
129 device_printf((_sc)->arge_dev, __VA_ARGS__); \
130 } while (0)
131 #else
132 #define ARGEDEBUG(_sc, _m, ...)
133 #endif
134
135 static int arge_attach(device_t);
136 static int arge_detach(device_t);
137 static void arge_flush_ddr(struct arge_softc *);
138 static int arge_ifmedia_upd(struct ifnet *);
139 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
140 static int arge_ioctl(struct ifnet *, u_long, caddr_t);
141 static void arge_init(void *);
142 static void arge_init_locked(struct arge_softc *);
143 static void arge_link_task(void *, int);
144 static void arge_update_link_locked(struct arge_softc *sc);
145 static void arge_set_pll(struct arge_softc *, int, int);
146 static int arge_miibus_readreg(device_t, int, int);
147 static void arge_miibus_statchg(device_t);
148 static int arge_miibus_writereg(device_t, int, int, int);
149 static int arge_probe(device_t);
150 static void arge_reset_dma(struct arge_softc *);
151 static int arge_resume(device_t);
152 static int arge_rx_ring_init(struct arge_softc *);
153 static void arge_rx_ring_free(struct arge_softc *sc);
154 static int arge_tx_ring_init(struct arge_softc *);
155 static void arge_tx_ring_free(struct arge_softc *);
156 #ifdef DEVICE_POLLING
157 static int arge_poll(struct ifnet *, enum poll_cmd, int);
158 #endif
159 static int arge_shutdown(device_t);
160 static void arge_start(struct ifnet *);
161 static void arge_start_locked(struct ifnet *);
162 static void arge_stop(struct arge_softc *);
163 static int arge_suspend(device_t);
164
165 static int arge_rx_locked(struct arge_softc *);
166 static void arge_tx_locked(struct arge_softc *);
167 static void arge_intr(void *);
168 static int arge_intr_filter(void *);
169 static void arge_tick(void *);
170
171 static void arge_hinted_child(device_t bus, const char *dname, int dunit);
172
173 /*
174 * ifmedia callbacks for multiPHY MAC
175 */
176 void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
177 int arge_multiphy_mediachange(struct ifnet *);
178
179 static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
180 static int arge_dma_alloc(struct arge_softc *);
181 static void arge_dma_free(struct arge_softc *);
182 static int arge_newbuf(struct arge_softc *, int);
183 static __inline void arge_fixup_rx(struct mbuf *);
184
185 static device_method_t arge_methods[] = {
186 /* Device interface */
187 DEVMETHOD(device_probe, arge_probe),
188 DEVMETHOD(device_attach, arge_attach),
189 DEVMETHOD(device_detach, arge_detach),
190 DEVMETHOD(device_suspend, arge_suspend),
191 DEVMETHOD(device_resume, arge_resume),
192 DEVMETHOD(device_shutdown, arge_shutdown),
193
194 /* MII interface */
195 DEVMETHOD(miibus_readreg, arge_miibus_readreg),
196 DEVMETHOD(miibus_writereg, arge_miibus_writereg),
197 DEVMETHOD(miibus_statchg, arge_miibus_statchg),
198
199 /* bus interface */
200 DEVMETHOD(bus_add_child, device_add_child_ordered),
201 DEVMETHOD(bus_hinted_child, arge_hinted_child),
202
203 DEVMETHOD_END
204 };
205
206 static driver_t arge_driver = {
207 "arge",
208 arge_methods,
209 sizeof(struct arge_softc)
210 };
211
212 static devclass_t arge_devclass;
213
214 DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
215 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
216
217 #if defined(ARGE_MDIO)
218 static int argemdio_probe(device_t);
219 static int argemdio_attach(device_t);
220 static int argemdio_detach(device_t);
221
222 /*
223 * Declare an additional, separate driver for accessing the MDIO bus.
224 */
225 static device_method_t argemdio_methods[] = {
226 /* Device interface */
227 DEVMETHOD(device_probe, argemdio_probe),
228 DEVMETHOD(device_attach, argemdio_attach),
229 DEVMETHOD(device_detach, argemdio_detach),
230
231 /* bus interface */
232 DEVMETHOD(bus_add_child, device_add_child_ordered),
233
234 /* MDIO access */
235 DEVMETHOD(mdio_readreg, arge_miibus_readreg),
236 DEVMETHOD(mdio_writereg, arge_miibus_writereg),
237 };
238
239 DEFINE_CLASS_0(argemdio, argemdio_driver, argemdio_methods,
240 sizeof(struct arge_softc));
241 static devclass_t argemdio_devclass;
242
243 DRIVER_MODULE(miiproxy, arge, miiproxy_driver, miiproxy_devclass, 0, 0);
244 DRIVER_MODULE(argemdio, nexus, argemdio_driver, argemdio_devclass, 0, 0);
245 DRIVER_MODULE(mdio, argemdio, mdio_driver, mdio_devclass, 0, 0);
246 #endif
247
248 static struct mtx miibus_mtx;
249
250 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
251
252 /*
253 * Flushes all
254 *
255 * XXX this needs to be done at interrupt time! Grr!
256 */
257 static void
arge_flush_ddr(struct arge_softc * sc)258 arge_flush_ddr(struct arge_softc *sc)
259 {
260 switch (sc->arge_mac_unit) {
261 case 0:
262 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_GE0);
263 break;
264 case 1:
265 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_GE1);
266 break;
267 default:
268 device_printf(sc->arge_dev, "%s: unknown unit (%d)\n",
269 __func__,
270 sc->arge_mac_unit);
271 break;
272 }
273 }
274
275 static int
arge_probe(device_t dev)276 arge_probe(device_t dev)
277 {
278
279 device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
280 return (BUS_PROBE_NOWILDCARD);
281 }
282
283 #ifdef ARGE_DEBUG
284 static void
arge_attach_intr_sysctl(device_t dev,struct sysctl_oid_list * parent)285 arge_attach_intr_sysctl(device_t dev, struct sysctl_oid_list *parent)
286 {
287 struct arge_softc *sc = device_get_softc(dev);
288 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
289 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
290 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
291 char sn[8];
292 int i;
293
294 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "intr",
295 CTLFLAG_RD, NULL, "Interrupt statistics");
296 child = SYSCTL_CHILDREN(tree);
297 for (i = 0; i < 32; i++) {
298 snprintf(sn, sizeof(sn), "%d", i);
299 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, sn, CTLFLAG_RD,
300 &sc->intr_stats.count[i], 0, "");
301 }
302 }
303 #endif
304
305 static void
arge_attach_sysctl(device_t dev)306 arge_attach_sysctl(device_t dev)
307 {
308 struct arge_softc *sc = device_get_softc(dev);
309 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
310 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
311
312 #ifdef ARGE_DEBUG
313 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
314 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
315 "arge interface debugging flags");
316 arge_attach_intr_sysctl(dev, SYSCTL_CHILDREN(tree));
317 #endif
318
319 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
320 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
321 "number of TX aligned packets");
322
323 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
324 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned,
325 0, "number of TX unaligned packets");
326
327 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
328 "tx_pkts_unaligned_start", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned_start,
329 0, "number of TX unaligned packets (start)");
330
331 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
332 "tx_pkts_unaligned_len", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned_len,
333 0, "number of TX unaligned packets (len)");
334
335 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
336 "tx_pkts_nosegs", CTLFLAG_RW, &sc->stats.tx_pkts_nosegs,
337 0, "number of TX packets fail with no ring slots avail");
338
339 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
340 "intr_stray_filter", CTLFLAG_RW, &sc->stats.intr_stray,
341 0, "number of stray interrupts (filter)");
342
343 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
344 "intr_stray_intr", CTLFLAG_RW, &sc->stats.intr_stray2,
345 0, "number of stray interrupts (intr)");
346
347 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
348 "intr_ok", CTLFLAG_RW, &sc->stats.intr_ok,
349 0, "number of OK interrupts");
350 #ifdef ARGE_DEBUG
351 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
352 CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
353 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
354 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
355 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
356 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
357 #endif
358 }
359
360 static void
arge_reset_mac(struct arge_softc * sc)361 arge_reset_mac(struct arge_softc *sc)
362 {
363 uint32_t reg;
364 uint32_t reset_reg;
365
366 ARGEDEBUG(sc, ARGE_DBG_RESET, "%s called\n", __func__);
367
368 /* Step 1. Soft-reset MAC */
369 ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
370 DELAY(20);
371
372 /* Step 2. Punt the MAC core from the central reset register */
373 /*
374 * XXX TODO: migrate this (and other) chip specific stuff into
375 * a chipdef method.
376 */
377 if (sc->arge_mac_unit == 0) {
378 reset_reg = RST_RESET_GE0_MAC;
379 } else {
380 reset_reg = RST_RESET_GE1_MAC;
381 }
382
383 /*
384 * AR934x (and later) also needs the MDIO block reset.
385 * XXX should methodize this!
386 */
387 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
388 ar71xx_soc == AR71XX_SOC_AR9342 ||
389 ar71xx_soc == AR71XX_SOC_AR9344) {
390 if (sc->arge_mac_unit == 0) {
391 reset_reg |= AR934X_RESET_GE0_MDIO;
392 } else {
393 reset_reg |= AR934X_RESET_GE1_MDIO;
394 }
395 }
396
397 if (ar71xx_soc == AR71XX_SOC_QCA9556 ||
398 ar71xx_soc == AR71XX_SOC_QCA9558) {
399 if (sc->arge_mac_unit == 0) {
400 reset_reg |= QCA955X_RESET_GE0_MDIO;
401 } else {
402 reset_reg |= QCA955X_RESET_GE1_MDIO;
403 }
404 }
405
406 if (ar71xx_soc == AR71XX_SOC_QCA9533 ||
407 ar71xx_soc == AR71XX_SOC_QCA9533_V2) {
408 if (sc->arge_mac_unit == 0) {
409 reset_reg |= QCA953X_RESET_GE0_MDIO;
410 } else {
411 reset_reg |= QCA953X_RESET_GE1_MDIO;
412 }
413 }
414
415 ar71xx_device_stop(reset_reg);
416 DELAY(100);
417 ar71xx_device_start(reset_reg);
418
419 /* Step 3. Reconfigure MAC block */
420 ARGE_WRITE(sc, AR71XX_MAC_CFG1,
421 MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
422 MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
423
424 reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
425 reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
426 ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
427
428 ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
429 }
430
431 /*
432 * These values map to the divisor values programmed into
433 * AR71XX_MAC_MII_CFG.
434 *
435 * The index of each value corresponds to the divisor section
436 * value in AR71XX_MAC_MII_CFG (ie, table[0] means '0' in
437 * AR71XX_MAC_MII_CFG, table[1] means '1', etc.)
438 */
439 static const uint32_t ar71xx_mdio_div_table[] = {
440 4, 4, 6, 8, 10, 14, 20, 28,
441 };
442
443 static const uint32_t ar7240_mdio_div_table[] = {
444 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
445 };
446
447 static const uint32_t ar933x_mdio_div_table[] = {
448 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
449 };
450
451 /*
452 * Lookup the divisor to use based on the given frequency.
453 *
454 * Returns the divisor to use, or -ve on error.
455 */
456 static int
arge_mdio_get_divider(struct arge_softc * sc,unsigned long mdio_clock)457 arge_mdio_get_divider(struct arge_softc *sc, unsigned long mdio_clock)
458 {
459 unsigned long ref_clock, t;
460 const uint32_t *table;
461 int ndivs;
462 int i;
463
464 /*
465 * This is the base MDIO frequency on the SoC.
466 * The dividers .. well, divide. Duh.
467 */
468 ref_clock = ar71xx_mdio_freq();
469
470 /*
471 * If either clock is undefined, just tell the
472 * caller to fall through to the defaults.
473 */
474 if (ref_clock == 0 || mdio_clock == 0)
475 return (-EINVAL);
476
477 /*
478 * Pick the correct table!
479 */
480 switch (ar71xx_soc) {
481 case AR71XX_SOC_AR9330:
482 case AR71XX_SOC_AR9331:
483 case AR71XX_SOC_AR9341:
484 case AR71XX_SOC_AR9342:
485 case AR71XX_SOC_AR9344:
486 case AR71XX_SOC_QCA9533:
487 case AR71XX_SOC_QCA9533_V2:
488 case AR71XX_SOC_QCA9556:
489 case AR71XX_SOC_QCA9558:
490 table = ar933x_mdio_div_table;
491 ndivs = nitems(ar933x_mdio_div_table);
492 break;
493
494 case AR71XX_SOC_AR7240:
495 case AR71XX_SOC_AR7241:
496 case AR71XX_SOC_AR7242:
497 table = ar7240_mdio_div_table;
498 ndivs = nitems(ar7240_mdio_div_table);
499 break;
500
501 default:
502 table = ar71xx_mdio_div_table;
503 ndivs = nitems(ar71xx_mdio_div_table);
504 }
505
506 /*
507 * Now, walk through the list and find the first divisor
508 * that falls under the target MDIO frequency.
509 *
510 * The divisors go up, but the corresponding frequencies
511 * are actually decreasing.
512 */
513 for (i = 0; i < ndivs; i++) {
514 t = ref_clock / table[i];
515 if (t <= mdio_clock) {
516 return (i);
517 }
518 }
519
520 ARGEDEBUG(sc, ARGE_DBG_RESET,
521 "No divider found; MDIO=%lu Hz; target=%lu Hz\n",
522 ref_clock, mdio_clock);
523 return (-ENOENT);
524 }
525
526 /*
527 * Fetch the MDIO bus clock rate.
528 *
529 * For now, the default is DIV_28 for everything
530 * bar AR934x, which will be DIV_58.
531 *
532 * It will definitely need updating to take into account
533 * the MDIO bus core clock rate and the target clock
534 * rate for the chip.
535 */
536 static uint32_t
arge_fetch_mdiobus_clock_rate(struct arge_softc * sc)537 arge_fetch_mdiobus_clock_rate(struct arge_softc *sc)
538 {
539 int mdio_freq, div;
540
541 /*
542 * Is the MDIO frequency defined? If so, find a divisor that
543 * makes reasonable sense. Don't overshoot the frequency.
544 */
545 if (resource_int_value(device_get_name(sc->arge_dev),
546 device_get_unit(sc->arge_dev),
547 "mdio_freq",
548 &mdio_freq) == 0) {
549 sc->arge_mdiofreq = mdio_freq;
550 div = arge_mdio_get_divider(sc, sc->arge_mdiofreq);
551 if (bootverbose)
552 device_printf(sc->arge_dev,
553 "%s: mdio ref freq=%llu Hz, target freq=%llu Hz,"
554 " divisor index=%d\n",
555 __func__,
556 (unsigned long long) ar71xx_mdio_freq(),
557 (unsigned long long) mdio_freq,
558 div);
559 if (div >= 0)
560 return (div);
561 }
562
563 /*
564 * Default value(s).
565 *
566 * XXX obviously these need .. fixing.
567 *
568 * From Linux/OpenWRT:
569 *
570 * + 7240? DIV_6
571 * + Builtin-switch port and not 934x? DIV_10
572 * + Not built-in switch port and 934x? DIV_58
573 * + .. else DIV_28.
574 */
575 switch (ar71xx_soc) {
576 case AR71XX_SOC_AR9341:
577 case AR71XX_SOC_AR9342:
578 case AR71XX_SOC_AR9344:
579 case AR71XX_SOC_QCA9533:
580 case AR71XX_SOC_QCA9533_V2:
581 case AR71XX_SOC_QCA9556:
582 case AR71XX_SOC_QCA9558:
583 return (MAC_MII_CFG_CLOCK_DIV_58);
584 break;
585 default:
586 return (MAC_MII_CFG_CLOCK_DIV_28);
587 }
588 }
589
590 static void
arge_reset_miibus(struct arge_softc * sc)591 arge_reset_miibus(struct arge_softc *sc)
592 {
593 uint32_t mdio_div;
594
595 mdio_div = arge_fetch_mdiobus_clock_rate(sc);
596
597 /*
598 * XXX AR934x and later; should we be also resetting the
599 * MDIO block(s) using the reset register block?
600 */
601
602 /* Reset MII bus; program in the default divisor */
603 ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | mdio_div);
604 DELAY(100);
605 ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, mdio_div);
606 DELAY(100);
607 }
608
609 static void
arge_fetch_pll_config(struct arge_softc * sc)610 arge_fetch_pll_config(struct arge_softc *sc)
611 {
612 long int val;
613
614 if (resource_long_value(device_get_name(sc->arge_dev),
615 device_get_unit(sc->arge_dev),
616 "pll_10", &val) == 0) {
617 sc->arge_pllcfg.pll_10 = val;
618 device_printf(sc->arge_dev, "%s: pll_10 = 0x%x\n",
619 __func__, (int) val);
620 }
621 if (resource_long_value(device_get_name(sc->arge_dev),
622 device_get_unit(sc->arge_dev),
623 "pll_100", &val) == 0) {
624 sc->arge_pllcfg.pll_100 = val;
625 device_printf(sc->arge_dev, "%s: pll_100 = 0x%x\n",
626 __func__, (int) val);
627 }
628 if (resource_long_value(device_get_name(sc->arge_dev),
629 device_get_unit(sc->arge_dev),
630 "pll_1000", &val) == 0) {
631 sc->arge_pllcfg.pll_1000 = val;
632 device_printf(sc->arge_dev, "%s: pll_1000 = 0x%x\n",
633 __func__, (int) val);
634 }
635 }
636
637 static int
arge_attach(device_t dev)638 arge_attach(device_t dev)
639 {
640 struct ifnet *ifp;
641 struct arge_softc *sc;
642 int error = 0, rid, i;
643 uint32_t hint;
644 long eeprom_mac_addr = 0;
645 int miicfg = 0;
646 int readascii = 0;
647 int local_mac = 0;
648 uint8_t local_macaddr[ETHER_ADDR_LEN];
649 char * local_macstr;
650 char devid_str[32];
651 int count;
652
653 sc = device_get_softc(dev);
654 sc->arge_dev = dev;
655 sc->arge_mac_unit = device_get_unit(dev);
656
657 /*
658 * See if there's a "board" MAC address hint available for
659 * this particular device.
660 *
661 * This is in the environment - it'd be nice to use the resource_*()
662 * routines, but at the moment the system is booting, the resource hints
663 * are set to the 'static' map so they're not pulling from kenv.
664 */
665 snprintf(devid_str, 32, "hint.%s.%d.macaddr",
666 device_get_name(dev),
667 device_get_unit(dev));
668 if ((local_macstr = kern_getenv(devid_str)) != NULL) {
669 uint32_t tmpmac[ETHER_ADDR_LEN];
670
671 /* Have a MAC address; should use it */
672 device_printf(dev, "Overriding MAC address from environment: '%s'\n",
673 local_macstr);
674
675 /* Extract out the MAC address */
676 /* XXX this should all be a generic method */
677 count = sscanf(local_macstr, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
678 &tmpmac[0], &tmpmac[1],
679 &tmpmac[2], &tmpmac[3],
680 &tmpmac[4], &tmpmac[5]);
681 if (count == 6) {
682 /* Valid! */
683 local_mac = 1;
684 for (i = 0; i < ETHER_ADDR_LEN; i++)
685 local_macaddr[i] = tmpmac[i];
686 }
687 /* Done! */
688 freeenv(local_macstr);
689 local_macstr = NULL;
690 }
691
692 /*
693 * Hardware workarounds.
694 */
695 switch (ar71xx_soc) {
696 case AR71XX_SOC_AR9330:
697 case AR71XX_SOC_AR9331:
698 case AR71XX_SOC_AR9341:
699 case AR71XX_SOC_AR9342:
700 case AR71XX_SOC_AR9344:
701 case AR71XX_SOC_QCA9533:
702 case AR71XX_SOC_QCA9533_V2:
703 case AR71XX_SOC_QCA9556:
704 case AR71XX_SOC_QCA9558:
705 /* Arbitrary alignment */
706 sc->arge_hw_flags |= ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE;
707 sc->arge_hw_flags |= ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE;
708 break;
709 default:
710 sc->arge_hw_flags |= ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE;
711 sc->arge_hw_flags |= ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE;
712 break;
713 }
714
715 /*
716 * Some units (eg the TP-Link WR-1043ND) do not have a convenient
717 * EEPROM location to read the ethernet MAC address from.
718 * OpenWRT simply snaffles it from a fixed location.
719 *
720 * Since multiple units seem to use this feature, include
721 * a method of setting the MAC address based on an flash location
722 * in CPU address space.
723 *
724 * Some vendors have decided to store the mac address as a literal
725 * string of 18 characters in xx:xx:xx:xx:xx:xx format instead of
726 * an array of numbers. Expose a hint to turn on this conversion
727 * feature via strtol()
728 */
729 if (local_mac == 0 && resource_long_value(device_get_name(dev),
730 device_get_unit(dev), "eeprommac", &eeprom_mac_addr) == 0) {
731 local_mac = 1;
732 int i;
733 const char *mac =
734 (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr);
735 device_printf(dev, "Overriding MAC from EEPROM\n");
736 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
737 "readascii", &readascii) == 0) {
738 device_printf(dev, "Vendor stores MAC in ASCII format\n");
739 for (i = 0; i < 6; i++) {
740 local_macaddr[i] = strtol(&(mac[i*3]), NULL, 16);
741 }
742 } else {
743 for (i = 0; i < 6; i++) {
744 local_macaddr[i] = mac[i];
745 }
746 }
747 }
748
749 KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)),
750 ("if_arge: Only MAC0 and MAC1 supported"));
751
752 /*
753 * Fetch the PLL configuration.
754 */
755 arge_fetch_pll_config(sc);
756
757 /*
758 * Get the MII configuration, if applicable.
759 */
760 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
761 "miimode", &miicfg) == 0) {
762 /* XXX bounds check? */
763 device_printf(dev, "%s: overriding MII mode to '%s'\n",
764 __func__, arge_miicfg_str[miicfg]);
765 sc->arge_miicfg = miicfg;
766 }
767
768 /*
769 * Get which PHY of 5 available we should use for this unit
770 */
771 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
772 "phymask", &sc->arge_phymask) != 0) {
773 /*
774 * Use port 4 (WAN) for GE0. For any other port use
775 * its PHY the same as its unit number
776 */
777 if (sc->arge_mac_unit == 0)
778 sc->arge_phymask = (1 << 4);
779 else
780 /* Use all phys up to 4 */
781 sc->arge_phymask = (1 << 4) - 1;
782
783 device_printf(dev, "No PHY specified, using mask %d\n", sc->arge_phymask);
784 }
785
786 /*
787 * Get default/hard-coded media & duplex mode.
788 */
789 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
790 "media", &hint) != 0)
791 hint = 0;
792
793 if (hint == 1000)
794 sc->arge_media_type = IFM_1000_T;
795 else if (hint == 100)
796 sc->arge_media_type = IFM_100_TX;
797 else if (hint == 10)
798 sc->arge_media_type = IFM_10_T;
799 else
800 sc->arge_media_type = 0;
801
802 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
803 "fduplex", &hint) != 0)
804 hint = 1;
805
806 if (hint)
807 sc->arge_duplex_mode = IFM_FDX;
808 else
809 sc->arge_duplex_mode = 0;
810
811 mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
812 MTX_DEF);
813 callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
814 TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
815
816 /* Map control/status registers. */
817 sc->arge_rid = 0;
818 sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
819 &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
820
821 if (sc->arge_res == NULL) {
822 device_printf(dev, "couldn't map memory\n");
823 error = ENXIO;
824 goto fail;
825 }
826
827 /* Allocate interrupts */
828 rid = 0;
829 sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
830 RF_SHAREABLE | RF_ACTIVE);
831
832 if (sc->arge_irq == NULL) {
833 device_printf(dev, "couldn't map interrupt\n");
834 error = ENXIO;
835 goto fail;
836 }
837
838 /* Allocate ifnet structure. */
839 ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
840
841 if (ifp == NULL) {
842 device_printf(dev, "couldn't allocate ifnet structure\n");
843 error = ENOSPC;
844 goto fail;
845 }
846
847 ifp->if_softc = sc;
848 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
849 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
850 ifp->if_ioctl = arge_ioctl;
851 ifp->if_start = arge_start;
852 ifp->if_init = arge_init;
853 sc->arge_if_flags = ifp->if_flags;
854
855 /* XXX: add real size */
856 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
857 ifp->if_snd.ifq_maxlen = ifqmaxlen;
858 IFQ_SET_READY(&ifp->if_snd);
859
860 /* Tell the upper layer(s) we support long frames. */
861 ifp->if_capabilities |= IFCAP_VLAN_MTU;
862
863 ifp->if_capenable = ifp->if_capabilities;
864 #ifdef DEVICE_POLLING
865 ifp->if_capabilities |= IFCAP_POLLING;
866 #endif
867
868 /* If there's a local mac defined, copy that in */
869 if (local_mac == 1) {
870 (void) ar71xx_mac_addr_init(sc->arge_eaddr,
871 local_macaddr, 0, 0);
872 } else {
873 /*
874 * No MAC address configured. Generate the random one.
875 */
876 if (bootverbose)
877 device_printf(dev,
878 "Generating random ethernet address.\n");
879 (void) ar71xx_mac_addr_random_init(sc->arge_eaddr);
880 }
881
882 if (arge_dma_alloc(sc) != 0) {
883 error = ENXIO;
884 goto fail;
885 }
886
887 /*
888 * Don't do this for the MDIO bus case - it's already done
889 * as part of the MDIO bus attachment.
890 *
891 * XXX TODO: if we don't do this, we don't ever release the MAC
892 * from reset and we can't use the port. Now, if we define ARGE_MDIO
893 * but we /don't/ define two MDIO busses, then we can't actually
894 * use both MACs.
895 */
896 #if !defined(ARGE_MDIO)
897 /* Initialize the MAC block */
898 arge_reset_mac(sc);
899 arge_reset_miibus(sc);
900 #endif
901
902 /* Configure MII mode, just for convienence */
903 if (sc->arge_miicfg != 0)
904 ar71xx_device_set_mii_if(sc->arge_mac_unit, sc->arge_miicfg);
905
906 /*
907 * Set all Ethernet address registers to the same initial values
908 * set all four addresses to 66-88-aa-cc-dd-ee
909 */
910 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, (sc->arge_eaddr[2] << 24)
911 | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8)
912 | sc->arge_eaddr[5]);
913 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
914 | sc->arge_eaddr[1]);
915
916 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
917 FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
918
919 /*
920 * SoC specific bits.
921 */
922 switch (ar71xx_soc) {
923 case AR71XX_SOC_AR7240:
924 case AR71XX_SOC_AR7241:
925 case AR71XX_SOC_AR7242:
926 case AR71XX_SOC_AR9330:
927 case AR71XX_SOC_AR9331:
928 case AR71XX_SOC_AR9341:
929 case AR71XX_SOC_AR9342:
930 case AR71XX_SOC_AR9344:
931 case AR71XX_SOC_QCA9533:
932 case AR71XX_SOC_QCA9533_V2:
933 case AR71XX_SOC_QCA9556:
934 case AR71XX_SOC_QCA9558:
935 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
936 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
937 break;
938 /* AR71xx, AR913x */
939 default:
940 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
941 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
942 }
943
944 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
945 FIFO_RX_FILTMATCH_DEFAULT);
946
947 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
948 FIFO_RX_FILTMASK_DEFAULT);
949
950 #if defined(ARGE_MDIO)
951 sc->arge_miiproxy = mii_attach_proxy(sc->arge_dev);
952 #endif
953
954 device_printf(sc->arge_dev, "finishing attachment, phymask %04x"
955 ", proxy %s \n", sc->arge_phymask, sc->arge_miiproxy == NULL ?
956 "null" : "set");
957 for (i = 0; i < ARGE_NPHY; i++) {
958 if (((1 << i) & sc->arge_phymask) != 0) {
959 error = mii_attach(sc->arge_miiproxy != NULL ?
960 sc->arge_miiproxy : sc->arge_dev,
961 &sc->arge_miibus, sc->arge_ifp,
962 arge_ifmedia_upd, arge_ifmedia_sts,
963 BMSR_DEFCAPMASK, i, MII_OFFSET_ANY, 0);
964 if (error != 0) {
965 device_printf(sc->arge_dev, "unable to attach"
966 " PHY %d: %d\n", i, error);
967 goto fail;
968 }
969 }
970 }
971
972 if (sc->arge_miibus == NULL) {
973 /* no PHY, so use hard-coded values */
974 ifmedia_init(&sc->arge_ifmedia, 0,
975 arge_multiphy_mediachange,
976 arge_multiphy_mediastatus);
977 ifmedia_add(&sc->arge_ifmedia,
978 IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode,
979 0, NULL);
980 ifmedia_set(&sc->arge_ifmedia,
981 IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode);
982 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
983 }
984
985 /* Call MI attach routine. */
986 ether_ifattach(sc->arge_ifp, sc->arge_eaddr);
987
988 /* Hook interrupt last to avoid having to lock softc */
989 error = bus_setup_intr(sc->arge_dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
990 arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
991
992 if (error) {
993 device_printf(sc->arge_dev, "couldn't set up irq\n");
994 ether_ifdetach(sc->arge_ifp);
995 goto fail;
996 }
997
998 /* setup sysctl variables */
999 arge_attach_sysctl(sc->arge_dev);
1000
1001 fail:
1002 if (error)
1003 arge_detach(dev);
1004
1005 return (error);
1006 }
1007
1008 static int
arge_detach(device_t dev)1009 arge_detach(device_t dev)
1010 {
1011 struct arge_softc *sc = device_get_softc(dev);
1012 struct ifnet *ifp = sc->arge_ifp;
1013
1014 KASSERT(mtx_initialized(&sc->arge_mtx),
1015 ("arge mutex not initialized"));
1016
1017 /* These should only be active if attach succeeded */
1018 if (device_is_attached(dev)) {
1019 ARGE_LOCK(sc);
1020 sc->arge_detach = 1;
1021 #ifdef DEVICE_POLLING
1022 if (ifp->if_capenable & IFCAP_POLLING)
1023 ether_poll_deregister(ifp);
1024 #endif
1025
1026 arge_stop(sc);
1027 ARGE_UNLOCK(sc);
1028 taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
1029 ether_ifdetach(ifp);
1030 }
1031
1032 if (sc->arge_miibus)
1033 device_delete_child(dev, sc->arge_miibus);
1034
1035 if (sc->arge_miiproxy)
1036 device_delete_child(dev, sc->arge_miiproxy);
1037
1038 bus_generic_detach(dev);
1039
1040 if (sc->arge_intrhand)
1041 bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
1042
1043 if (sc->arge_res)
1044 bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid,
1045 sc->arge_res);
1046
1047 if (ifp)
1048 if_free(ifp);
1049
1050 arge_dma_free(sc);
1051
1052 mtx_destroy(&sc->arge_mtx);
1053
1054 return (0);
1055
1056 }
1057
1058 static int
arge_suspend(device_t dev)1059 arge_suspend(device_t dev)
1060 {
1061
1062 panic("%s", __func__);
1063 return 0;
1064 }
1065
1066 static int
arge_resume(device_t dev)1067 arge_resume(device_t dev)
1068 {
1069
1070 panic("%s", __func__);
1071 return 0;
1072 }
1073
1074 static int
arge_shutdown(device_t dev)1075 arge_shutdown(device_t dev)
1076 {
1077 struct arge_softc *sc;
1078
1079 sc = device_get_softc(dev);
1080
1081 ARGE_LOCK(sc);
1082 arge_stop(sc);
1083 ARGE_UNLOCK(sc);
1084
1085 return (0);
1086 }
1087
1088 static void
arge_hinted_child(device_t bus,const char * dname,int dunit)1089 arge_hinted_child(device_t bus, const char *dname, int dunit)
1090 {
1091 BUS_ADD_CHILD(bus, 0, dname, dunit);
1092 device_printf(bus, "hinted child %s%d\n", dname, dunit);
1093 }
1094
1095 static int
arge_mdio_busy(struct arge_softc * sc)1096 arge_mdio_busy(struct arge_softc *sc)
1097 {
1098 int i,result;
1099
1100 for (i = 0; i < ARGE_MII_TIMEOUT; i++) {
1101 DELAY(5);
1102 ARGE_MDIO_BARRIER_READ(sc);
1103 result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR);
1104 if (! result)
1105 return (0);
1106 DELAY(5);
1107 }
1108 return (-1);
1109 }
1110
1111 static int
arge_miibus_readreg(device_t dev,int phy,int reg)1112 arge_miibus_readreg(device_t dev, int phy, int reg)
1113 {
1114 struct arge_softc * sc = device_get_softc(dev);
1115 int result;
1116 uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
1117 | (reg & MAC_MII_REG_MASK);
1118
1119 mtx_lock(&miibus_mtx);
1120 ARGE_MDIO_BARRIER_RW(sc);
1121 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
1122 ARGE_MDIO_BARRIER_WRITE(sc);
1123 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
1124 ARGE_MDIO_BARRIER_WRITE(sc);
1125 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
1126
1127 if (arge_mdio_busy(sc) != 0) {
1128 mtx_unlock(&miibus_mtx);
1129 ARGEDEBUG(sc, ARGE_DBG_ANY, "%s timedout\n", __func__);
1130 /* XXX: return ERRNO istead? */
1131 return (-1);
1132 }
1133
1134 ARGE_MDIO_BARRIER_READ(sc);
1135 result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
1136 ARGE_MDIO_BARRIER_RW(sc);
1137 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
1138 mtx_unlock(&miibus_mtx);
1139
1140 ARGEDEBUG(sc, ARGE_DBG_MII,
1141 "%s: phy=%d, reg=%02x, value[%08x]=%04x\n",
1142 __func__, phy, reg, addr, result);
1143
1144 return (result);
1145 }
1146
1147 static int
arge_miibus_writereg(device_t dev,int phy,int reg,int data)1148 arge_miibus_writereg(device_t dev, int phy, int reg, int data)
1149 {
1150 struct arge_softc * sc = device_get_softc(dev);
1151 uint32_t addr =
1152 (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
1153
1154 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
1155 phy, reg, data);
1156
1157 mtx_lock(&miibus_mtx);
1158 ARGE_MDIO_BARRIER_RW(sc);
1159 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
1160 ARGE_MDIO_BARRIER_WRITE(sc);
1161 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CONTROL, data);
1162 ARGE_MDIO_BARRIER_WRITE(sc);
1163
1164 if (arge_mdio_busy(sc) != 0) {
1165 mtx_unlock(&miibus_mtx);
1166 ARGEDEBUG(sc, ARGE_DBG_ANY, "%s timedout\n", __func__);
1167 /* XXX: return ERRNO istead? */
1168 return (-1);
1169 }
1170
1171 mtx_unlock(&miibus_mtx);
1172 return (0);
1173 }
1174
1175 static void
arge_miibus_statchg(device_t dev)1176 arge_miibus_statchg(device_t dev)
1177 {
1178 struct arge_softc *sc;
1179
1180 sc = device_get_softc(dev);
1181 taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
1182 }
1183
1184 static void
arge_link_task(void * arg,int pending)1185 arge_link_task(void *arg, int pending)
1186 {
1187 struct arge_softc *sc;
1188 sc = (struct arge_softc *)arg;
1189
1190 ARGE_LOCK(sc);
1191 arge_update_link_locked(sc);
1192 ARGE_UNLOCK(sc);
1193 }
1194
1195 static void
arge_update_link_locked(struct arge_softc * sc)1196 arge_update_link_locked(struct arge_softc *sc)
1197 {
1198 struct mii_data *mii;
1199 struct ifnet *ifp;
1200 uint32_t media, duplex;
1201
1202 mii = device_get_softc(sc->arge_miibus);
1203 ifp = sc->arge_ifp;
1204 if (mii == NULL || ifp == NULL ||
1205 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1206 return;
1207 }
1208
1209 /*
1210 * If we have a static media type configured, then
1211 * use that. Some PHY configurations (eg QCA955x -> AR8327)
1212 * use a static speed/duplex between the SoC and switch,
1213 * even though the front-facing PHY speed changes.
1214 */
1215 if (sc->arge_media_type != 0) {
1216 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: fixed; media=%d, duplex=%d\n",
1217 __func__,
1218 sc->arge_media_type,
1219 sc->arge_duplex_mode);
1220 if (mii->mii_media_status & IFM_ACTIVE) {
1221 sc->arge_link_status = 1;
1222 } else {
1223 sc->arge_link_status = 0;
1224 }
1225 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
1226 }
1227
1228 if (mii->mii_media_status & IFM_ACTIVE) {
1229
1230 media = IFM_SUBTYPE(mii->mii_media_active);
1231 if (media != IFM_NONE) {
1232 sc->arge_link_status = 1;
1233 duplex = mii->mii_media_active & IFM_GMASK;
1234 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: media=%d, duplex=%d\n",
1235 __func__,
1236 media,
1237 duplex);
1238 arge_set_pll(sc, media, duplex);
1239 }
1240 } else {
1241 sc->arge_link_status = 0;
1242 }
1243 }
1244
1245 static void
arge_set_pll(struct arge_softc * sc,int media,int duplex)1246 arge_set_pll(struct arge_softc *sc, int media, int duplex)
1247 {
1248 uint32_t cfg, ifcontrol, rx_filtmask;
1249 uint32_t fifo_tx, pll;
1250 int if_speed;
1251
1252 /*
1253 * XXX Verify - is this valid for all chips?
1254 * QCA955x (and likely some of the earlier chips!) define
1255 * this as nibble mode and byte mode, and those have to do
1256 * with the interface type (MII/SMII versus GMII/RGMII.)
1257 */
1258 ARGEDEBUG(sc, ARGE_DBG_PLL, "set_pll(%04x, %s)\n", media,
1259 duplex == IFM_FDX ? "full" : "half");
1260 cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
1261 cfg &= ~(MAC_CFG2_IFACE_MODE_1000
1262 | MAC_CFG2_IFACE_MODE_10_100
1263 | MAC_CFG2_FULL_DUPLEX);
1264
1265 if (duplex == IFM_FDX)
1266 cfg |= MAC_CFG2_FULL_DUPLEX;
1267
1268 ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
1269 ifcontrol &= ~MAC_IFCONTROL_SPEED;
1270 rx_filtmask =
1271 ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
1272 rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
1273
1274 switch(media) {
1275 case IFM_10_T:
1276 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1277 if_speed = 10;
1278 break;
1279 case IFM_100_TX:
1280 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1281 ifcontrol |= MAC_IFCONTROL_SPEED;
1282 if_speed = 100;
1283 break;
1284 case IFM_1000_T:
1285 case IFM_1000_SX:
1286 cfg |= MAC_CFG2_IFACE_MODE_1000;
1287 rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
1288 if_speed = 1000;
1289 break;
1290 default:
1291 if_speed = 100;
1292 device_printf(sc->arge_dev,
1293 "Unknown media %d\n", media);
1294 }
1295
1296 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: if_speed=%d\n", __func__, if_speed);
1297
1298 switch (ar71xx_soc) {
1299 case AR71XX_SOC_AR7240:
1300 case AR71XX_SOC_AR7241:
1301 case AR71XX_SOC_AR7242:
1302 case AR71XX_SOC_AR9330:
1303 case AR71XX_SOC_AR9331:
1304 case AR71XX_SOC_AR9341:
1305 case AR71XX_SOC_AR9342:
1306 case AR71XX_SOC_AR9344:
1307 case AR71XX_SOC_QCA9533:
1308 case AR71XX_SOC_QCA9533_V2:
1309 case AR71XX_SOC_QCA9556:
1310 case AR71XX_SOC_QCA9558:
1311 fifo_tx = 0x01f00140;
1312 break;
1313 case AR71XX_SOC_AR9130:
1314 case AR71XX_SOC_AR9132:
1315 fifo_tx = 0x00780fff;
1316 break;
1317 /* AR71xx */
1318 default:
1319 fifo_tx = 0x008001ff;
1320 }
1321
1322 ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
1323 ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
1324 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
1325 rx_filtmask);
1326 ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
1327
1328 /* fetch PLL registers */
1329 pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed);
1330 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: pll=0x%x\n", __func__, pll);
1331
1332 /* Override if required by platform data */
1333 if (if_speed == 10 && sc->arge_pllcfg.pll_10 != 0)
1334 pll = sc->arge_pllcfg.pll_10;
1335 else if (if_speed == 100 && sc->arge_pllcfg.pll_100 != 0)
1336 pll = sc->arge_pllcfg.pll_100;
1337 else if (if_speed == 1000 && sc->arge_pllcfg.pll_1000 != 0)
1338 pll = sc->arge_pllcfg.pll_1000;
1339 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: final pll=0x%x\n", __func__, pll);
1340
1341 /* XXX ensure pll != 0 */
1342 ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll);
1343
1344 /* set MII registers */
1345 /*
1346 * This was introduced to match what the Linux ag71xx ethernet
1347 * driver does. For the AR71xx case, it does set the port
1348 * MII speed. However, if this is done, non-gigabit speeds
1349 * are not at all reliable when speaking via RGMII through
1350 * 'bridge' PHY port that's pretending to be a local PHY.
1351 *
1352 * Until that gets root caused, and until an AR71xx + normal
1353 * PHY board is tested, leave this disabled.
1354 */
1355 #if 0
1356 ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed);
1357 #endif
1358 }
1359
1360
1361 static void
arge_reset_dma(struct arge_softc * sc)1362 arge_reset_dma(struct arge_softc *sc)
1363 {
1364
1365 ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: called\n", __func__);
1366
1367 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
1368 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
1369
1370 ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
1371 ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
1372
1373 /* Clear all possible RX interrupts */
1374 while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
1375 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
1376
1377 /*
1378 * Clear all possible TX interrupts
1379 */
1380 while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
1381 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
1382
1383 /*
1384 * Now Rx/Tx errors
1385 */
1386 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
1387 DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
1388 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
1389 DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
1390
1391 /*
1392 * Force a DDR flush so any pending data is properly
1393 * flushed to RAM before underlying buffers are freed.
1394 */
1395 arge_flush_ddr(sc);
1396 }
1397
1398 static void
arge_init(void * xsc)1399 arge_init(void *xsc)
1400 {
1401 struct arge_softc *sc = xsc;
1402
1403 ARGE_LOCK(sc);
1404 arge_init_locked(sc);
1405 ARGE_UNLOCK(sc);
1406 }
1407
1408 static void
arge_init_locked(struct arge_softc * sc)1409 arge_init_locked(struct arge_softc *sc)
1410 {
1411 struct ifnet *ifp = sc->arge_ifp;
1412 struct mii_data *mii;
1413
1414 ARGE_LOCK_ASSERT(sc);
1415
1416 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1417 return;
1418
1419 /* Init circular RX list. */
1420 if (arge_rx_ring_init(sc) != 0) {
1421 device_printf(sc->arge_dev,
1422 "initialization failed: no memory for rx buffers\n");
1423 arge_stop(sc);
1424 return;
1425 }
1426
1427 /* Init tx descriptors. */
1428 arge_tx_ring_init(sc);
1429
1430 arge_reset_dma(sc);
1431
1432 if (sc->arge_miibus) {
1433 mii = device_get_softc(sc->arge_miibus);
1434 mii_mediachg(mii);
1435 }
1436 else {
1437 /*
1438 * Sun always shines over multiPHY interface
1439 */
1440 sc->arge_link_status = 1;
1441 }
1442
1443 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1444 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1445
1446 if (sc->arge_miibus) {
1447 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
1448 arge_update_link_locked(sc);
1449 }
1450
1451 ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
1452 ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
1453
1454 /* Start listening */
1455 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
1456
1457 /* Enable interrupts */
1458 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1459 }
1460
1461 /*
1462 * Return whether the mbuf chain is correctly aligned
1463 * for the arge TX engine.
1464 *
1465 * All the MACs have a length requirement: any non-final
1466 * fragment (ie, descriptor with MORE bit set) needs to have
1467 * a length divisible by 4.
1468 *
1469 * The AR71xx, AR913x require the start address also be
1470 * DWORD aligned. The later MACs don't.
1471 */
1472 static int
arge_mbuf_chain_is_tx_aligned(struct arge_softc * sc,struct mbuf * m0)1473 arge_mbuf_chain_is_tx_aligned(struct arge_softc *sc, struct mbuf *m0)
1474 {
1475 struct mbuf *m;
1476
1477 for (m = m0; m != NULL; m = m->m_next) {
1478 /*
1479 * Only do this for chips that require it.
1480 */
1481 if ((sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE) &&
1482 (mtod(m, intptr_t) & 3) != 0) {
1483 sc->stats.tx_pkts_unaligned_start++;
1484 return 0;
1485 }
1486
1487 /*
1488 * All chips have this requirement for length.
1489 */
1490 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0)) {
1491 sc->stats.tx_pkts_unaligned_len++;
1492 return 0;
1493 }
1494 }
1495 return 1;
1496 }
1497
1498 /*
1499 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1500 * pointers to the fragment pointers.
1501 */
1502 static int
arge_encap(struct arge_softc * sc,struct mbuf ** m_head)1503 arge_encap(struct arge_softc *sc, struct mbuf **m_head)
1504 {
1505 struct arge_txdesc *txd;
1506 struct arge_desc *desc, *prev_desc;
1507 bus_dma_segment_t txsegs[ARGE_MAXFRAGS];
1508 int error, i, nsegs, prod, prev_prod;
1509 struct mbuf *m;
1510
1511 ARGE_LOCK_ASSERT(sc);
1512
1513 /*
1514 * Fix mbuf chain based on hardware alignment constraints.
1515 */
1516 m = *m_head;
1517 if (! arge_mbuf_chain_is_tx_aligned(sc, m)) {
1518 sc->stats.tx_pkts_unaligned++;
1519 m = m_defrag(*m_head, M_NOWAIT);
1520 if (m == NULL) {
1521 m_freem(*m_head);
1522 *m_head = NULL;
1523 return (ENOBUFS);
1524 }
1525 *m_head = m;
1526 } else
1527 sc->stats.tx_pkts_aligned++;
1528
1529 prod = sc->arge_cdata.arge_tx_prod;
1530 txd = &sc->arge_cdata.arge_txdesc[prod];
1531 error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag,
1532 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1533
1534 if (error == EFBIG) {
1535 panic("EFBIG");
1536 } else if (error != 0)
1537 return (error);
1538
1539 if (nsegs == 0) {
1540 m_freem(*m_head);
1541 *m_head = NULL;
1542 return (EIO);
1543 }
1544
1545 /* Check number of available descriptors. */
1546 if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 2)) {
1547 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1548 sc->stats.tx_pkts_nosegs++;
1549 return (ENOBUFS);
1550 }
1551
1552 txd->tx_m = *m_head;
1553 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1554 BUS_DMASYNC_PREWRITE);
1555
1556 /*
1557 * Make a list of descriptors for this packet. DMA controller will
1558 * walk through it while arge_link is not zero.
1559 *
1560 * Since we're in a endless circular buffer, ensure that
1561 * the first descriptor in a multi-descriptor ring is always
1562 * set to EMPTY, then un-do it when we're done populating.
1563 */
1564 prev_prod = prod;
1565 desc = prev_desc = NULL;
1566 for (i = 0; i < nsegs; i++) {
1567 uint32_t tmp;
1568
1569 desc = &sc->arge_rdata.arge_tx_ring[prod];
1570
1571 /*
1572 * Set DESC_EMPTY so the hardware (hopefully) stops at this
1573 * point. We don't want it to start transmitting descriptors
1574 * before we've finished fleshing this out.
1575 */
1576 tmp = ARGE_DMASIZE(txsegs[i].ds_len);
1577 if (i == 0)
1578 tmp |= ARGE_DESC_EMPTY;
1579 desc->packet_ctrl = tmp;
1580
1581 /* XXX Note: only relevant for older MACs; but check length! */
1582 if ((sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE) &&
1583 (txsegs[i].ds_addr & 3))
1584 panic("TX packet address unaligned\n");
1585
1586 desc->packet_addr = txsegs[i].ds_addr;
1587
1588 /* link with previous descriptor */
1589 if (prev_desc)
1590 prev_desc->packet_ctrl |= ARGE_DESC_MORE;
1591
1592 sc->arge_cdata.arge_tx_cnt++;
1593 prev_desc = desc;
1594 ARGE_INC(prod, ARGE_TX_RING_COUNT);
1595 }
1596
1597 /* Update producer index. */
1598 sc->arge_cdata.arge_tx_prod = prod;
1599
1600 /*
1601 * The descriptors are updated, so enable the first one.
1602 */
1603 desc = &sc->arge_rdata.arge_tx_ring[prev_prod];
1604 desc->packet_ctrl &= ~ ARGE_DESC_EMPTY;
1605
1606 /* Sync descriptors. */
1607 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1608 sc->arge_cdata.arge_tx_ring_map,
1609 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1610
1611 /* Flush writes */
1612 ARGE_BARRIER_WRITE(sc);
1613
1614 /* Start transmitting */
1615 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n",
1616 __func__);
1617 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
1618 return (0);
1619 }
1620
1621 static void
arge_start(struct ifnet * ifp)1622 arge_start(struct ifnet *ifp)
1623 {
1624 struct arge_softc *sc;
1625
1626 sc = ifp->if_softc;
1627
1628 ARGE_LOCK(sc);
1629 arge_start_locked(ifp);
1630 ARGE_UNLOCK(sc);
1631 }
1632
1633 static void
arge_start_locked(struct ifnet * ifp)1634 arge_start_locked(struct ifnet *ifp)
1635 {
1636 struct arge_softc *sc;
1637 struct mbuf *m_head;
1638 int enq = 0;
1639
1640 sc = ifp->if_softc;
1641
1642 ARGE_LOCK_ASSERT(sc);
1643
1644 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__);
1645
1646 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1647 IFF_DRV_RUNNING || sc->arge_link_status == 0 )
1648 return;
1649
1650 /*
1651 * Before we go any further, check whether we're already full.
1652 * The below check errors out immediately if the ring is full
1653 * and never gets a chance to set this flag. Although it's
1654 * likely never needed, this at least avoids an unexpected
1655 * situation.
1656 */
1657 if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) {
1658 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1659 ARGEDEBUG(sc, ARGE_DBG_ERR,
1660 "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n",
1661 __func__, sc->arge_cdata.arge_tx_cnt,
1662 ARGE_TX_RING_COUNT - 2);
1663 return;
1664 }
1665
1666 arge_flush_ddr(sc);
1667
1668 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1669 sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
1670 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1671 if (m_head == NULL)
1672 break;
1673
1674
1675 /*
1676 * Pack the data into the transmit ring.
1677 */
1678 if (arge_encap(sc, &m_head)) {
1679 if (m_head == NULL)
1680 break;
1681 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1682 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1683 break;
1684 }
1685
1686 enq++;
1687 /*
1688 * If there's a BPF listener, bounce a copy of this frame
1689 * to him.
1690 */
1691 ETHER_BPF_MTAP(ifp, m_head);
1692 }
1693 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n",
1694 __func__, enq);
1695 }
1696
1697 static void
arge_stop(struct arge_softc * sc)1698 arge_stop(struct arge_softc *sc)
1699 {
1700 struct ifnet *ifp;
1701
1702 ARGE_LOCK_ASSERT(sc);
1703
1704 ifp = sc->arge_ifp;
1705 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1706 if (sc->arge_miibus)
1707 callout_stop(&sc->arge_stat_callout);
1708
1709 /* mask out interrupts */
1710 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1711
1712 arge_reset_dma(sc);
1713
1714 /* Flush FIFO and free any existing mbufs */
1715 arge_flush_ddr(sc);
1716 arge_rx_ring_free(sc);
1717 arge_tx_ring_free(sc);
1718 }
1719
1720
1721 static int
arge_ioctl(struct ifnet * ifp,u_long command,caddr_t data)1722 arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1723 {
1724 struct arge_softc *sc = ifp->if_softc;
1725 struct ifreq *ifr = (struct ifreq *) data;
1726 struct mii_data *mii;
1727 int error;
1728 #ifdef DEVICE_POLLING
1729 int mask;
1730 #endif
1731
1732 switch (command) {
1733 case SIOCSIFFLAGS:
1734 ARGE_LOCK(sc);
1735 if ((ifp->if_flags & IFF_UP) != 0) {
1736 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1737 if (((ifp->if_flags ^ sc->arge_if_flags)
1738 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1739 /* XXX: handle promisc & multi flags */
1740 }
1741
1742 } else {
1743 if (!sc->arge_detach)
1744 arge_init_locked(sc);
1745 }
1746 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1747 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1748 arge_stop(sc);
1749 }
1750 sc->arge_if_flags = ifp->if_flags;
1751 ARGE_UNLOCK(sc);
1752 error = 0;
1753 break;
1754 case SIOCADDMULTI:
1755 case SIOCDELMULTI:
1756 /* XXX: implement SIOCDELMULTI */
1757 error = 0;
1758 break;
1759 case SIOCGIFMEDIA:
1760 case SIOCSIFMEDIA:
1761 if (sc->arge_miibus) {
1762 mii = device_get_softc(sc->arge_miibus);
1763 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1764 command);
1765 }
1766 else
1767 error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia,
1768 command);
1769 break;
1770 case SIOCSIFCAP:
1771 /* XXX: Check other capabilities */
1772 #ifdef DEVICE_POLLING
1773 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1774 if (mask & IFCAP_POLLING) {
1775 if (ifr->ifr_reqcap & IFCAP_POLLING) {
1776 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1777 error = ether_poll_register(arge_poll, ifp);
1778 if (error)
1779 return error;
1780 ARGE_LOCK(sc);
1781 ifp->if_capenable |= IFCAP_POLLING;
1782 ARGE_UNLOCK(sc);
1783 } else {
1784 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1785 error = ether_poll_deregister(ifp);
1786 ARGE_LOCK(sc);
1787 ifp->if_capenable &= ~IFCAP_POLLING;
1788 ARGE_UNLOCK(sc);
1789 }
1790 }
1791 error = 0;
1792 break;
1793 #endif
1794 default:
1795 error = ether_ioctl(ifp, command, data);
1796 break;
1797 }
1798
1799 return (error);
1800 }
1801
1802 /*
1803 * Set media options.
1804 */
1805 static int
arge_ifmedia_upd(struct ifnet * ifp)1806 arge_ifmedia_upd(struct ifnet *ifp)
1807 {
1808 struct arge_softc *sc;
1809 struct mii_data *mii;
1810 struct mii_softc *miisc;
1811 int error;
1812
1813 sc = ifp->if_softc;
1814 ARGE_LOCK(sc);
1815 mii = device_get_softc(sc->arge_miibus);
1816 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1817 PHY_RESET(miisc);
1818 error = mii_mediachg(mii);
1819 ARGE_UNLOCK(sc);
1820
1821 return (error);
1822 }
1823
1824 /*
1825 * Report current media status.
1826 */
1827 static void
arge_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1828 arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1829 {
1830 struct arge_softc *sc = ifp->if_softc;
1831 struct mii_data *mii;
1832
1833 mii = device_get_softc(sc->arge_miibus);
1834 ARGE_LOCK(sc);
1835 mii_pollstat(mii);
1836 ifmr->ifm_active = mii->mii_media_active;
1837 ifmr->ifm_status = mii->mii_media_status;
1838 ARGE_UNLOCK(sc);
1839 }
1840
1841 struct arge_dmamap_arg {
1842 bus_addr_t arge_busaddr;
1843 };
1844
1845 static void
arge_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)1846 arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1847 {
1848 struct arge_dmamap_arg *ctx;
1849
1850 if (error != 0)
1851 return;
1852 ctx = arg;
1853 ctx->arge_busaddr = segs[0].ds_addr;
1854 }
1855
1856 static int
arge_dma_alloc(struct arge_softc * sc)1857 arge_dma_alloc(struct arge_softc *sc)
1858 {
1859 struct arge_dmamap_arg ctx;
1860 struct arge_txdesc *txd;
1861 struct arge_rxdesc *rxd;
1862 int error, i;
1863 int arge_tx_align, arge_rx_align;
1864
1865 /* Assume 4 byte alignment by default */
1866 arge_tx_align = 4;
1867 arge_rx_align = 4;
1868
1869 if (sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE)
1870 arge_tx_align = 1;
1871 if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE)
1872 arge_rx_align = 1;
1873
1874 /* Create parent DMA tag. */
1875 error = bus_dma_tag_create(
1876 bus_get_dma_tag(sc->arge_dev), /* parent */
1877 1, 0, /* alignment, boundary */
1878 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1879 BUS_SPACE_MAXADDR, /* highaddr */
1880 NULL, NULL, /* filter, filterarg */
1881 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1882 0, /* nsegments */
1883 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1884 0, /* flags */
1885 NULL, NULL, /* lockfunc, lockarg */
1886 &sc->arge_cdata.arge_parent_tag);
1887 if (error != 0) {
1888 device_printf(sc->arge_dev,
1889 "failed to create parent DMA tag\n");
1890 goto fail;
1891 }
1892 /* Create tag for Tx ring. */
1893 error = bus_dma_tag_create(
1894 sc->arge_cdata.arge_parent_tag, /* parent */
1895 ARGE_RING_ALIGN, 0, /* alignment, boundary */
1896 BUS_SPACE_MAXADDR, /* lowaddr */
1897 BUS_SPACE_MAXADDR, /* highaddr */
1898 NULL, NULL, /* filter, filterarg */
1899 ARGE_TX_DMA_SIZE, /* maxsize */
1900 1, /* nsegments */
1901 ARGE_TX_DMA_SIZE, /* maxsegsize */
1902 0, /* flags */
1903 NULL, NULL, /* lockfunc, lockarg */
1904 &sc->arge_cdata.arge_tx_ring_tag);
1905 if (error != 0) {
1906 device_printf(sc->arge_dev,
1907 "failed to create Tx ring DMA tag\n");
1908 goto fail;
1909 }
1910
1911 /* Create tag for Rx ring. */
1912 error = bus_dma_tag_create(
1913 sc->arge_cdata.arge_parent_tag, /* parent */
1914 ARGE_RING_ALIGN, 0, /* alignment, boundary */
1915 BUS_SPACE_MAXADDR, /* lowaddr */
1916 BUS_SPACE_MAXADDR, /* highaddr */
1917 NULL, NULL, /* filter, filterarg */
1918 ARGE_RX_DMA_SIZE, /* maxsize */
1919 1, /* nsegments */
1920 ARGE_RX_DMA_SIZE, /* maxsegsize */
1921 0, /* flags */
1922 NULL, NULL, /* lockfunc, lockarg */
1923 &sc->arge_cdata.arge_rx_ring_tag);
1924 if (error != 0) {
1925 device_printf(sc->arge_dev,
1926 "failed to create Rx ring DMA tag\n");
1927 goto fail;
1928 }
1929
1930 /* Create tag for Tx buffers. */
1931 error = bus_dma_tag_create(
1932 sc->arge_cdata.arge_parent_tag, /* parent */
1933 arge_tx_align, 0, /* alignment, boundary */
1934 BUS_SPACE_MAXADDR, /* lowaddr */
1935 BUS_SPACE_MAXADDR, /* highaddr */
1936 NULL, NULL, /* filter, filterarg */
1937 MCLBYTES * ARGE_MAXFRAGS, /* maxsize */
1938 ARGE_MAXFRAGS, /* nsegments */
1939 MCLBYTES, /* maxsegsize */
1940 0, /* flags */
1941 NULL, NULL, /* lockfunc, lockarg */
1942 &sc->arge_cdata.arge_tx_tag);
1943 if (error != 0) {
1944 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
1945 goto fail;
1946 }
1947
1948 /* Create tag for Rx buffers. */
1949 error = bus_dma_tag_create(
1950 sc->arge_cdata.arge_parent_tag, /* parent */
1951 arge_rx_align, 0, /* alignment, boundary */
1952 BUS_SPACE_MAXADDR, /* lowaddr */
1953 BUS_SPACE_MAXADDR, /* highaddr */
1954 NULL, NULL, /* filter, filterarg */
1955 MCLBYTES, /* maxsize */
1956 ARGE_MAXFRAGS, /* nsegments */
1957 MCLBYTES, /* maxsegsize */
1958 0, /* flags */
1959 NULL, NULL, /* lockfunc, lockarg */
1960 &sc->arge_cdata.arge_rx_tag);
1961 if (error != 0) {
1962 device_printf(sc->arge_dev, "failed to create Rx DMA tag\n");
1963 goto fail;
1964 }
1965
1966 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1967 error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag,
1968 (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK |
1969 BUS_DMA_COHERENT | BUS_DMA_ZERO,
1970 &sc->arge_cdata.arge_tx_ring_map);
1971 if (error != 0) {
1972 device_printf(sc->arge_dev,
1973 "failed to allocate DMA'able memory for Tx ring\n");
1974 goto fail;
1975 }
1976
1977 ctx.arge_busaddr = 0;
1978 error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag,
1979 sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring,
1980 ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1981 if (error != 0 || ctx.arge_busaddr == 0) {
1982 device_printf(sc->arge_dev,
1983 "failed to load DMA'able memory for Tx ring\n");
1984 goto fail;
1985 }
1986 sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr;
1987
1988 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1989 error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag,
1990 (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK |
1991 BUS_DMA_COHERENT | BUS_DMA_ZERO,
1992 &sc->arge_cdata.arge_rx_ring_map);
1993 if (error != 0) {
1994 device_printf(sc->arge_dev,
1995 "failed to allocate DMA'able memory for Rx ring\n");
1996 goto fail;
1997 }
1998
1999 ctx.arge_busaddr = 0;
2000 error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag,
2001 sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring,
2002 ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
2003 if (error != 0 || ctx.arge_busaddr == 0) {
2004 device_printf(sc->arge_dev,
2005 "failed to load DMA'able memory for Rx ring\n");
2006 goto fail;
2007 }
2008 sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr;
2009
2010 /* Create DMA maps for Tx buffers. */
2011 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2012 txd = &sc->arge_cdata.arge_txdesc[i];
2013 txd->tx_m = NULL;
2014 txd->tx_dmamap = NULL;
2015 error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0,
2016 &txd->tx_dmamap);
2017 if (error != 0) {
2018 device_printf(sc->arge_dev,
2019 "failed to create Tx dmamap\n");
2020 goto fail;
2021 }
2022 }
2023 /* Create DMA maps for Rx buffers. */
2024 if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
2025 &sc->arge_cdata.arge_rx_sparemap)) != 0) {
2026 device_printf(sc->arge_dev,
2027 "failed to create spare Rx dmamap\n");
2028 goto fail;
2029 }
2030 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2031 rxd = &sc->arge_cdata.arge_rxdesc[i];
2032 rxd->rx_m = NULL;
2033 rxd->rx_dmamap = NULL;
2034 error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
2035 &rxd->rx_dmamap);
2036 if (error != 0) {
2037 device_printf(sc->arge_dev,
2038 "failed to create Rx dmamap\n");
2039 goto fail;
2040 }
2041 }
2042
2043 fail:
2044 return (error);
2045 }
2046
2047 static void
arge_dma_free(struct arge_softc * sc)2048 arge_dma_free(struct arge_softc *sc)
2049 {
2050 struct arge_txdesc *txd;
2051 struct arge_rxdesc *rxd;
2052 int i;
2053
2054 /* Tx ring. */
2055 if (sc->arge_cdata.arge_tx_ring_tag) {
2056 if (sc->arge_rdata.arge_tx_ring_paddr)
2057 bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag,
2058 sc->arge_cdata.arge_tx_ring_map);
2059 if (sc->arge_rdata.arge_tx_ring)
2060 bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag,
2061 sc->arge_rdata.arge_tx_ring,
2062 sc->arge_cdata.arge_tx_ring_map);
2063 sc->arge_rdata.arge_tx_ring = NULL;
2064 sc->arge_rdata.arge_tx_ring_paddr = 0;
2065 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag);
2066 sc->arge_cdata.arge_tx_ring_tag = NULL;
2067 }
2068 /* Rx ring. */
2069 if (sc->arge_cdata.arge_rx_ring_tag) {
2070 if (sc->arge_rdata.arge_rx_ring_paddr)
2071 bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag,
2072 sc->arge_cdata.arge_rx_ring_map);
2073 if (sc->arge_rdata.arge_rx_ring)
2074 bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag,
2075 sc->arge_rdata.arge_rx_ring,
2076 sc->arge_cdata.arge_rx_ring_map);
2077 sc->arge_rdata.arge_rx_ring = NULL;
2078 sc->arge_rdata.arge_rx_ring_paddr = 0;
2079 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag);
2080 sc->arge_cdata.arge_rx_ring_tag = NULL;
2081 }
2082 /* Tx buffers. */
2083 if (sc->arge_cdata.arge_tx_tag) {
2084 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2085 txd = &sc->arge_cdata.arge_txdesc[i];
2086 if (txd->tx_dmamap) {
2087 bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag,
2088 txd->tx_dmamap);
2089 txd->tx_dmamap = NULL;
2090 }
2091 }
2092 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag);
2093 sc->arge_cdata.arge_tx_tag = NULL;
2094 }
2095 /* Rx buffers. */
2096 if (sc->arge_cdata.arge_rx_tag) {
2097 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2098 rxd = &sc->arge_cdata.arge_rxdesc[i];
2099 if (rxd->rx_dmamap) {
2100 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
2101 rxd->rx_dmamap);
2102 rxd->rx_dmamap = NULL;
2103 }
2104 }
2105 if (sc->arge_cdata.arge_rx_sparemap) {
2106 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
2107 sc->arge_cdata.arge_rx_sparemap);
2108 sc->arge_cdata.arge_rx_sparemap = 0;
2109 }
2110 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag);
2111 sc->arge_cdata.arge_rx_tag = NULL;
2112 }
2113
2114 if (sc->arge_cdata.arge_parent_tag) {
2115 bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag);
2116 sc->arge_cdata.arge_parent_tag = NULL;
2117 }
2118 }
2119
2120 /*
2121 * Initialize the transmit descriptors.
2122 */
2123 static int
arge_tx_ring_init(struct arge_softc * sc)2124 arge_tx_ring_init(struct arge_softc *sc)
2125 {
2126 struct arge_ring_data *rd;
2127 struct arge_txdesc *txd;
2128 bus_addr_t addr;
2129 int i;
2130
2131 sc->arge_cdata.arge_tx_prod = 0;
2132 sc->arge_cdata.arge_tx_cons = 0;
2133 sc->arge_cdata.arge_tx_cnt = 0;
2134
2135 rd = &sc->arge_rdata;
2136 bzero(rd->arge_tx_ring, sizeof(*rd->arge_tx_ring));
2137 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2138 if (i == ARGE_TX_RING_COUNT - 1)
2139 addr = ARGE_TX_RING_ADDR(sc, 0);
2140 else
2141 addr = ARGE_TX_RING_ADDR(sc, i + 1);
2142 rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY;
2143 rd->arge_tx_ring[i].next_desc = addr;
2144 txd = &sc->arge_cdata.arge_txdesc[i];
2145 txd->tx_m = NULL;
2146 }
2147
2148 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2149 sc->arge_cdata.arge_tx_ring_map,
2150 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2151
2152 return (0);
2153 }
2154
2155 /*
2156 * Free the Tx ring, unload any pending dma transaction and free the mbuf.
2157 */
2158 static void
arge_tx_ring_free(struct arge_softc * sc)2159 arge_tx_ring_free(struct arge_softc *sc)
2160 {
2161 struct arge_txdesc *txd;
2162 int i;
2163
2164 /* Free the Tx buffers. */
2165 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2166 txd = &sc->arge_cdata.arge_txdesc[i];
2167 if (txd->tx_dmamap) {
2168 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag,
2169 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2170 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag,
2171 txd->tx_dmamap);
2172 }
2173 if (txd->tx_m)
2174 m_freem(txd->tx_m);
2175 txd->tx_m = NULL;
2176 }
2177 }
2178
2179 /*
2180 * Initialize the RX descriptors and allocate mbufs for them. Note that
2181 * we arrange the descriptors in a closed ring, so that the last descriptor
2182 * points back to the first.
2183 */
2184 static int
arge_rx_ring_init(struct arge_softc * sc)2185 arge_rx_ring_init(struct arge_softc *sc)
2186 {
2187 struct arge_ring_data *rd;
2188 struct arge_rxdesc *rxd;
2189 bus_addr_t addr;
2190 int i;
2191
2192 sc->arge_cdata.arge_rx_cons = 0;
2193
2194 rd = &sc->arge_rdata;
2195 bzero(rd->arge_rx_ring, sizeof(*rd->arge_rx_ring));
2196 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2197 rxd = &sc->arge_cdata.arge_rxdesc[i];
2198 if (rxd->rx_m != NULL) {
2199 device_printf(sc->arge_dev,
2200 "%s: ring[%d] rx_m wasn't free?\n",
2201 __func__,
2202 i);
2203 }
2204 rxd->rx_m = NULL;
2205 rxd->desc = &rd->arge_rx_ring[i];
2206 if (i == ARGE_RX_RING_COUNT - 1)
2207 addr = ARGE_RX_RING_ADDR(sc, 0);
2208 else
2209 addr = ARGE_RX_RING_ADDR(sc, i + 1);
2210 rd->arge_rx_ring[i].next_desc = addr;
2211 if (arge_newbuf(sc, i) != 0) {
2212 return (ENOBUFS);
2213 }
2214 }
2215
2216 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2217 sc->arge_cdata.arge_rx_ring_map,
2218 BUS_DMASYNC_PREWRITE);
2219
2220 return (0);
2221 }
2222
2223 /*
2224 * Free all the buffers in the RX ring.
2225 *
2226 * TODO: ensure that DMA is disabled and no pending DMA
2227 * is lurking in the FIFO.
2228 */
2229 static void
arge_rx_ring_free(struct arge_softc * sc)2230 arge_rx_ring_free(struct arge_softc *sc)
2231 {
2232 int i;
2233 struct arge_rxdesc *rxd;
2234
2235 ARGE_LOCK_ASSERT(sc);
2236
2237 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2238 rxd = &sc->arge_cdata.arge_rxdesc[i];
2239 /* Unmap the mbuf */
2240 if (rxd->rx_m != NULL) {
2241 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag,
2242 rxd->rx_dmamap);
2243 m_free(rxd->rx_m);
2244 rxd->rx_m = NULL;
2245 }
2246 }
2247 }
2248
2249 /*
2250 * Initialize an RX descriptor and attach an MBUF cluster.
2251 */
2252 static int
arge_newbuf(struct arge_softc * sc,int idx)2253 arge_newbuf(struct arge_softc *sc, int idx)
2254 {
2255 struct arge_desc *desc;
2256 struct arge_rxdesc *rxd;
2257 struct mbuf *m;
2258 bus_dma_segment_t segs[1];
2259 bus_dmamap_t map;
2260 int nsegs;
2261
2262 /* XXX TODO: should just allocate an explicit 2KiB buffer */
2263 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2264 if (m == NULL)
2265 return (ENOBUFS);
2266 m->m_len = m->m_pkthdr.len = MCLBYTES;
2267
2268 /*
2269 * Add extra space to "adjust" (copy) the packet back to be aligned
2270 * for purposes of IPv4/IPv6 header contents.
2271 */
2272 if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE)
2273 m_adj(m, sizeof(uint64_t));
2274 /*
2275 * If it's a 1-byte aligned buffer, then just offset it two bytes
2276 * and that will give us a hopefully correctly DWORD aligned
2277 * L3 payload - and we won't have to undo it afterwards.
2278 */
2279 else if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE)
2280 m_adj(m, sizeof(uint16_t));
2281
2282 if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
2283 sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2284 m_freem(m);
2285 return (ENOBUFS);
2286 }
2287 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2288
2289 rxd = &sc->arge_cdata.arge_rxdesc[idx];
2290 if (rxd->rx_m != NULL) {
2291 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
2292 }
2293 map = rxd->rx_dmamap;
2294 rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
2295 sc->arge_cdata.arge_rx_sparemap = map;
2296 rxd->rx_m = m;
2297 desc = rxd->desc;
2298 if ((sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE) &&
2299 segs[0].ds_addr & 3)
2300 panic("RX packet address unaligned");
2301 desc->packet_addr = segs[0].ds_addr;
2302 desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
2303
2304 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2305 sc->arge_cdata.arge_rx_ring_map,
2306 BUS_DMASYNC_PREWRITE);
2307
2308 return (0);
2309 }
2310
2311 /*
2312 * Move the data backwards 16 bits to (hopefully!) ensure the
2313 * IPv4/IPv6 payload is aligned.
2314 *
2315 * This is required for earlier hardware where the RX path
2316 * requires DWORD aligned buffers.
2317 */
2318 static __inline void
arge_fixup_rx(struct mbuf * m)2319 arge_fixup_rx(struct mbuf *m)
2320 {
2321 int i;
2322 uint16_t *src, *dst;
2323
2324 src = mtod(m, uint16_t *);
2325 dst = src - 1;
2326
2327 for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
2328 *dst++ = *src++;
2329 }
2330
2331 if (m->m_len % sizeof(uint16_t))
2332 *(uint8_t *)dst = *(uint8_t *)src;
2333
2334 m->m_data -= ETHER_ALIGN;
2335 }
2336
2337 #ifdef DEVICE_POLLING
2338 static int
arge_poll(struct ifnet * ifp,enum poll_cmd cmd,int count)2339 arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2340 {
2341 struct arge_softc *sc = ifp->if_softc;
2342 int rx_npkts = 0;
2343
2344 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2345 ARGE_LOCK(sc);
2346 arge_tx_locked(sc);
2347 rx_npkts = arge_rx_locked(sc);
2348 ARGE_UNLOCK(sc);
2349 }
2350
2351 return (rx_npkts);
2352 }
2353 #endif /* DEVICE_POLLING */
2354
2355
2356 static void
arge_tx_locked(struct arge_softc * sc)2357 arge_tx_locked(struct arge_softc *sc)
2358 {
2359 struct arge_txdesc *txd;
2360 struct arge_desc *cur_tx;
2361 struct ifnet *ifp;
2362 uint32_t ctrl;
2363 int cons, prod;
2364
2365 ARGE_LOCK_ASSERT(sc);
2366
2367 cons = sc->arge_cdata.arge_tx_cons;
2368 prod = sc->arge_cdata.arge_tx_prod;
2369
2370 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons,
2371 prod);
2372
2373 if (cons == prod)
2374 return;
2375
2376 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2377 sc->arge_cdata.arge_tx_ring_map,
2378 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2379
2380 ifp = sc->arge_ifp;
2381 /*
2382 * Go through our tx list and free mbufs for those
2383 * frames that have been transmitted.
2384 */
2385 for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) {
2386 cur_tx = &sc->arge_rdata.arge_tx_ring[cons];
2387 ctrl = cur_tx->packet_ctrl;
2388 /* Check if descriptor has "finished" flag */
2389 if ((ctrl & ARGE_DESC_EMPTY) == 0)
2390 break;
2391
2392 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
2393
2394 sc->arge_cdata.arge_tx_cnt--;
2395 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2396
2397 txd = &sc->arge_cdata.arge_txdesc[cons];
2398
2399 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2400
2401 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
2402 BUS_DMASYNC_POSTWRITE);
2403 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
2404
2405 /* Free only if it's first descriptor in list */
2406 if (txd->tx_m)
2407 m_freem(txd->tx_m);
2408 txd->tx_m = NULL;
2409
2410 /* reset descriptor */
2411 cur_tx->packet_addr = 0;
2412 }
2413
2414 sc->arge_cdata.arge_tx_cons = cons;
2415
2416 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2417 sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
2418 }
2419
2420
2421 static int
arge_rx_locked(struct arge_softc * sc)2422 arge_rx_locked(struct arge_softc *sc)
2423 {
2424 struct arge_rxdesc *rxd;
2425 struct ifnet *ifp = sc->arge_ifp;
2426 int cons, prog, packet_len, i;
2427 struct arge_desc *cur_rx;
2428 struct mbuf *m;
2429 int rx_npkts = 0;
2430
2431 ARGE_LOCK_ASSERT(sc);
2432
2433 cons = sc->arge_cdata.arge_rx_cons;
2434
2435 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2436 sc->arge_cdata.arge_rx_ring_map,
2437 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2438
2439 for (prog = 0; prog < ARGE_RX_RING_COUNT;
2440 ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
2441 cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
2442 rxd = &sc->arge_cdata.arge_rxdesc[cons];
2443 m = rxd->rx_m;
2444
2445 if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0)
2446 break;
2447
2448 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
2449
2450 prog++;
2451
2452 packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl);
2453 bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap,
2454 BUS_DMASYNC_POSTREAD);
2455 m = rxd->rx_m;
2456
2457 /*
2458 * If the MAC requires 4 byte alignment then the RX setup
2459 * routine will have pre-offset things; so un-offset it here.
2460 */
2461 if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE)
2462 arge_fixup_rx(m);
2463
2464 m->m_pkthdr.rcvif = ifp;
2465 /* Skip 4 bytes of CRC */
2466 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
2467 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2468 rx_npkts++;
2469
2470 ARGE_UNLOCK(sc);
2471 (*ifp->if_input)(ifp, m);
2472 ARGE_LOCK(sc);
2473 cur_rx->packet_addr = 0;
2474 }
2475
2476 if (prog > 0) {
2477
2478 i = sc->arge_cdata.arge_rx_cons;
2479 for (; prog > 0 ; prog--) {
2480 if (arge_newbuf(sc, i) != 0) {
2481 device_printf(sc->arge_dev,
2482 "Failed to allocate buffer\n");
2483 break;
2484 }
2485 ARGE_INC(i, ARGE_RX_RING_COUNT);
2486 }
2487
2488 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2489 sc->arge_cdata.arge_rx_ring_map,
2490 BUS_DMASYNC_PREWRITE);
2491
2492 sc->arge_cdata.arge_rx_cons = cons;
2493 }
2494
2495 return (rx_npkts);
2496 }
2497
2498 static int
arge_intr_filter(void * arg)2499 arge_intr_filter(void *arg)
2500 {
2501 struct arge_softc *sc = arg;
2502 uint32_t status, ints;
2503
2504 status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2505 ints = ARGE_READ(sc, AR71XX_DMA_INTR);
2506
2507 ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints,
2508 "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2509 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2510 ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
2511 "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2512 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2513
2514 if (status & DMA_INTR_ALL) {
2515 sc->arge_intr_status |= status;
2516 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
2517 sc->stats.intr_ok++;
2518 return (FILTER_SCHEDULE_THREAD);
2519 }
2520
2521 sc->arge_intr_status = 0;
2522 sc->stats.intr_stray++;
2523 return (FILTER_STRAY);
2524 }
2525
2526 static void
arge_intr(void * arg)2527 arge_intr(void *arg)
2528 {
2529 struct arge_softc *sc = arg;
2530 uint32_t status;
2531 struct ifnet *ifp = sc->arge_ifp;
2532 #ifdef ARGE_DEBUG
2533 int i;
2534 #endif
2535
2536 status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2537 status |= sc->arge_intr_status;
2538
2539 ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
2540 "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
2541 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2542
2543 /*
2544 * Is it our interrupt at all?
2545 */
2546 if (status == 0) {
2547 sc->stats.intr_stray2++;
2548 return;
2549 }
2550
2551 #ifdef ARGE_DEBUG
2552 for (i = 0; i < 32; i++) {
2553 if (status & (1U << i)) {
2554 sc->intr_stats.count[i]++;
2555 }
2556 }
2557 #endif
2558
2559 if (status & DMA_INTR_RX_BUS_ERROR) {
2560 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
2561 device_printf(sc->arge_dev, "RX bus error");
2562 return;
2563 }
2564
2565 if (status & DMA_INTR_TX_BUS_ERROR) {
2566 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
2567 device_printf(sc->arge_dev, "TX bus error");
2568 return;
2569 }
2570
2571 ARGE_LOCK(sc);
2572 arge_flush_ddr(sc);
2573
2574 if (status & DMA_INTR_RX_PKT_RCVD)
2575 arge_rx_locked(sc);
2576
2577 /*
2578 * RX overrun disables the receiver.
2579 * Clear indication and re-enable rx.
2580 */
2581 if ( status & DMA_INTR_RX_OVERFLOW) {
2582 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
2583 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
2584 sc->stats.rx_overflow++;
2585 }
2586
2587 if (status & DMA_INTR_TX_PKT_SENT)
2588 arge_tx_locked(sc);
2589 /*
2590 * Underrun turns off TX. Clear underrun indication.
2591 * If there's anything left in the ring, reactivate the tx.
2592 */
2593 if (status & DMA_INTR_TX_UNDERRUN) {
2594 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
2595 sc->stats.tx_underflow++;
2596 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n",
2597 __func__, sc->arge_cdata.arge_tx_cnt);
2598 if (sc->arge_cdata.arge_tx_cnt > 0 ) {
2599 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
2600 DMA_TX_CONTROL_EN);
2601 }
2602 }
2603
2604 /*
2605 * If we've finished TXing and there's space for more packets
2606 * to be queued for TX, do so. Otherwise we may end up in a
2607 * situation where the interface send queue was filled
2608 * whilst the hardware queue was full, then the hardware
2609 * queue was drained by the interface send queue wasn't,
2610 * and thus if_start() is never called to kick-start
2611 * the send process (and all subsequent packets are simply
2612 * discarded.
2613 *
2614 * XXX TODO: make sure that the hardware deals nicely
2615 * with the possibility of the queue being enabled above
2616 * after a TX underrun, then having the hardware queue added
2617 * to below.
2618 */
2619 if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) &&
2620 (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
2621 if (!IFQ_IS_EMPTY(&ifp->if_snd))
2622 arge_start_locked(ifp);
2623 }
2624
2625 /*
2626 * We handled all bits, clear status
2627 */
2628 sc->arge_intr_status = 0;
2629 ARGE_UNLOCK(sc);
2630 /*
2631 * re-enable all interrupts
2632 */
2633 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
2634 }
2635
2636
2637 static void
arge_tick(void * xsc)2638 arge_tick(void *xsc)
2639 {
2640 struct arge_softc *sc = xsc;
2641 struct mii_data *mii;
2642
2643 ARGE_LOCK_ASSERT(sc);
2644
2645 if (sc->arge_miibus) {
2646 mii = device_get_softc(sc->arge_miibus);
2647 mii_tick(mii);
2648 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
2649 }
2650 }
2651
2652 int
arge_multiphy_mediachange(struct ifnet * ifp)2653 arge_multiphy_mediachange(struct ifnet *ifp)
2654 {
2655 struct arge_softc *sc = ifp->if_softc;
2656 struct ifmedia *ifm = &sc->arge_ifmedia;
2657 struct ifmedia_entry *ife = ifm->ifm_cur;
2658
2659 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2660 return (EINVAL);
2661
2662 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
2663 device_printf(sc->arge_dev,
2664 "AUTO is not supported for multiphy MAC");
2665 return (EINVAL);
2666 }
2667
2668 /*
2669 * Ignore everything
2670 */
2671 return (0);
2672 }
2673
2674 void
arge_multiphy_mediastatus(struct ifnet * ifp,struct ifmediareq * ifmr)2675 arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2676 {
2677 struct arge_softc *sc = ifp->if_softc;
2678
2679 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
2680 ifmr->ifm_active = IFM_ETHER | sc->arge_media_type |
2681 sc->arge_duplex_mode;
2682 }
2683
2684 #if defined(ARGE_MDIO)
2685 static int
argemdio_probe(device_t dev)2686 argemdio_probe(device_t dev)
2687 {
2688 device_set_desc(dev, "Atheros AR71xx built-in ethernet interface, MDIO controller");
2689 return (0);
2690 }
2691
2692 static int
argemdio_attach(device_t dev)2693 argemdio_attach(device_t dev)
2694 {
2695 struct arge_softc *sc;
2696 int error = 0;
2697 #ifdef ARGE_DEBUG
2698 struct sysctl_ctx_list *ctx;
2699 struct sysctl_oid *tree;
2700 #endif
2701 sc = device_get_softc(dev);
2702 sc->arge_dev = dev;
2703 sc->arge_mac_unit = device_get_unit(dev);
2704 sc->arge_rid = 0;
2705 sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2706 &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
2707 if (sc->arge_res == NULL) {
2708 device_printf(dev, "couldn't map memory\n");
2709 error = ENXIO;
2710 goto fail;
2711 }
2712
2713 #ifdef ARGE_DEBUG
2714 ctx = device_get_sysctl_ctx(dev);
2715 tree = device_get_sysctl_tree(dev);
2716 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2717 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
2718 "argemdio interface debugging flags");
2719 #endif
2720
2721 /* Reset MAC - required for AR71xx MDIO to successfully occur */
2722 arge_reset_mac(sc);
2723 /* Reset MII bus */
2724 arge_reset_miibus(sc);
2725
2726 bus_generic_probe(dev);
2727 bus_enumerate_hinted_children(dev);
2728 error = bus_generic_attach(dev);
2729 fail:
2730 return (error);
2731 }
2732
2733 static int
argemdio_detach(device_t dev)2734 argemdio_detach(device_t dev)
2735 {
2736 return (0);
2737 }
2738
2739 #endif
2740