1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/thermal/thermal.h> 47 48#include <dt-bindings/clock/sun6i-a31-ccu.h> 49#include <dt-bindings/reset/sun6i-a31-ccu.h> 50 51/ { 52 interrupt-parent = <&gic>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 aliases { 57 ethernet0 = &gmac; 58 }; 59 60 chosen { 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges; 64 65 simplefb_hdmi: framebuffer-lcd0-hdmi { 66 compatible = "allwinner,simple-framebuffer", 67 "simple-framebuffer"; 68 allwinner,pipeline = "de_be0-lcd0-hdmi"; 69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, 70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, 71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, 72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; 73 status = "disabled"; 74 }; 75 76 simplefb_lcd: framebuffer-lcd0 { 77 compatible = "allwinner,simple-framebuffer", 78 "simple-framebuffer"; 79 allwinner,pipeline = "de_be0-lcd0"; 80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, 81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, 82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; 83 status = "disabled"; 84 }; 85 }; 86 87 timer { 88 compatible = "arm,armv7-timer"; 89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 93 clock-frequency = <24000000>; 94 arm,cpu-registers-not-fw-configured; 95 }; 96 97 cpus { 98 enable-method = "allwinner,sun6i-a31"; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 cpu0: cpu@0 { 103 compatible = "arm,cortex-a7"; 104 device_type = "cpu"; 105 reg = <0>; 106 clocks = <&ccu CLK_CPU>; 107 clock-latency = <244144>; /* 8 32k periods */ 108 operating-points = < 109 /* kHz uV */ 110 1008000 1200000 111 864000 1200000 112 720000 1100000 113 480000 1000000 114 >; 115 #cooling-cells = <2>; 116 }; 117 118 cpu1: cpu@1 { 119 compatible = "arm,cortex-a7"; 120 device_type = "cpu"; 121 reg = <1>; 122 clocks = <&ccu CLK_CPU>; 123 clock-latency = <244144>; /* 8 32k periods */ 124 operating-points = < 125 /* kHz uV */ 126 1008000 1200000 127 864000 1200000 128 720000 1100000 129 480000 1000000 130 >; 131 #cooling-cells = <2>; 132 }; 133 134 cpu2: cpu@2 { 135 compatible = "arm,cortex-a7"; 136 device_type = "cpu"; 137 reg = <2>; 138 clocks = <&ccu CLK_CPU>; 139 clock-latency = <244144>; /* 8 32k periods */ 140 operating-points = < 141 /* kHz uV */ 142 1008000 1200000 143 864000 1200000 144 720000 1100000 145 480000 1000000 146 >; 147 #cooling-cells = <2>; 148 }; 149 150 cpu3: cpu@3 { 151 compatible = "arm,cortex-a7"; 152 device_type = "cpu"; 153 reg = <3>; 154 clocks = <&ccu CLK_CPU>; 155 clock-latency = <244144>; /* 8 32k periods */ 156 operating-points = < 157 /* kHz uV */ 158 1008000 1200000 159 864000 1200000 160 720000 1100000 161 480000 1000000 162 >; 163 #cooling-cells = <2>; 164 }; 165 }; 166 167 thermal-zones { 168 cpu_thermal { 169 /* milliseconds */ 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 thermal-sensors = <&rtp>; 173 174 cooling-maps { 175 map0 { 176 trip = <&cpu_alert0>; 177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 178 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 179 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 180 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 181 }; 182 }; 183 184 trips { 185 cpu_alert0: cpu_alert0 { 186 /* milliCelsius */ 187 temperature = <70000>; 188 hysteresis = <2000>; 189 type = "passive"; 190 }; 191 192 cpu_crit: cpu_crit { 193 /* milliCelsius */ 194 temperature = <100000>; 195 hysteresis = <2000>; 196 type = "critical"; 197 }; 198 }; 199 }; 200 }; 201 202 pmu { 203 compatible = "arm,cortex-a7-pmu"; 204 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 208 }; 209 210 clocks { 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges; 214 215 osc24M: clk-24M { 216 #clock-cells = <0>; 217 compatible = "fixed-clock"; 218 clock-frequency = <24000000>; 219 clock-accuracy = <50000>; 220 clock-output-names = "osc24M"; 221 }; 222 223 osc32k: clk-32k { 224 #clock-cells = <0>; 225 compatible = "fixed-clock"; 226 clock-frequency = <32768>; 227 clock-accuracy = <50000>; 228 clock-output-names = "ext_osc32k"; 229 }; 230 231 /* 232 * The following two are dummy clocks, placeholders 233 * used in the gmac_tx clock. The gmac driver will 234 * choose one parent depending on the PHY interface 235 * mode, using clk_set_rate auto-reparenting. 236 * 237 * The actual TX clock rate is not controlled by the 238 * gmac_tx clock. 239 */ 240 mii_phy_tx_clk: clk-mii-phy-tx { 241 #clock-cells = <0>; 242 compatible = "fixed-clock"; 243 clock-frequency = <25000000>; 244 clock-output-names = "mii_phy_tx"; 245 }; 246 247 gmac_int_tx_clk: clk-gmac-int-tx { 248 #clock-cells = <0>; 249 compatible = "fixed-clock"; 250 clock-frequency = <125000000>; 251 clock-output-names = "gmac_int_tx"; 252 }; 253 254 gmac_tx_clk: clk@1c200d0 { 255 #clock-cells = <0>; 256 compatible = "allwinner,sun7i-a20-gmac-clk"; 257 reg = <0x01c200d0 0x4>; 258 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 259 clock-output-names = "gmac_tx"; 260 }; 261 }; 262 263 de: display-engine { 264 compatible = "allwinner,sun6i-a31-display-engine"; 265 allwinner,pipelines = <&fe0>, <&fe1>; 266 status = "disabled"; 267 }; 268 269 soc { 270 compatible = "simple-bus"; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 ranges; 274 275 dma: dma-controller@1c02000 { 276 compatible = "allwinner,sun6i-a31-dma"; 277 reg = <0x01c02000 0x1000>; 278 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&ccu CLK_AHB1_DMA>; 280 resets = <&ccu RST_AHB1_DMA>; 281 #dma-cells = <1>; 282 }; 283 284 tcon0: lcd-controller@1c0c000 { 285 compatible = "allwinner,sun6i-a31-tcon"; 286 reg = <0x01c0c000 0x1000>; 287 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 288 dmas = <&dma 11>; 289 resets = <&ccu RST_AHB1_LCD0>, 290 <&ccu RST_AHB1_LVDS>; 291 reset-names = "lcd", 292 "lvds"; 293 clocks = <&ccu CLK_AHB1_LCD0>, 294 <&ccu CLK_LCD0_CH0>, 295 <&ccu CLK_LCD0_CH1>, 296 <&ccu 15>; 297 clock-names = "ahb", 298 "tcon-ch0", 299 "tcon-ch1", 300 "lvds-alt"; 301 clock-output-names = "tcon0-pixel-clock"; 302 #clock-cells = <0>; 303 304 ports { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 308 tcon0_in: port@0 { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 reg = <0>; 312 313 tcon0_in_drc0: endpoint@0 { 314 reg = <0>; 315 remote-endpoint = <&drc0_out_tcon0>; 316 }; 317 318 tcon0_in_drc1: endpoint@1 { 319 reg = <1>; 320 remote-endpoint = <&drc1_out_tcon0>; 321 }; 322 }; 323 324 tcon0_out: port@1 { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 reg = <1>; 328 329 tcon0_out_hdmi: endpoint@1 { 330 reg = <1>; 331 remote-endpoint = <&hdmi_in_tcon0>; 332 allwinner,tcon-channel = <1>; 333 }; 334 }; 335 }; 336 }; 337 338 tcon1: lcd-controller@1c0d000 { 339 compatible = "allwinner,sun6i-a31-tcon"; 340 reg = <0x01c0d000 0x1000>; 341 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 342 dmas = <&dma 12>; 343 resets = <&ccu RST_AHB1_LCD1>, 344 <&ccu RST_AHB1_LVDS>; 345 reset-names = "lcd", "lvds"; 346 clocks = <&ccu CLK_AHB1_LCD1>, 347 <&ccu CLK_LCD1_CH0>, 348 <&ccu CLK_LCD1_CH1>, 349 <&ccu 15>; 350 clock-names = "ahb", 351 "tcon-ch0", 352 "tcon-ch1", 353 "lvds-alt"; 354 clock-output-names = "tcon1-pixel-clock"; 355 #clock-cells = <0>; 356 357 ports { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 361 tcon1_in: port@0 { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 reg = <0>; 365 366 tcon1_in_drc0: endpoint@0 { 367 reg = <0>; 368 remote-endpoint = <&drc0_out_tcon1>; 369 }; 370 371 tcon1_in_drc1: endpoint@1 { 372 reg = <1>; 373 remote-endpoint = <&drc1_out_tcon1>; 374 }; 375 }; 376 377 tcon1_out: port@1 { 378 #address-cells = <1>; 379 #size-cells = <0>; 380 reg = <1>; 381 382 tcon1_out_hdmi: endpoint@1 { 383 reg = <1>; 384 remote-endpoint = <&hdmi_in_tcon1>; 385 allwinner,tcon-channel = <1>; 386 }; 387 }; 388 }; 389 }; 390 391 mmc0: mmc@1c0f000 { 392 compatible = "allwinner,sun7i-a20-mmc"; 393 reg = <0x01c0f000 0x1000>; 394 clocks = <&ccu CLK_AHB1_MMC0>, 395 <&ccu CLK_MMC0>, 396 <&ccu CLK_MMC0_OUTPUT>, 397 <&ccu CLK_MMC0_SAMPLE>; 398 clock-names = "ahb", 399 "mmc", 400 "output", 401 "sample"; 402 resets = <&ccu RST_AHB1_MMC0>; 403 reset-names = "ahb"; 404 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&mmc0_pins>; 407 status = "disabled"; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 }; 411 412 mmc1: mmc@1c10000 { 413 compatible = "allwinner,sun7i-a20-mmc"; 414 reg = <0x01c10000 0x1000>; 415 clocks = <&ccu CLK_AHB1_MMC1>, 416 <&ccu CLK_MMC1>, 417 <&ccu CLK_MMC1_OUTPUT>, 418 <&ccu CLK_MMC1_SAMPLE>; 419 clock-names = "ahb", 420 "mmc", 421 "output", 422 "sample"; 423 resets = <&ccu RST_AHB1_MMC1>; 424 reset-names = "ahb"; 425 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&mmc1_pins>; 428 status = "disabled"; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 }; 432 433 mmc2: mmc@1c11000 { 434 compatible = "allwinner,sun7i-a20-mmc"; 435 reg = <0x01c11000 0x1000>; 436 clocks = <&ccu CLK_AHB1_MMC2>, 437 <&ccu CLK_MMC2>, 438 <&ccu CLK_MMC2_OUTPUT>, 439 <&ccu CLK_MMC2_SAMPLE>; 440 clock-names = "ahb", 441 "mmc", 442 "output", 443 "sample"; 444 resets = <&ccu RST_AHB1_MMC2>; 445 reset-names = "ahb"; 446 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 447 status = "disabled"; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 }; 451 452 mmc3: mmc@1c12000 { 453 compatible = "allwinner,sun7i-a20-mmc"; 454 reg = <0x01c12000 0x1000>; 455 clocks = <&ccu CLK_AHB1_MMC3>, 456 <&ccu CLK_MMC3>, 457 <&ccu CLK_MMC3_OUTPUT>, 458 <&ccu CLK_MMC3_SAMPLE>; 459 clock-names = "ahb", 460 "mmc", 461 "output", 462 "sample"; 463 resets = <&ccu RST_AHB1_MMC3>; 464 reset-names = "ahb"; 465 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 466 status = "disabled"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 }; 470 471 hdmi: hdmi@1c16000 { 472 compatible = "allwinner,sun6i-a31-hdmi"; 473 reg = <0x01c16000 0x1000>; 474 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, 476 <&ccu CLK_HDMI_DDC>, 477 <&ccu CLK_PLL_VIDEO0_2X>, 478 <&ccu CLK_PLL_VIDEO1_2X>; 479 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; 480 resets = <&ccu RST_AHB1_HDMI>; 481 dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 482 dmas = <&dma 13>, <&dma 13>, <&dma 14>; 483 status = "disabled"; 484 485 ports { 486 #address-cells = <1>; 487 #size-cells = <0>; 488 489 hdmi_in: port@0 { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <0>; 493 494 hdmi_in_tcon0: endpoint@0 { 495 reg = <0>; 496 remote-endpoint = <&tcon0_out_hdmi>; 497 }; 498 499 hdmi_in_tcon1: endpoint@1 { 500 reg = <1>; 501 remote-endpoint = <&tcon1_out_hdmi>; 502 }; 503 }; 504 505 hdmi_out: port@1 { 506 reg = <1>; 507 }; 508 }; 509 }; 510 511 usb_otg: usb@1c19000 { 512 compatible = "allwinner,sun6i-a31-musb"; 513 reg = <0x01c19000 0x0400>; 514 clocks = <&ccu CLK_AHB1_OTG>; 515 resets = <&ccu RST_AHB1_OTG>; 516 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 517 interrupt-names = "mc"; 518 phys = <&usbphy 0>; 519 phy-names = "usb"; 520 extcon = <&usbphy 0>; 521 dr_mode = "otg"; 522 status = "disabled"; 523 }; 524 525 usbphy: phy@1c19400 { 526 compatible = "allwinner,sun6i-a31-usb-phy"; 527 reg = <0x01c19400 0x10>, 528 <0x01c1a800 0x4>, 529 <0x01c1b800 0x4>; 530 reg-names = "phy_ctrl", 531 "pmu1", 532 "pmu2"; 533 clocks = <&ccu CLK_USB_PHY0>, 534 <&ccu CLK_USB_PHY1>, 535 <&ccu CLK_USB_PHY2>; 536 clock-names = "usb0_phy", 537 "usb1_phy", 538 "usb2_phy"; 539 resets = <&ccu RST_USB_PHY0>, 540 <&ccu RST_USB_PHY1>, 541 <&ccu RST_USB_PHY2>; 542 reset-names = "usb0_reset", 543 "usb1_reset", 544 "usb2_reset"; 545 status = "disabled"; 546 #phy-cells = <1>; 547 }; 548 549 ehci0: usb@1c1a000 { 550 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 551 reg = <0x01c1a000 0x100>; 552 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&ccu CLK_AHB1_EHCI0>; 554 resets = <&ccu RST_AHB1_EHCI0>; 555 phys = <&usbphy 1>; 556 phy-names = "usb"; 557 status = "disabled"; 558 }; 559 560 ohci0: usb@1c1a400 { 561 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 562 reg = <0x01c1a400 0x100>; 563 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; 565 resets = <&ccu RST_AHB1_OHCI0>; 566 phys = <&usbphy 1>; 567 phy-names = "usb"; 568 status = "disabled"; 569 }; 570 571 ehci1: usb@1c1b000 { 572 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 573 reg = <0x01c1b000 0x100>; 574 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&ccu CLK_AHB1_EHCI1>; 576 resets = <&ccu RST_AHB1_EHCI1>; 577 phys = <&usbphy 2>; 578 phy-names = "usb"; 579 status = "disabled"; 580 }; 581 582 ohci1: usb@1c1b400 { 583 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 584 reg = <0x01c1b400 0x100>; 585 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; 587 resets = <&ccu RST_AHB1_OHCI1>; 588 phys = <&usbphy 2>; 589 phy-names = "usb"; 590 status = "disabled"; 591 }; 592 593 ohci2: usb@1c1c400 { 594 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 595 reg = <0x01c1c400 0x100>; 596 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; 598 resets = <&ccu RST_AHB1_OHCI2>; 599 status = "disabled"; 600 }; 601 602 ccu: clock@1c20000 { 603 compatible = "allwinner,sun6i-a31-ccu"; 604 reg = <0x01c20000 0x400>; 605 clocks = <&osc24M>, <&rtc 0>; 606 clock-names = "hosc", "losc"; 607 #clock-cells = <1>; 608 #reset-cells = <1>; 609 }; 610 611 pio: pinctrl@1c20800 { 612 compatible = "allwinner,sun6i-a31-pinctrl"; 613 reg = <0x01c20800 0x400>; 614 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; 619 clock-names = "apb", "hosc", "losc"; 620 gpio-controller; 621 interrupt-controller; 622 #interrupt-cells = <3>; 623 #gpio-cells = <3>; 624 625 gmac_gmii_pins: gmac-gmii-pins { 626 pins = "PA0", "PA1", "PA2", "PA3", 627 "PA4", "PA5", "PA6", "PA7", 628 "PA8", "PA9", "PA10", "PA11", 629 "PA12", "PA13", "PA14", "PA15", 630 "PA16", "PA17", "PA18", "PA19", 631 "PA20", "PA21", "PA22", "PA23", 632 "PA24", "PA25", "PA26", "PA27"; 633 function = "gmac"; 634 /* 635 * data lines in GMII mode run at 125MHz and 636 * might need a higher signal drive strength 637 */ 638 drive-strength = <30>; 639 }; 640 641 gmac_mii_pins: gmac-mii-pins { 642 pins = "PA0", "PA1", "PA2", "PA3", 643 "PA8", "PA9", "PA11", 644 "PA12", "PA13", "PA14", "PA19", 645 "PA20", "PA21", "PA22", "PA23", 646 "PA24", "PA26", "PA27"; 647 function = "gmac"; 648 }; 649 650 gmac_rgmii_pins: gmac-rgmii-pins { 651 pins = "PA0", "PA1", "PA2", "PA3", 652 "PA9", "PA10", "PA11", 653 "PA12", "PA13", "PA14", "PA19", 654 "PA20", "PA25", "PA26", "PA27"; 655 function = "gmac"; 656 /* 657 * data lines in RGMII mode use DDR mode 658 * and need a higher signal drive strength 659 */ 660 drive-strength = <40>; 661 }; 662 663 i2c0_pins: i2c0-pins { 664 pins = "PH14", "PH15"; 665 function = "i2c0"; 666 }; 667 668 i2c1_pins: i2c1-pins { 669 pins = "PH16", "PH17"; 670 function = "i2c1"; 671 }; 672 673 i2c2_pins: i2c2-pins { 674 pins = "PH18", "PH19"; 675 function = "i2c2"; 676 }; 677 678 lcd0_rgb888_pins: lcd0-rgb888-pins { 679 pins = "PD0", "PD1", "PD2", "PD3", 680 "PD4", "PD5", "PD6", "PD7", 681 "PD8", "PD9", "PD10", "PD11", 682 "PD12", "PD13", "PD14", "PD15", 683 "PD16", "PD17", "PD18", "PD19", 684 "PD20", "PD21", "PD22", "PD23", 685 "PD24", "PD25", "PD26", "PD27"; 686 function = "lcd0"; 687 }; 688 689 mmc0_pins: mmc0-pins { 690 pins = "PF0", "PF1", "PF2", 691 "PF3", "PF4", "PF5"; 692 function = "mmc0"; 693 drive-strength = <30>; 694 bias-pull-up; 695 }; 696 697 mmc1_pins: mmc1-pins { 698 pins = "PG0", "PG1", "PG2", "PG3", 699 "PG4", "PG5"; 700 function = "mmc1"; 701 drive-strength = <30>; 702 bias-pull-up; 703 }; 704 705 mmc2_4bit_pins: mmc2-4bit-pins { 706 pins = "PC6", "PC7", "PC8", "PC9", 707 "PC10", "PC11"; 708 function = "mmc2"; 709 drive-strength = <30>; 710 bias-pull-up; 711 }; 712 713 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { 714 pins = "PC6", "PC7", "PC8", "PC9", 715 "PC10", "PC11", "PC12", 716 "PC13", "PC14", "PC15", 717 "PC24"; 718 function = "mmc2"; 719 drive-strength = <30>; 720 bias-pull-up; 721 }; 722 723 mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins { 724 pins = "PC6", "PC7", "PC8", "PC9", 725 "PC10", "PC11", "PC12", 726 "PC13", "PC14", "PC15", 727 "PC24"; 728 function = "mmc3"; 729 drive-strength = <40>; 730 bias-pull-up; 731 }; 732 733 spdif_tx_pin: spdif-tx-pin { 734 pins = "PH28"; 735 function = "spdif"; 736 }; 737 738 uart0_ph_pins: uart0-ph-pins { 739 pins = "PH20", "PH21"; 740 function = "uart0"; 741 }; 742 }; 743 744 timer@1c20c00 { 745 compatible = "allwinner,sun4i-a10-timer"; 746 reg = <0x01c20c00 0xa0>; 747 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&osc24M>; 754 }; 755 756 wdt1: watchdog@1c20ca0 { 757 compatible = "allwinner,sun6i-a31-wdt"; 758 reg = <0x01c20ca0 0x20>; 759 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&osc24M>; 761 }; 762 763 spdif: spdif@1c21000 { 764 #sound-dai-cells = <0>; 765 compatible = "allwinner,sun6i-a31-spdif"; 766 reg = <0x01c21000 0x400>; 767 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>; 769 resets = <&ccu RST_APB1_SPDIF>; 770 clock-names = "apb", "spdif"; 771 dmas = <&dma 2>, <&dma 2>; 772 dma-names = "rx", "tx"; 773 status = "disabled"; 774 }; 775 776 i2s0: i2s@1c22000 { 777 #sound-dai-cells = <0>; 778 compatible = "allwinner,sun6i-a31-i2s"; 779 reg = <0x01c22000 0x400>; 780 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; 782 resets = <&ccu RST_APB1_DAUDIO0>; 783 clock-names = "apb", "mod"; 784 dmas = <&dma 3>, <&dma 3>; 785 dma-names = "rx", "tx"; 786 status = "disabled"; 787 }; 788 789 i2s1: i2s@1c22400 { 790 #sound-dai-cells = <0>; 791 compatible = "allwinner,sun6i-a31-i2s"; 792 reg = <0x01c22400 0x400>; 793 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; 795 resets = <&ccu RST_APB1_DAUDIO1>; 796 clock-names = "apb", "mod"; 797 dmas = <&dma 4>, <&dma 4>; 798 dma-names = "rx", "tx"; 799 status = "disabled"; 800 }; 801 802 lradc: lradc@1c22800 { 803 compatible = "allwinner,sun4i-a10-lradc-keys"; 804 reg = <0x01c22800 0x100>; 805 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 806 status = "disabled"; 807 }; 808 809 rtp: rtp@1c25000 { 810 compatible = "allwinner,sun6i-a31-ts"; 811 reg = <0x01c25000 0x100>; 812 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 813 #thermal-sensor-cells = <0>; 814 }; 815 816 uart0: serial@1c28000 { 817 compatible = "snps,dw-apb-uart"; 818 reg = <0x01c28000 0x400>; 819 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 820 reg-shift = <2>; 821 reg-io-width = <4>; 822 clocks = <&ccu CLK_APB2_UART0>; 823 resets = <&ccu RST_APB2_UART0>; 824 dmas = <&dma 6>, <&dma 6>; 825 dma-names = "rx", "tx"; 826 status = "disabled"; 827 }; 828 829 uart1: serial@1c28400 { 830 compatible = "snps,dw-apb-uart"; 831 reg = <0x01c28400 0x400>; 832 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 833 reg-shift = <2>; 834 reg-io-width = <4>; 835 clocks = <&ccu CLK_APB2_UART1>; 836 resets = <&ccu RST_APB2_UART1>; 837 dmas = <&dma 7>, <&dma 7>; 838 dma-names = "rx", "tx"; 839 status = "disabled"; 840 }; 841 842 uart2: serial@1c28800 { 843 compatible = "snps,dw-apb-uart"; 844 reg = <0x01c28800 0x400>; 845 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 846 reg-shift = <2>; 847 reg-io-width = <4>; 848 clocks = <&ccu CLK_APB2_UART2>; 849 resets = <&ccu RST_APB2_UART2>; 850 dmas = <&dma 8>, <&dma 8>; 851 dma-names = "rx", "tx"; 852 status = "disabled"; 853 }; 854 855 uart3: serial@1c28c00 { 856 compatible = "snps,dw-apb-uart"; 857 reg = <0x01c28c00 0x400>; 858 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 859 reg-shift = <2>; 860 reg-io-width = <4>; 861 clocks = <&ccu CLK_APB2_UART3>; 862 resets = <&ccu RST_APB2_UART3>; 863 dmas = <&dma 9>, <&dma 9>; 864 dma-names = "rx", "tx"; 865 status = "disabled"; 866 }; 867 868 uart4: serial@1c29000 { 869 compatible = "snps,dw-apb-uart"; 870 reg = <0x01c29000 0x400>; 871 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 872 reg-shift = <2>; 873 reg-io-width = <4>; 874 clocks = <&ccu CLK_APB2_UART4>; 875 resets = <&ccu RST_APB2_UART4>; 876 dmas = <&dma 10>, <&dma 10>; 877 dma-names = "rx", "tx"; 878 status = "disabled"; 879 }; 880 881 uart5: serial@1c29400 { 882 compatible = "snps,dw-apb-uart"; 883 reg = <0x01c29400 0x400>; 884 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 885 reg-shift = <2>; 886 reg-io-width = <4>; 887 clocks = <&ccu CLK_APB2_UART5>; 888 resets = <&ccu RST_APB2_UART5>; 889 dmas = <&dma 22>, <&dma 22>; 890 dma-names = "rx", "tx"; 891 status = "disabled"; 892 }; 893 894 i2c0: i2c@1c2ac00 { 895 compatible = "allwinner,sun6i-a31-i2c"; 896 reg = <0x01c2ac00 0x400>; 897 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&ccu CLK_APB2_I2C0>; 899 resets = <&ccu RST_APB2_I2C0>; 900 pinctrl-names = "default"; 901 pinctrl-0 = <&i2c0_pins>; 902 status = "disabled"; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 }; 906 907 i2c1: i2c@1c2b000 { 908 compatible = "allwinner,sun6i-a31-i2c"; 909 reg = <0x01c2b000 0x400>; 910 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&ccu CLK_APB2_I2C1>; 912 resets = <&ccu RST_APB2_I2C1>; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&i2c1_pins>; 915 status = "disabled"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 }; 919 920 i2c2: i2c@1c2b400 { 921 compatible = "allwinner,sun6i-a31-i2c"; 922 reg = <0x01c2b400 0x400>; 923 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&ccu CLK_APB2_I2C2>; 925 resets = <&ccu RST_APB2_I2C2>; 926 pinctrl-names = "default"; 927 pinctrl-0 = <&i2c2_pins>; 928 status = "disabled"; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 }; 932 933 i2c3: i2c@1c2b800 { 934 compatible = "allwinner,sun6i-a31-i2c"; 935 reg = <0x01c2b800 0x400>; 936 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&ccu CLK_APB2_I2C3>; 938 resets = <&ccu RST_APB2_I2C3>; 939 status = "disabled"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 }; 943 944 gmac: ethernet@1c30000 { 945 compatible = "allwinner,sun7i-a20-gmac"; 946 reg = <0x01c30000 0x1054>; 947 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "macirq"; 949 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; 950 clock-names = "stmmaceth", "allwinner_gmac_tx"; 951 resets = <&ccu RST_AHB1_EMAC>; 952 reset-names = "stmmaceth"; 953 snps,pbl = <2>; 954 snps,fixed-burst; 955 snps,force_sf_dma_mode; 956 status = "disabled"; 957 958 mdio: mdio { 959 compatible = "snps,dwmac-mdio"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 }; 963 }; 964 965 crypto: crypto-engine@1c15000 { 966 compatible = "allwinner,sun6i-a31-crypto", 967 "allwinner,sun4i-a10-crypto"; 968 reg = <0x01c15000 0x1000>; 969 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; 971 clock-names = "ahb", "mod"; 972 resets = <&ccu RST_AHB1_SS>; 973 reset-names = "ahb"; 974 }; 975 976 codec: codec@1c22c00 { 977 #sound-dai-cells = <0>; 978 compatible = "allwinner,sun6i-a31-codec"; 979 reg = <0x01c22c00 0x400>; 980 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; 982 clock-names = "apb", "codec"; 983 resets = <&ccu RST_APB1_CODEC>; 984 dmas = <&dma 15>, <&dma 15>; 985 dma-names = "rx", "tx"; 986 status = "disabled"; 987 }; 988 989 timer@1c60000 { 990 compatible = "allwinner,sun6i-a31-hstimer", 991 "allwinner,sun7i-a20-hstimer"; 992 reg = <0x01c60000 0x1000>; 993 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&ccu CLK_AHB1_HSTIMER>; 998 resets = <&ccu RST_AHB1_HSTIMER>; 999 }; 1000 1001 spi0: spi@1c68000 { 1002 compatible = "allwinner,sun6i-a31-spi"; 1003 reg = <0x01c68000 0x1000>; 1004 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; 1006 clock-names = "ahb", "mod"; 1007 dmas = <&dma 23>, <&dma 23>; 1008 dma-names = "rx", "tx"; 1009 resets = <&ccu RST_AHB1_SPI0>; 1010 status = "disabled"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 }; 1014 1015 spi1: spi@1c69000 { 1016 compatible = "allwinner,sun6i-a31-spi"; 1017 reg = <0x01c69000 0x1000>; 1018 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; 1020 clock-names = "ahb", "mod"; 1021 dmas = <&dma 24>, <&dma 24>; 1022 dma-names = "rx", "tx"; 1023 resets = <&ccu RST_AHB1_SPI1>; 1024 status = "disabled"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 }; 1028 1029 spi2: spi@1c6a000 { 1030 compatible = "allwinner,sun6i-a31-spi"; 1031 reg = <0x01c6a000 0x1000>; 1032 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; 1034 clock-names = "ahb", "mod"; 1035 dmas = <&dma 25>, <&dma 25>; 1036 dma-names = "rx", "tx"; 1037 resets = <&ccu RST_AHB1_SPI2>; 1038 status = "disabled"; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 }; 1042 1043 spi3: spi@1c6b000 { 1044 compatible = "allwinner,sun6i-a31-spi"; 1045 reg = <0x01c6b000 0x1000>; 1046 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; 1048 clock-names = "ahb", "mod"; 1049 dmas = <&dma 26>, <&dma 26>; 1050 dma-names = "rx", "tx"; 1051 resets = <&ccu RST_AHB1_SPI3>; 1052 status = "disabled"; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 }; 1056 1057 gic: interrupt-controller@1c81000 { 1058 compatible = "arm,gic-400"; 1059 reg = <0x01c81000 0x1000>, 1060 <0x01c82000 0x2000>, 1061 <0x01c84000 0x2000>, 1062 <0x01c86000 0x2000>; 1063 interrupt-controller; 1064 #interrupt-cells = <3>; 1065 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1066 }; 1067 1068 fe0: display-frontend@1e00000 { 1069 compatible = "allwinner,sun6i-a31-display-frontend"; 1070 reg = <0x01e00000 0x20000>; 1071 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, 1073 <&ccu CLK_DRAM_FE0>; 1074 clock-names = "ahb", "mod", 1075 "ram"; 1076 resets = <&ccu RST_AHB1_FE0>; 1077 1078 ports { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 1082 fe0_out: port@1 { 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 reg = <1>; 1086 1087 fe0_out_be0: endpoint@0 { 1088 reg = <0>; 1089 remote-endpoint = <&be0_in_fe0>; 1090 }; 1091 1092 fe0_out_be1: endpoint@1 { 1093 reg = <1>; 1094 remote-endpoint = <&be1_in_fe0>; 1095 }; 1096 }; 1097 }; 1098 }; 1099 1100 fe1: display-frontend@1e20000 { 1101 compatible = "allwinner,sun6i-a31-display-frontend"; 1102 reg = <0x01e20000 0x20000>; 1103 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, 1105 <&ccu CLK_DRAM_FE1>; 1106 clock-names = "ahb", "mod", 1107 "ram"; 1108 resets = <&ccu RST_AHB1_FE1>; 1109 1110 ports { 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 1114 fe1_out: port@1 { 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 reg = <1>; 1118 1119 fe1_out_be0: endpoint@0 { 1120 reg = <0>; 1121 remote-endpoint = <&be0_in_fe1>; 1122 }; 1123 1124 fe1_out_be1: endpoint@1 { 1125 reg = <1>; 1126 remote-endpoint = <&be1_in_fe1>; 1127 }; 1128 }; 1129 }; 1130 }; 1131 1132 be1: display-backend@1e40000 { 1133 compatible = "allwinner,sun6i-a31-display-backend"; 1134 reg = <0x01e40000 0x10000>; 1135 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, 1137 <&ccu CLK_DRAM_BE1>; 1138 clock-names = "ahb", "mod", 1139 "ram"; 1140 resets = <&ccu RST_AHB1_BE1>; 1141 1142 assigned-clocks = <&ccu CLK_BE1>; 1143 assigned-clock-rates = <300000000>; 1144 1145 ports { 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 1149 be1_in: port@0 { 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 reg = <0>; 1153 1154 be1_in_fe0: endpoint@0 { 1155 reg = <0>; 1156 remote-endpoint = <&fe0_out_be1>; 1157 }; 1158 1159 be1_in_fe1: endpoint@1 { 1160 reg = <1>; 1161 remote-endpoint = <&fe1_out_be1>; 1162 }; 1163 }; 1164 1165 be1_out: port@1 { 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 reg = <1>; 1169 1170 be1_out_drc1: endpoint@1 { 1171 reg = <1>; 1172 remote-endpoint = <&drc1_in_be1>; 1173 }; 1174 }; 1175 }; 1176 }; 1177 1178 drc1: drc@1e50000 { 1179 compatible = "allwinner,sun6i-a31-drc"; 1180 reg = <0x01e50000 0x10000>; 1181 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, 1183 <&ccu CLK_DRAM_DRC1>; 1184 clock-names = "ahb", "mod", 1185 "ram"; 1186 resets = <&ccu RST_AHB1_DRC1>; 1187 1188 assigned-clocks = <&ccu CLK_IEP_DRC1>; 1189 assigned-clock-rates = <300000000>; 1190 1191 ports { 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 1195 drc1_in: port@0 { 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 reg = <0>; 1199 1200 drc1_in_be1: endpoint@1 { 1201 reg = <1>; 1202 remote-endpoint = <&be1_out_drc1>; 1203 }; 1204 }; 1205 1206 drc1_out: port@1 { 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 reg = <1>; 1210 1211 drc1_out_tcon0: endpoint@0 { 1212 reg = <0>; 1213 remote-endpoint = <&tcon0_in_drc1>; 1214 }; 1215 1216 drc1_out_tcon1: endpoint@1 { 1217 reg = <1>; 1218 remote-endpoint = <&tcon1_in_drc1>; 1219 }; 1220 }; 1221 }; 1222 }; 1223 1224 be0: display-backend@1e60000 { 1225 compatible = "allwinner,sun6i-a31-display-backend"; 1226 reg = <0x01e60000 0x10000>; 1227 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, 1229 <&ccu CLK_DRAM_BE0>; 1230 clock-names = "ahb", "mod", 1231 "ram"; 1232 resets = <&ccu RST_AHB1_BE0>; 1233 1234 assigned-clocks = <&ccu CLK_BE0>; 1235 assigned-clock-rates = <300000000>; 1236 1237 ports { 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 1241 be0_in: port@0 { 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 reg = <0>; 1245 1246 be0_in_fe0: endpoint@0 { 1247 reg = <0>; 1248 remote-endpoint = <&fe0_out_be0>; 1249 }; 1250 1251 be0_in_fe1: endpoint@1 { 1252 reg = <1>; 1253 remote-endpoint = <&fe1_out_be0>; 1254 }; 1255 }; 1256 1257 be0_out: port@1 { 1258 reg = <1>; 1259 1260 be0_out_drc0: endpoint { 1261 remote-endpoint = <&drc0_in_be0>; 1262 }; 1263 }; 1264 }; 1265 }; 1266 1267 drc0: drc@1e70000 { 1268 compatible = "allwinner,sun6i-a31-drc"; 1269 reg = <0x01e70000 0x10000>; 1270 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1271 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, 1272 <&ccu CLK_DRAM_DRC0>; 1273 clock-names = "ahb", "mod", 1274 "ram"; 1275 resets = <&ccu RST_AHB1_DRC0>; 1276 1277 assigned-clocks = <&ccu CLK_IEP_DRC0>; 1278 assigned-clock-rates = <300000000>; 1279 1280 ports { 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 1284 drc0_in: port@0 { 1285 reg = <0>; 1286 1287 drc0_in_be0: endpoint { 1288 remote-endpoint = <&be0_out_drc0>; 1289 }; 1290 }; 1291 1292 drc0_out: port@1 { 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 reg = <1>; 1296 1297 drc0_out_tcon0: endpoint@0 { 1298 reg = <0>; 1299 remote-endpoint = <&tcon0_in_drc0>; 1300 }; 1301 1302 drc0_out_tcon1: endpoint@1 { 1303 reg = <1>; 1304 remote-endpoint = <&tcon1_in_drc0>; 1305 }; 1306 }; 1307 }; 1308 }; 1309 1310 rtc: rtc@1f00000 { 1311 #clock-cells = <1>; 1312 compatible = "allwinner,sun6i-a31-rtc"; 1313 reg = <0x01f00000 0x54>; 1314 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&osc32k>; 1317 clock-output-names = "osc32k"; 1318 }; 1319 1320 nmi_intc: interrupt-controller@1f00c00 { 1321 compatible = "allwinner,sun6i-a31-r-intc"; 1322 interrupt-controller; 1323 #interrupt-cells = <2>; 1324 reg = <0x01f00c00 0x400>; 1325 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1326 }; 1327 1328 prcm@1f01400 { 1329 compatible = "allwinner,sun6i-a31-prcm"; 1330 reg = <0x01f01400 0x200>; 1331 1332 ar100: ar100_clk { 1333 compatible = "allwinner,sun6i-a31-ar100-clk"; 1334 #clock-cells = <0>; 1335 clocks = <&rtc 0>, <&osc24M>, 1336 <&ccu CLK_PLL_PERIPH>, 1337 <&ccu CLK_PLL_PERIPH>; 1338 clock-output-names = "ar100"; 1339 }; 1340 1341 ahb0: ahb0_clk { 1342 compatible = "fixed-factor-clock"; 1343 #clock-cells = <0>; 1344 clock-div = <1>; 1345 clock-mult = <1>; 1346 clocks = <&ar100>; 1347 clock-output-names = "ahb0"; 1348 }; 1349 1350 apb0: apb0_clk { 1351 compatible = "allwinner,sun6i-a31-apb0-clk"; 1352 #clock-cells = <0>; 1353 clocks = <&ahb0>; 1354 clock-output-names = "apb0"; 1355 }; 1356 1357 apb0_gates: apb0_gates_clk { 1358 compatible = "allwinner,sun6i-a31-apb0-gates-clk"; 1359 #clock-cells = <1>; 1360 clocks = <&apb0>; 1361 clock-output-names = "apb0_pio", "apb0_ir", 1362 "apb0_timer", "apb0_p2wi", 1363 "apb0_uart", "apb0_1wire", 1364 "apb0_i2c"; 1365 }; 1366 1367 ir_clk: ir_clk { 1368 #clock-cells = <0>; 1369 compatible = "allwinner,sun4i-a10-mod0-clk"; 1370 clocks = <&rtc 0>, <&osc24M>; 1371 clock-output-names = "ir"; 1372 }; 1373 1374 apb0_rst: apb0_rst { 1375 compatible = "allwinner,sun6i-a31-clock-reset"; 1376 #reset-cells = <1>; 1377 }; 1378 }; 1379 1380 cpucfg@1f01c00 { 1381 compatible = "allwinner,sun6i-a31-cpuconfig"; 1382 reg = <0x01f01c00 0x300>; 1383 }; 1384 1385 ir: ir@1f02000 { 1386 compatible = "allwinner,sun6i-a31-ir"; 1387 clocks = <&apb0_gates 1>, <&ir_clk>; 1388 clock-names = "apb", "ir"; 1389 resets = <&apb0_rst 1>; 1390 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1391 reg = <0x01f02000 0x40>; 1392 status = "disabled"; 1393 }; 1394 1395 r_pio: pinctrl@1f02c00 { 1396 compatible = "allwinner,sun6i-a31-r-pinctrl"; 1397 reg = <0x01f02c00 0x400>; 1398 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1400 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; 1401 clock-names = "apb", "hosc", "losc"; 1402 resets = <&apb0_rst 0>; 1403 gpio-controller; 1404 interrupt-controller; 1405 #interrupt-cells = <3>; 1406 #gpio-cells = <3>; 1407 1408 s_ir_rx_pin: s-ir-rx-pin { 1409 pins = "PL4"; 1410 function = "s_ir"; 1411 }; 1412 1413 s_p2wi_pins: s-p2wi-pins { 1414 pins = "PL0", "PL1"; 1415 function = "s_p2wi"; 1416 }; 1417 }; 1418 1419 p2wi: i2c@1f03400 { 1420 compatible = "allwinner,sun6i-a31-p2wi"; 1421 reg = <0x01f03400 0x400>; 1422 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&apb0_gates 3>; 1424 clock-frequency = <100000>; 1425 resets = <&apb0_rst 3>; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&s_p2wi_pins>; 1428 status = "disabled"; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 }; 1432 }; 1433}; 1434