1/* 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "armv7-m.dtsi" 49#include <dt-bindings/clock/stm32fx-clock.h> 50#include <dt-bindings/mfd/stm32f4-rcc.h> 51 52/ { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <0>; 61 }; 62 63 clk_lse: clk-lse { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <32768>; 67 }; 68 69 clk_lsi: clk-lsi { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32000>; 73 }; 74 75 clk_i2s_ckin: i2s-ckin { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <0>; 79 }; 80 }; 81 82 soc { 83 romem: efuse@1fff7800 { 84 compatible = "st,stm32f4-otp"; 85 reg = <0x1fff7800 0x400>; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ts_cal1: calib@22c { 89 reg = <0x22c 0x2>; 90 }; 91 ts_cal2: calib@22e { 92 reg = <0x22e 0x2>; 93 }; 94 }; 95 96 timer2: timer@40000000 { 97 compatible = "st,stm32-timer"; 98 reg = <0x40000000 0x400>; 99 interrupts = <28>; 100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 101 status = "disabled"; 102 }; 103 104 timers2: timers@40000000 { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 compatible = "st,stm32-timers"; 108 reg = <0x40000000 0x400>; 109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 110 clock-names = "int"; 111 status = "disabled"; 112 113 pwm { 114 compatible = "st,stm32-pwm"; 115 #pwm-cells = <3>; 116 status = "disabled"; 117 }; 118 119 timer@1 { 120 compatible = "st,stm32-timer-trigger"; 121 reg = <1>; 122 status = "disabled"; 123 }; 124 }; 125 126 timer3: timer@40000400 { 127 compatible = "st,stm32-timer"; 128 reg = <0x40000400 0x400>; 129 interrupts = <29>; 130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; 131 status = "disabled"; 132 }; 133 134 timers3: timers@40000400 { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 compatible = "st,stm32-timers"; 138 reg = <0x40000400 0x400>; 139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; 140 clock-names = "int"; 141 status = "disabled"; 142 143 pwm { 144 compatible = "st,stm32-pwm"; 145 #pwm-cells = <3>; 146 status = "disabled"; 147 }; 148 149 timer@2 { 150 compatible = "st,stm32-timer-trigger"; 151 reg = <2>; 152 status = "disabled"; 153 }; 154 }; 155 156 timer4: timer@40000800 { 157 compatible = "st,stm32-timer"; 158 reg = <0x40000800 0x400>; 159 interrupts = <30>; 160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; 161 status = "disabled"; 162 }; 163 164 timers4: timers@40000800 { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 compatible = "st,stm32-timers"; 168 reg = <0x40000800 0x400>; 169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; 170 clock-names = "int"; 171 status = "disabled"; 172 173 pwm { 174 compatible = "st,stm32-pwm"; 175 #pwm-cells = <3>; 176 status = "disabled"; 177 }; 178 179 timer@3 { 180 compatible = "st,stm32-timer-trigger"; 181 reg = <3>; 182 status = "disabled"; 183 }; 184 }; 185 186 timer5: timer@40000c00 { 187 compatible = "st,stm32-timer"; 188 reg = <0x40000c00 0x400>; 189 interrupts = <50>; 190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; 191 }; 192 193 timers5: timers@40000c00 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 compatible = "st,stm32-timers"; 197 reg = <0x40000C00 0x400>; 198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; 199 clock-names = "int"; 200 status = "disabled"; 201 202 pwm { 203 compatible = "st,stm32-pwm"; 204 #pwm-cells = <3>; 205 status = "disabled"; 206 }; 207 208 timer@4 { 209 compatible = "st,stm32-timer-trigger"; 210 reg = <4>; 211 status = "disabled"; 212 }; 213 }; 214 215 timer6: timer@40001000 { 216 compatible = "st,stm32-timer"; 217 reg = <0x40001000 0x400>; 218 interrupts = <54>; 219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; 220 status = "disabled"; 221 }; 222 223 timers6: timers@40001000 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "st,stm32-timers"; 227 reg = <0x40001000 0x400>; 228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; 229 clock-names = "int"; 230 status = "disabled"; 231 232 timer@5 { 233 compatible = "st,stm32-timer-trigger"; 234 reg = <5>; 235 status = "disabled"; 236 }; 237 }; 238 239 timer7: timer@40001400 { 240 compatible = "st,stm32-timer"; 241 reg = <0x40001400 0x400>; 242 interrupts = <55>; 243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; 244 status = "disabled"; 245 }; 246 247 timers7: timers@40001400 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "st,stm32-timers"; 251 reg = <0x40001400 0x400>; 252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; 253 clock-names = "int"; 254 status = "disabled"; 255 256 timer@6 { 257 compatible = "st,stm32-timer-trigger"; 258 reg = <6>; 259 status = "disabled"; 260 }; 261 }; 262 263 timers12: timers@40001800 { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 compatible = "st,stm32-timers"; 267 reg = <0x40001800 0x400>; 268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; 269 clock-names = "int"; 270 status = "disabled"; 271 272 pwm { 273 compatible = "st,stm32-pwm"; 274 #pwm-cells = <3>; 275 status = "disabled"; 276 }; 277 278 timer@11 { 279 compatible = "st,stm32-timer-trigger"; 280 reg = <11>; 281 status = "disabled"; 282 }; 283 }; 284 285 timers13: timers@40001c00 { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 compatible = "st,stm32-timers"; 289 reg = <0x40001C00 0x400>; 290 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; 291 clock-names = "int"; 292 status = "disabled"; 293 294 pwm { 295 compatible = "st,stm32-pwm"; 296 #pwm-cells = <3>; 297 status = "disabled"; 298 }; 299 }; 300 301 timers14: timers@40002000 { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 compatible = "st,stm32-timers"; 305 reg = <0x40002000 0x400>; 306 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; 307 clock-names = "int"; 308 status = "disabled"; 309 310 pwm { 311 compatible = "st,stm32-pwm"; 312 #pwm-cells = <3>; 313 status = "disabled"; 314 }; 315 }; 316 317 rtc: rtc@40002800 { 318 compatible = "st,stm32-rtc"; 319 reg = <0x40002800 0x400>; 320 clocks = <&rcc 1 CLK_RTC>; 321 assigned-clocks = <&rcc 1 CLK_RTC>; 322 assigned-clock-parents = <&rcc 1 CLK_LSE>; 323 interrupt-parent = <&exti>; 324 interrupts = <17 1>; 325 interrupt-names = "alarm"; 326 st,syscfg = <&pwrcfg 0x00 0x100>; 327 status = "disabled"; 328 }; 329 330 iwdg: watchdog@40003000 { 331 compatible = "st,stm32-iwdg"; 332 reg = <0x40003000 0x400>; 333 clocks = <&clk_lsi>; 334 clock-names = "lsi"; 335 status = "disabled"; 336 }; 337 338 spi2: spi@40003800 { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 compatible = "st,stm32f4-spi"; 342 reg = <0x40003800 0x400>; 343 interrupts = <36>; 344 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; 345 status = "disabled"; 346 }; 347 348 spi3: spi@40003c00 { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 compatible = "st,stm32f4-spi"; 352 reg = <0x40003c00 0x400>; 353 interrupts = <51>; 354 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; 355 status = "disabled"; 356 }; 357 358 usart2: serial@40004400 { 359 compatible = "st,stm32-uart"; 360 reg = <0x40004400 0x400>; 361 interrupts = <38>; 362 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; 363 status = "disabled"; 364 }; 365 366 usart3: serial@40004800 { 367 compatible = "st,stm32-uart"; 368 reg = <0x40004800 0x400>; 369 interrupts = <39>; 370 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; 371 status = "disabled"; 372 dmas = <&dma1 1 4 0x400 0x0>, 373 <&dma1 3 4 0x400 0x0>; 374 dma-names = "rx", "tx"; 375 }; 376 377 usart4: serial@40004c00 { 378 compatible = "st,stm32-uart"; 379 reg = <0x40004c00 0x400>; 380 interrupts = <52>; 381 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; 382 status = "disabled"; 383 }; 384 385 usart5: serial@40005000 { 386 compatible = "st,stm32-uart"; 387 reg = <0x40005000 0x400>; 388 interrupts = <53>; 389 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; 390 status = "disabled"; 391 }; 392 393 i2c1: i2c@40005400 { 394 compatible = "st,stm32f4-i2c"; 395 reg = <0x40005400 0x400>; 396 interrupts = <31>, 397 <32>; 398 resets = <&rcc STM32F4_APB1_RESET(I2C1)>; 399 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 dac: dac@40007400 { 406 compatible = "st,stm32f4-dac-core"; 407 reg = <0x40007400 0x400>; 408 resets = <&rcc STM32F4_APB1_RESET(DAC)>; 409 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; 410 clock-names = "pclk"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 status = "disabled"; 414 415 dac1: dac@1 { 416 compatible = "st,stm32-dac"; 417 #io-channels-cells = <1>; 418 reg = <1>; 419 status = "disabled"; 420 }; 421 422 dac2: dac@2 { 423 compatible = "st,stm32-dac"; 424 #io-channels-cells = <1>; 425 reg = <2>; 426 status = "disabled"; 427 }; 428 }; 429 430 usart7: serial@40007800 { 431 compatible = "st,stm32-uart"; 432 reg = <0x40007800 0x400>; 433 interrupts = <82>; 434 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; 435 status = "disabled"; 436 }; 437 438 usart8: serial@40007c00 { 439 compatible = "st,stm32-uart"; 440 reg = <0x40007c00 0x400>; 441 interrupts = <83>; 442 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; 443 status = "disabled"; 444 }; 445 446 timers1: timers@40010000 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 compatible = "st,stm32-timers"; 450 reg = <0x40010000 0x400>; 451 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; 452 clock-names = "int"; 453 status = "disabled"; 454 455 pwm { 456 compatible = "st,stm32-pwm"; 457 #pwm-cells = <3>; 458 status = "disabled"; 459 }; 460 461 timer@0 { 462 compatible = "st,stm32-timer-trigger"; 463 reg = <0>; 464 status = "disabled"; 465 }; 466 }; 467 468 timers8: timers@40010400 { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 compatible = "st,stm32-timers"; 472 reg = <0x40010400 0x400>; 473 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; 474 clock-names = "int"; 475 status = "disabled"; 476 477 pwm { 478 compatible = "st,stm32-pwm"; 479 #pwm-cells = <3>; 480 status = "disabled"; 481 }; 482 483 timer@7 { 484 compatible = "st,stm32-timer-trigger"; 485 reg = <7>; 486 status = "disabled"; 487 }; 488 }; 489 490 usart1: serial@40011000 { 491 compatible = "st,stm32-uart"; 492 reg = <0x40011000 0x400>; 493 interrupts = <37>; 494 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; 495 status = "disabled"; 496 dmas = <&dma2 2 4 0x400 0x0>, 497 <&dma2 7 4 0x400 0x0>; 498 dma-names = "rx", "tx"; 499 }; 500 501 usart6: serial@40011400 { 502 compatible = "st,stm32-uart"; 503 reg = <0x40011400 0x400>; 504 interrupts = <71>; 505 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; 506 status = "disabled"; 507 }; 508 509 adc: adc@40012000 { 510 compatible = "st,stm32f4-adc-core"; 511 reg = <0x40012000 0x400>; 512 interrupts = <18>; 513 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 514 clock-names = "adc"; 515 interrupt-controller; 516 #interrupt-cells = <1>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 521 adc1: adc@0 { 522 compatible = "st,stm32f4-adc"; 523 #io-channel-cells = <1>; 524 reg = <0x0>; 525 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 526 interrupt-parent = <&adc>; 527 interrupts = <0>; 528 dmas = <&dma2 0 0 0x400 0x0>; 529 dma-names = "rx"; 530 status = "disabled"; 531 }; 532 533 adc2: adc@100 { 534 compatible = "st,stm32f4-adc"; 535 #io-channel-cells = <1>; 536 reg = <0x100>; 537 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; 538 interrupt-parent = <&adc>; 539 interrupts = <1>; 540 dmas = <&dma2 3 1 0x400 0x0>; 541 dma-names = "rx"; 542 status = "disabled"; 543 }; 544 545 adc3: adc@200 { 546 compatible = "st,stm32f4-adc"; 547 #io-channel-cells = <1>; 548 reg = <0x200>; 549 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; 550 interrupt-parent = <&adc>; 551 interrupts = <2>; 552 dmas = <&dma2 1 2 0x400 0x0>; 553 dma-names = "rx"; 554 status = "disabled"; 555 }; 556 }; 557 558 sdio: sdio@40012c00 { 559 compatible = "arm,pl180", "arm,primecell"; 560 arm,primecell-periphid = <0x00880180>; 561 reg = <0x40012c00 0x400>; 562 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; 563 clock-names = "apb_pclk"; 564 interrupts = <49>; 565 max-frequency = <48000000>; 566 status = "disabled"; 567 }; 568 569 spi1: spi@40013000 { 570 #address-cells = <1>; 571 #size-cells = <0>; 572 compatible = "st,stm32f4-spi"; 573 reg = <0x40013000 0x400>; 574 interrupts = <35>; 575 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; 576 status = "disabled"; 577 }; 578 579 spi4: spi@40013400 { 580 #address-cells = <1>; 581 #size-cells = <0>; 582 compatible = "st,stm32f4-spi"; 583 reg = <0x40013400 0x400>; 584 interrupts = <84>; 585 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; 586 status = "disabled"; 587 }; 588 589 syscfg: system-config@40013800 { 590 compatible = "syscon"; 591 reg = <0x40013800 0x400>; 592 }; 593 594 exti: interrupt-controller@40013c00 { 595 compatible = "st,stm32-exti"; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 reg = <0x40013C00 0x400>; 599 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 600 }; 601 602 timers9: timers@40014000 { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 compatible = "st,stm32-timers"; 606 reg = <0x40014000 0x400>; 607 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; 608 clock-names = "int"; 609 status = "disabled"; 610 611 pwm { 612 compatible = "st,stm32-pwm"; 613 #pwm-cells = <3>; 614 status = "disabled"; 615 }; 616 617 timer@8 { 618 compatible = "st,stm32-timer-trigger"; 619 reg = <8>; 620 status = "disabled"; 621 }; 622 }; 623 624 timers10: timers@40014400 { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 compatible = "st,stm32-timers"; 628 reg = <0x40014400 0x400>; 629 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; 630 clock-names = "int"; 631 status = "disabled"; 632 633 pwm { 634 compatible = "st,stm32-pwm"; 635 #pwm-cells = <3>; 636 status = "disabled"; 637 }; 638 }; 639 640 timers11: timers@40014800 { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 compatible = "st,stm32-timers"; 644 reg = <0x40014800 0x400>; 645 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; 646 clock-names = "int"; 647 status = "disabled"; 648 649 pwm { 650 compatible = "st,stm32-pwm"; 651 #pwm-cells = <3>; 652 status = "disabled"; 653 }; 654 }; 655 656 spi5: spi@40015000 { 657 #address-cells = <1>; 658 #size-cells = <0>; 659 compatible = "st,stm32f4-spi"; 660 reg = <0x40015000 0x400>; 661 interrupts = <85>; 662 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; 663 status = "disabled"; 664 }; 665 666 spi6: spi@40015400 { 667 #address-cells = <1>; 668 #size-cells = <0>; 669 compatible = "st,stm32f4-spi"; 670 reg = <0x40015400 0x400>; 671 interrupts = <86>; 672 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; 673 status = "disabled"; 674 }; 675 676 pwrcfg: power-config@40007000 { 677 compatible = "syscon"; 678 reg = <0x40007000 0x400>; 679 }; 680 681 ltdc: display-controller@40016800 { 682 compatible = "st,stm32-ltdc"; 683 reg = <0x40016800 0x200>; 684 interrupts = <88>, <89>; 685 resets = <&rcc STM32F4_APB2_RESET(LTDC)>; 686 clocks = <&rcc 1 CLK_LCD>; 687 clock-names = "lcd"; 688 status = "disabled"; 689 }; 690 691 crc: crc@40023000 { 692 compatible = "st,stm32f4-crc"; 693 reg = <0x40023000 0x400>; 694 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; 695 status = "disabled"; 696 }; 697 698 rcc: rcc@40023810 { 699 #reset-cells = <1>; 700 #clock-cells = <2>; 701 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; 702 reg = <0x40023800 0x400>; 703 clocks = <&clk_hse>, <&clk_i2s_ckin>; 704 st,syscfg = <&pwrcfg>; 705 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 706 assigned-clock-rates = <1000000>; 707 }; 708 709 dma1: dma-controller@40026000 { 710 compatible = "st,stm32-dma"; 711 reg = <0x40026000 0x400>; 712 interrupts = <11>, 713 <12>, 714 <13>, 715 <14>, 716 <15>, 717 <16>, 718 <17>, 719 <47>; 720 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; 721 #dma-cells = <4>; 722 }; 723 724 dma2: dma-controller@40026400 { 725 compatible = "st,stm32-dma"; 726 reg = <0x40026400 0x400>; 727 interrupts = <56>, 728 <57>, 729 <58>, 730 <59>, 731 <60>, 732 <68>, 733 <69>, 734 <70>; 735 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; 736 #dma-cells = <4>; 737 st,mem2mem; 738 }; 739 740 mac: ethernet@40028000 { 741 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; 742 reg = <0x40028000 0x8000>; 743 reg-names = "stmmaceth"; 744 interrupts = <61>; 745 interrupt-names = "macirq"; 746 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 747 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, 748 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, 749 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; 750 st,syscon = <&syscfg 0x4>; 751 snps,pbl = <8>; 752 snps,mixed-burst; 753 status = "disabled"; 754 }; 755 756 usbotg_hs: usb@40040000 { 757 compatible = "snps,dwc2"; 758 reg = <0x40040000 0x40000>; 759 interrupts = <77>; 760 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; 761 clock-names = "otg"; 762 status = "disabled"; 763 }; 764 765 usbotg_fs: usb@50000000 { 766 compatible = "st,stm32f4x9-fsotg"; 767 reg = <0x50000000 0x40000>; 768 interrupts = <67>; 769 clocks = <&rcc 0 39>; 770 clock-names = "otg"; 771 status = "disabled"; 772 }; 773 774 dcmi: dcmi@50050000 { 775 compatible = "st,stm32-dcmi"; 776 reg = <0x50050000 0x400>; 777 interrupts = <78>; 778 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; 779 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; 780 clock-names = "mclk"; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&dcmi_pins>; 783 dmas = <&dma2 1 1 0x414 0x3>; 784 dma-names = "tx"; 785 status = "disabled"; 786 }; 787 788 rng: rng@50060800 { 789 compatible = "st,stm32-rng"; 790 reg = <0x50060800 0x400>; 791 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; 792 793 }; 794 }; 795}; 796 797&systick { 798 clocks = <&rcc 1 SYSTICK>; 799 status = "okay"; 800}; 801