1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos5420 SoC device tree source 4 * 5 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Samsung Exynos5420 SoC device nodes are listed in this file. 9 * Exynos5420 based board files can include this file and provide 10 * values for board specfic bindings. 11 */ 12 13#include "exynos54xx.dtsi" 14#include <dt-bindings/clock/exynos5420.h> 15#include <dt-bindings/clock/exynos-audss-clk.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17 18/ { 19 compatible = "samsung,exynos5420", "samsung,exynos5"; 20 21 aliases { 22 mshc0 = &mmc_0; 23 mshc1 = &mmc_1; 24 mshc2 = &mmc_2; 25 pinctrl0 = &pinctrl_0; 26 pinctrl1 = &pinctrl_1; 27 pinctrl2 = &pinctrl_2; 28 pinctrl3 = &pinctrl_3; 29 pinctrl4 = &pinctrl_4; 30 i2c8 = &hsi2c_8; 31 i2c9 = &hsi2c_9; 32 i2c10 = &hsi2c_10; 33 gsc0 = &gsc_0; 34 gsc1 = &gsc_1; 35 spi0 = &spi_0; 36 spi1 = &spi_1; 37 spi2 = &spi_2; 38 }; 39 40 /* 41 * The 'cpus' node is not present here but instead it is provided 42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. 43 */ 44 45 cluster_a15_opp_table: opp_table0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-1800000000 { 50 opp-hz = /bits/ 64 <1800000000>; 51 opp-microvolt = <1250000 1250000 1500000>; 52 clock-latency-ns = <140000>; 53 }; 54 opp-1700000000 { 55 opp-hz = /bits/ 64 <1700000000>; 56 opp-microvolt = <1212500 1212500 1500000>; 57 clock-latency-ns = <140000>; 58 }; 59 opp-1600000000 { 60 opp-hz = /bits/ 64 <1600000000>; 61 opp-microvolt = <1175000 1175000 1500000>; 62 clock-latency-ns = <140000>; 63 }; 64 opp-1500000000 { 65 opp-hz = /bits/ 64 <1500000000>; 66 opp-microvolt = <1137500 1137500 1500000>; 67 clock-latency-ns = <140000>; 68 }; 69 opp-1400000000 { 70 opp-hz = /bits/ 64 <1400000000>; 71 opp-microvolt = <1112500 1112500 1500000>; 72 clock-latency-ns = <140000>; 73 }; 74 opp-1300000000 { 75 opp-hz = /bits/ 64 <1300000000>; 76 opp-microvolt = <1062500 1062500 1500000>; 77 clock-latency-ns = <140000>; 78 }; 79 opp-1200000000 { 80 opp-hz = /bits/ 64 <1200000000>; 81 opp-microvolt = <1037500 1037500 1500000>; 82 clock-latency-ns = <140000>; 83 }; 84 opp-1100000000 { 85 opp-hz = /bits/ 64 <1100000000>; 86 opp-microvolt = <1012500 1012500 1500000>; 87 clock-latency-ns = <140000>; 88 }; 89 opp-1000000000 { 90 opp-hz = /bits/ 64 <1000000000>; 91 opp-microvolt = < 987500 987500 1500000>; 92 clock-latency-ns = <140000>; 93 }; 94 opp-900000000 { 95 opp-hz = /bits/ 64 <900000000>; 96 opp-microvolt = < 962500 962500 1500000>; 97 clock-latency-ns = <140000>; 98 }; 99 opp-800000000 { 100 opp-hz = /bits/ 64 <800000000>; 101 opp-microvolt = < 937500 937500 1500000>; 102 clock-latency-ns = <140000>; 103 }; 104 opp-700000000 { 105 opp-hz = /bits/ 64 <700000000>; 106 opp-microvolt = < 912500 912500 1500000>; 107 clock-latency-ns = <140000>; 108 }; 109 }; 110 111 cluster_a7_opp_table: opp_table1 { 112 compatible = "operating-points-v2"; 113 opp-shared; 114 115 opp-1300000000 { 116 opp-hz = /bits/ 64 <1300000000>; 117 opp-microvolt = <1275000>; 118 clock-latency-ns = <140000>; 119 }; 120 opp-1200000000 { 121 opp-hz = /bits/ 64 <1200000000>; 122 opp-microvolt = <1212500>; 123 clock-latency-ns = <140000>; 124 }; 125 opp-1100000000 { 126 opp-hz = /bits/ 64 <1100000000>; 127 opp-microvolt = <1162500>; 128 clock-latency-ns = <140000>; 129 }; 130 opp-1000000000 { 131 opp-hz = /bits/ 64 <1000000000>; 132 opp-microvolt = <1112500>; 133 clock-latency-ns = <140000>; 134 }; 135 opp-900000000 { 136 opp-hz = /bits/ 64 <900000000>; 137 opp-microvolt = <1062500>; 138 clock-latency-ns = <140000>; 139 }; 140 opp-800000000 { 141 opp-hz = /bits/ 64 <800000000>; 142 opp-microvolt = <1025000>; 143 clock-latency-ns = <140000>; 144 }; 145 opp-700000000 { 146 opp-hz = /bits/ 64 <700000000>; 147 opp-microvolt = <975000>; 148 clock-latency-ns = <140000>; 149 }; 150 opp-600000000 { 151 opp-hz = /bits/ 64 <600000000>; 152 opp-microvolt = <937500>; 153 clock-latency-ns = <140000>; 154 }; 155 }; 156 157 soc: soc { 158 cci: cci@10d20000 { 159 compatible = "arm,cci-400"; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 reg = <0x10d20000 0x1000>; 163 ranges = <0x0 0x10d20000 0x6000>; 164 165 cci_control0: slave-if@4000 { 166 compatible = "arm,cci-400-ctrl-if"; 167 interface-type = "ace"; 168 reg = <0x4000 0x1000>; 169 }; 170 cci_control1: slave-if@5000 { 171 compatible = "arm,cci-400-ctrl-if"; 172 interface-type = "ace"; 173 reg = <0x5000 0x1000>; 174 }; 175 }; 176 177 clock: clock-controller@10010000 { 178 compatible = "samsung,exynos5420-clock", "syscon"; 179 reg = <0x10010000 0x30000>; 180 #clock-cells = <1>; 181 }; 182 183 clock_audss: audss-clock-controller@3810000 { 184 compatible = "samsung,exynos5420-audss-clock"; 185 reg = <0x03810000 0x0C>; 186 #clock-cells = <1>; 187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, 188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; 189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 190 power-domains = <&mau_pd>; 191 }; 192 193 mfc: codec@11000000 { 194 compatible = "samsung,mfc-v7"; 195 reg = <0x11000000 0x10000>; 196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clock CLK_MFC>; 198 clock-names = "mfc"; 199 power-domains = <&mfc_pd>; 200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 201 iommu-names = "left", "right"; 202 }; 203 204 mmc_0: mmc@12200000 { 205 compatible = "samsung,exynos5420-dw-mshc-smu"; 206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 reg = <0x12200000 0x2000>; 210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; 211 clock-names = "biu", "ciu"; 212 fifo-depth = <0x40>; 213 status = "disabled"; 214 }; 215 216 mmc_1: mmc@12210000 { 217 compatible = "samsung,exynos5420-dw-mshc-smu"; 218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 reg = <0x12210000 0x2000>; 222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; 223 clock-names = "biu", "ciu"; 224 fifo-depth = <0x40>; 225 status = "disabled"; 226 }; 227 228 mmc_2: mmc@12220000 { 229 compatible = "samsung,exynos5420-dw-mshc"; 230 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 reg = <0x12220000 0x1000>; 234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; 235 clock-names = "biu", "ciu"; 236 fifo-depth = <0x40>; 237 status = "disabled"; 238 }; 239 240 dmc: memory-controller@10c20000 { 241 compatible = "samsung,exynos5422-dmc"; 242 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; 243 interrupt-parent = <&combiner>; 244 interrupts = <16 0>, <16 1>; 245 interrupt-names = "drex_0", "drex_1"; 246 clocks = <&clock CLK_FOUT_SPLL>, 247 <&clock CLK_MOUT_SCLK_SPLL>, 248 <&clock CLK_FF_DOUT_SPLL2>, 249 <&clock CLK_FOUT_BPLL>, 250 <&clock CLK_MOUT_BPLL>, 251 <&clock CLK_SCLK_BPLL>, 252 <&clock CLK_MOUT_MX_MSPLL_CCORE>, 253 <&clock CLK_MOUT_MCLK_CDREX>; 254 clock-names = "fout_spll", 255 "mout_sclk_spll", 256 "ff_dout_spll2", 257 "fout_bpll", 258 "mout_bpll", 259 "sclk_bpll", 260 "mout_mx_mspll_ccore", 261 "mout_mclk_cdrex"; 262 samsung,syscon-clk = <&clock>; 263 status = "disabled"; 264 }; 265 266 nocp_mem0_0: nocp@10ca1000 { 267 compatible = "samsung,exynos5420-nocp"; 268 reg = <0x10CA1000 0x200>; 269 status = "disabled"; 270 }; 271 272 nocp_mem0_1: nocp@10ca1400 { 273 compatible = "samsung,exynos5420-nocp"; 274 reg = <0x10CA1400 0x200>; 275 status = "disabled"; 276 }; 277 278 nocp_mem1_0: nocp@10ca1800 { 279 compatible = "samsung,exynos5420-nocp"; 280 reg = <0x10CA1800 0x200>; 281 status = "disabled"; 282 }; 283 284 nocp_mem1_1: nocp@10ca1c00 { 285 compatible = "samsung,exynos5420-nocp"; 286 reg = <0x10CA1C00 0x200>; 287 status = "disabled"; 288 }; 289 290 nocp_g3d_0: nocp@11a51000 { 291 compatible = "samsung,exynos5420-nocp"; 292 reg = <0x11A51000 0x200>; 293 status = "disabled"; 294 }; 295 296 nocp_g3d_1: nocp@11a51400 { 297 compatible = "samsung,exynos5420-nocp"; 298 reg = <0x11A51400 0x200>; 299 status = "disabled"; 300 }; 301 302 ppmu_dmc0_0: ppmu@10d00000 { 303 compatible = "samsung,exynos-ppmu"; 304 reg = <0x10d00000 0x2000>; 305 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; 306 clock-names = "ppmu"; 307 events { 308 ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { 309 event-name = "ppmu-event3-dmc0_0"; 310 }; 311 }; 312 }; 313 314 ppmu_dmc0_1: ppmu@10d10000 { 315 compatible = "samsung,exynos-ppmu"; 316 reg = <0x10d10000 0x2000>; 317 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; 318 clock-names = "ppmu"; 319 events { 320 ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { 321 event-name = "ppmu-event3-dmc0_1"; 322 }; 323 }; 324 }; 325 326 ppmu_dmc1_0: ppmu@10d60000 { 327 compatible = "samsung,exynos-ppmu"; 328 reg = <0x10d60000 0x2000>; 329 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; 330 clock-names = "ppmu"; 331 events { 332 ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { 333 event-name = "ppmu-event3-dmc1_0"; 334 }; 335 }; 336 }; 337 338 ppmu_dmc1_1: ppmu@10d70000 { 339 compatible = "samsung,exynos-ppmu"; 340 reg = <0x10d70000 0x2000>; 341 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; 342 clock-names = "ppmu"; 343 events { 344 ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { 345 event-name = "ppmu-event3-dmc1_1"; 346 }; 347 }; 348 }; 349 350 gsc_pd: power-domain@10044000 { 351 compatible = "samsung,exynos4210-pd"; 352 reg = <0x10044000 0x20>; 353 #power-domain-cells = <0>; 354 label = "GSC"; 355 }; 356 357 isp_pd: power-domain@10044020 { 358 compatible = "samsung,exynos4210-pd"; 359 reg = <0x10044020 0x20>; 360 #power-domain-cells = <0>; 361 label = "ISP"; 362 }; 363 364 mfc_pd: power-domain@10044060 { 365 compatible = "samsung,exynos4210-pd"; 366 reg = <0x10044060 0x20>; 367 #power-domain-cells = <0>; 368 label = "MFC"; 369 }; 370 371 g3d_pd: power-domain@10044080 { 372 compatible = "samsung,exynos4210-pd"; 373 reg = <0x10044080 0x20>; 374 #power-domain-cells = <0>; 375 label = "G3D"; 376 }; 377 378 disp_pd: power-domain@100440c0 { 379 compatible = "samsung,exynos4210-pd"; 380 reg = <0x100440C0 0x20>; 381 #power-domain-cells = <0>; 382 label = "DISP"; 383 }; 384 385 mau_pd: power-domain@100440e0 { 386 compatible = "samsung,exynos4210-pd"; 387 reg = <0x100440E0 0x20>; 388 #power-domain-cells = <0>; 389 label = "MAU"; 390 }; 391 392 msc_pd: power-domain@10044120 { 393 compatible = "samsung,exynos4210-pd"; 394 reg = <0x10044120 0x20>; 395 #power-domain-cells = <0>; 396 label = "MSC"; 397 }; 398 399 pinctrl_0: pinctrl@13400000 { 400 compatible = "samsung,exynos5420-pinctrl"; 401 reg = <0x13400000 0x1000>; 402 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 403 404 wakeup-interrupt-controller { 405 compatible = "samsung,exynos4210-wakeup-eint"; 406 interrupt-parent = <&gic>; 407 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 408 }; 409 }; 410 411 pinctrl_1: pinctrl@13410000 { 412 compatible = "samsung,exynos5420-pinctrl"; 413 reg = <0x13410000 0x1000>; 414 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 415 }; 416 417 pinctrl_2: pinctrl@14000000 { 418 compatible = "samsung,exynos5420-pinctrl"; 419 reg = <0x14000000 0x1000>; 420 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 421 }; 422 423 pinctrl_3: pinctrl@14010000 { 424 compatible = "samsung,exynos5420-pinctrl"; 425 reg = <0x14010000 0x1000>; 426 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 427 }; 428 429 pinctrl_4: pinctrl@3860000 { 430 compatible = "samsung,exynos5420-pinctrl"; 431 reg = <0x03860000 0x1000>; 432 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 433 power-domains = <&mau_pd>; 434 }; 435 436 amba { 437 #address-cells = <1>; 438 #size-cells = <1>; 439 compatible = "simple-bus"; 440 interrupt-parent = <&gic>; 441 ranges; 442 443 adma: adma@3880000 { 444 compatible = "arm,pl330", "arm,primecell"; 445 reg = <0x03880000 0x1000>; 446 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&clock_audss EXYNOS_ADMA>; 448 clock-names = "apb_pclk"; 449 #dma-cells = <1>; 450 #dma-channels = <6>; 451 #dma-requests = <16>; 452 power-domains = <&mau_pd>; 453 }; 454 455 pdma0: pdma@121a0000 { 456 compatible = "arm,pl330", "arm,primecell"; 457 reg = <0x121A0000 0x1000>; 458 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clock CLK_PDMA0>; 460 clock-names = "apb_pclk"; 461 #dma-cells = <1>; 462 #dma-channels = <8>; 463 #dma-requests = <32>; 464 }; 465 466 pdma1: pdma@121b0000 { 467 compatible = "arm,pl330", "arm,primecell"; 468 reg = <0x121B0000 0x1000>; 469 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clock CLK_PDMA1>; 471 clock-names = "apb_pclk"; 472 #dma-cells = <1>; 473 #dma-channels = <8>; 474 #dma-requests = <32>; 475 }; 476 477 mdma0: mdma@10800000 { 478 compatible = "arm,pl330", "arm,primecell"; 479 reg = <0x10800000 0x1000>; 480 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clock CLK_MDMA0>; 482 clock-names = "apb_pclk"; 483 #dma-cells = <1>; 484 #dma-channels = <8>; 485 #dma-requests = <1>; 486 }; 487 488 mdma1: mdma@11c10000 { 489 compatible = "arm,pl330", "arm,primecell"; 490 reg = <0x11C10000 0x1000>; 491 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clock CLK_MDMA1>; 493 clock-names = "apb_pclk"; 494 #dma-cells = <1>; 495 #dma-channels = <8>; 496 #dma-requests = <1>; 497 /* 498 * MDMA1 can support both secure and non-secure 499 * AXI transactions. When this is enabled in 500 * the kernel for boards that run in secure 501 * mode, we are getting imprecise external 502 * aborts causing the kernel to oops. 503 */ 504 status = "disabled"; 505 }; 506 }; 507 508 i2s0: i2s@3830000 { 509 compatible = "samsung,exynos5420-i2s"; 510 reg = <0x03830000 0x100>; 511 dmas = <&adma 0>, 512 <&adma 2>, 513 <&adma 1>; 514 dma-names = "tx", "rx", "tx-sec"; 515 clocks = <&clock_audss EXYNOS_I2S_BUS>, 516 <&clock_audss EXYNOS_I2S_BUS>, 517 <&clock_audss EXYNOS_SCLK_I2S>; 518 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 519 #clock-cells = <1>; 520 clock-output-names = "i2s_cdclk0"; 521 #sound-dai-cells = <1>; 522 samsung,idma-addr = <0x03000000>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&i2s0_bus>; 525 power-domains = <&mau_pd>; 526 status = "disabled"; 527 }; 528 529 i2s1: i2s@12d60000 { 530 compatible = "samsung,exynos5420-i2s"; 531 reg = <0x12D60000 0x100>; 532 dmas = <&pdma1 12>, 533 <&pdma1 11>; 534 dma-names = "tx", "rx"; 535 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; 536 clock-names = "iis", "i2s_opclk0"; 537 #clock-cells = <1>; 538 clock-output-names = "i2s_cdclk1"; 539 #sound-dai-cells = <1>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&i2s1_bus>; 542 status = "disabled"; 543 }; 544 545 i2s2: i2s@12d70000 { 546 compatible = "samsung,exynos5420-i2s"; 547 reg = <0x12D70000 0x100>; 548 dmas = <&pdma0 12>, 549 <&pdma0 11>; 550 dma-names = "tx", "rx"; 551 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; 552 clock-names = "iis", "i2s_opclk0"; 553 #clock-cells = <1>; 554 clock-output-names = "i2s_cdclk2"; 555 #sound-dai-cells = <1>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&i2s2_bus>; 558 status = "disabled"; 559 }; 560 561 spi_0: spi@12d20000 { 562 compatible = "samsung,exynos4210-spi"; 563 reg = <0x12d20000 0x100>; 564 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 565 dmas = <&pdma0 5 566 &pdma0 4>; 567 dma-names = "tx", "rx"; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&spi0_bus>; 572 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 573 clock-names = "spi", "spi_busclk0"; 574 status = "disabled"; 575 }; 576 577 spi_1: spi@12d30000 { 578 compatible = "samsung,exynos4210-spi"; 579 reg = <0x12d30000 0x100>; 580 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 581 dmas = <&pdma1 5 582 &pdma1 4>; 583 dma-names = "tx", "rx"; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&spi1_bus>; 588 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 589 clock-names = "spi", "spi_busclk0"; 590 status = "disabled"; 591 }; 592 593 spi_2: spi@12d40000 { 594 compatible = "samsung,exynos4210-spi"; 595 reg = <0x12d40000 0x100>; 596 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 597 dmas = <&pdma0 7 598 &pdma0 6>; 599 dma-names = "tx", "rx"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&spi2_bus>; 604 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 605 clock-names = "spi", "spi_busclk0"; 606 status = "disabled"; 607 }; 608 609 dp_phy: dp-video-phy { 610 compatible = "samsung,exynos5420-dp-video-phy"; 611 samsung,pmu-syscon = <&pmu_system_controller>; 612 #phy-cells = <0>; 613 }; 614 615 mipi_phy: mipi-video-phy { 616 compatible = "samsung,s5pv210-mipi-video-phy"; 617 syscon = <&pmu_system_controller>; 618 #phy-cells = <1>; 619 }; 620 621 dsi@14500000 { 622 compatible = "samsung,exynos5410-mipi-dsi"; 623 reg = <0x14500000 0x10000>; 624 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 625 phys = <&mipi_phy 1>; 626 phy-names = "dsim"; 627 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; 628 clock-names = "bus_clk", "pll_clk"; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 status = "disabled"; 632 }; 633 634 hsi2c_8: i2c@12e00000 { 635 compatible = "samsung,exynos5250-hsi2c"; 636 reg = <0x12E00000 0x1000>; 637 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&i2c8_hs_bus>; 642 clocks = <&clock CLK_USI4>; 643 clock-names = "hsi2c"; 644 status = "disabled"; 645 }; 646 647 hsi2c_9: i2c@12e10000 { 648 compatible = "samsung,exynos5250-hsi2c"; 649 reg = <0x12E10000 0x1000>; 650 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&i2c9_hs_bus>; 655 clocks = <&clock CLK_USI5>; 656 clock-names = "hsi2c"; 657 status = "disabled"; 658 }; 659 660 hsi2c_10: i2c@12e20000 { 661 compatible = "samsung,exynos5250-hsi2c"; 662 reg = <0x12E20000 0x1000>; 663 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&i2c10_hs_bus>; 668 clocks = <&clock CLK_USI6>; 669 clock-names = "hsi2c"; 670 status = "disabled"; 671 }; 672 673 hdmi: hdmi@14530000 { 674 compatible = "samsung,exynos5420-hdmi"; 675 reg = <0x14530000 0x70000>; 676 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 678 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 679 <&clock CLK_MOUT_HDMI>; 680 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 681 "sclk_hdmiphy", "mout_hdmi"; 682 phy = <&hdmiphy>; 683 samsung,syscon-phandle = <&pmu_system_controller>; 684 status = "disabled"; 685 power-domains = <&disp_pd>; 686 #sound-dai-cells = <0>; 687 }; 688 689 hdmiphy: hdmiphy@145d0000 { 690 reg = <0x145D0000 0x20>; 691 }; 692 693 hdmicec: cec@101b0000 { 694 compatible = "samsung,s5p-cec"; 695 reg = <0x101B0000 0x200>; 696 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clock CLK_HDMI_CEC>; 698 clock-names = "hdmicec"; 699 samsung,syscon-phandle = <&pmu_system_controller>; 700 hdmi-phandle = <&hdmi>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&hdmi_cec>; 703 status = "disabled"; 704 }; 705 706 mixer: mixer@14450000 { 707 compatible = "samsung,exynos5420-mixer"; 708 reg = <0x14450000 0x10000>; 709 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 711 <&clock CLK_SCLK_HDMI>; 712 clock-names = "mixer", "hdmi", "sclk_hdmi"; 713 power-domains = <&disp_pd>; 714 iommus = <&sysmmu_tv>; 715 status = "disabled"; 716 }; 717 718 rotator: rotator@11c00000 { 719 compatible = "samsung,exynos5250-rotator"; 720 reg = <0x11C00000 0x64>; 721 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&clock CLK_ROTATOR>; 723 clock-names = "rotator"; 724 iommus = <&sysmmu_rotator>; 725 }; 726 727 gsc_0: video-scaler@13e00000 { 728 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; 729 reg = <0x13e00000 0x1000>; 730 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&clock CLK_GSCL0>; 732 clock-names = "gscl"; 733 power-domains = <&gsc_pd>; 734 iommus = <&sysmmu_gscl0>; 735 }; 736 737 gsc_1: video-scaler@13e10000 { 738 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc"; 739 reg = <0x13e10000 0x1000>; 740 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&clock CLK_GSCL1>; 742 clock-names = "gscl"; 743 power-domains = <&gsc_pd>; 744 iommus = <&sysmmu_gscl1>; 745 }; 746 747 gpu: gpu@11800000 { 748 compatible = "samsung,exynos5420-mali", "arm,mali-t628"; 749 reg = <0x11800000 0x5000>; 750 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 753 interrupt-names = "job", "mmu", "gpu"; 754 755 clocks = <&clock CLK_G3D>; 756 clock-names = "core"; 757 power-domains = <&g3d_pd>; 758 operating-points-v2 = <&gpu_opp_table>; 759 760 status = "disabled"; 761 #cooling-cells = <2>; 762 763 gpu_opp_table: opp-table { 764 compatible = "operating-points-v2"; 765 766 opp-177000000 { 767 opp-hz = /bits/ 64 <177000000>; 768 opp-microvolt = <812500>; 769 }; 770 opp-266000000 { 771 opp-hz = /bits/ 64 <266000000>; 772 opp-microvolt = <862500>; 773 }; 774 opp-350000000 { 775 opp-hz = /bits/ 64 <350000000>; 776 opp-microvolt = <912500>; 777 }; 778 opp-420000000 { 779 opp-hz = /bits/ 64 <420000000>; 780 opp-microvolt = <962500>; 781 }; 782 opp-480000000 { 783 opp-hz = /bits/ 64 <480000000>; 784 opp-microvolt = <1000000>; 785 }; 786 opp-543000000 { 787 opp-hz = /bits/ 64 <543000000>; 788 opp-microvolt = <1037500>; 789 }; 790 opp-600000000 { 791 opp-hz = /bits/ 64 <600000000>; 792 opp-microvolt = <1150000>; 793 }; 794 }; 795 }; 796 797 scaler_0: scaler@12800000 { 798 compatible = "samsung,exynos5420-scaler"; 799 reg = <0x12800000 0x1294>; 800 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&clock CLK_MSCL0>; 802 clock-names = "mscl"; 803 power-domains = <&msc_pd>; 804 iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; 805 }; 806 807 scaler_1: scaler@12810000 { 808 compatible = "samsung,exynos5420-scaler"; 809 reg = <0x12810000 0x1294>; 810 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&clock CLK_MSCL1>; 812 clock-names = "mscl"; 813 power-domains = <&msc_pd>; 814 iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; 815 }; 816 817 scaler_2: scaler@12820000 { 818 compatible = "samsung,exynos5420-scaler"; 819 reg = <0x12820000 0x1294>; 820 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&clock CLK_MSCL2>; 822 clock-names = "mscl"; 823 power-domains = <&msc_pd>; 824 iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; 825 }; 826 827 jpeg_0: jpeg@11f50000 { 828 compatible = "samsung,exynos5420-jpeg"; 829 reg = <0x11F50000 0x1000>; 830 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 831 clock-names = "jpeg"; 832 clocks = <&clock CLK_JPEG>; 833 iommus = <&sysmmu_jpeg0>; 834 }; 835 836 jpeg_1: jpeg@11f60000 { 837 compatible = "samsung,exynos5420-jpeg"; 838 reg = <0x11F60000 0x1000>; 839 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 840 clock-names = "jpeg"; 841 clocks = <&clock CLK_JPEG2>; 842 iommus = <&sysmmu_jpeg1>; 843 }; 844 845 pmu_system_controller: system-controller@10040000 { 846 compatible = "samsung,exynos5420-pmu", "syscon"; 847 reg = <0x10040000 0x5000>; 848 clock-names = "clkout16"; 849 clocks = <&clock CLK_FIN_PLL>; 850 #clock-cells = <1>; 851 interrupt-controller; 852 #interrupt-cells = <3>; 853 interrupt-parent = <&gic>; 854 }; 855 856 tmu_cpu0: tmu@10060000 { 857 compatible = "samsung,exynos5420-tmu"; 858 reg = <0x10060000 0x100>; 859 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&clock CLK_TMU>; 861 clock-names = "tmu_apbif"; 862 #thermal-sensor-cells = <0>; 863 }; 864 865 tmu_cpu1: tmu@10064000 { 866 compatible = "samsung,exynos5420-tmu"; 867 reg = <0x10064000 0x100>; 868 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&clock CLK_TMU>; 870 clock-names = "tmu_apbif"; 871 #thermal-sensor-cells = <0>; 872 }; 873 874 tmu_cpu2: tmu@10068000 { 875 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 876 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 877 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 879 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 880 #thermal-sensor-cells = <0>; 881 }; 882 883 tmu_cpu3: tmu@1006c000 { 884 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 885 reg = <0x1006c000 0x100>, <0x100a0000 0x4>; 886 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 888 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 889 #thermal-sensor-cells = <0>; 890 }; 891 892 tmu_gpu: tmu@100a0000 { 893 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 894 reg = <0x100a0000 0x100>, <0x10068000 0x4>; 895 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 897 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 898 #thermal-sensor-cells = <0>; 899 }; 900 901 sysmmu_g2dr: sysmmu@10a60000 { 902 compatible = "samsung,exynos-sysmmu"; 903 reg = <0x10A60000 0x1000>; 904 interrupt-parent = <&combiner>; 905 interrupts = <24 5>; 906 clock-names = "sysmmu", "master"; 907 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 908 #iommu-cells = <0>; 909 }; 910 911 sysmmu_g2dw: sysmmu@10a70000 { 912 compatible = "samsung,exynos-sysmmu"; 913 reg = <0x10A70000 0x1000>; 914 interrupt-parent = <&combiner>; 915 interrupts = <22 2>; 916 clock-names = "sysmmu", "master"; 917 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 918 #iommu-cells = <0>; 919 }; 920 921 sysmmu_tv: sysmmu@14650000 { 922 compatible = "samsung,exynos-sysmmu"; 923 reg = <0x14650000 0x1000>; 924 interrupt-parent = <&combiner>; 925 interrupts = <7 4>; 926 clock-names = "sysmmu", "master"; 927 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; 928 power-domains = <&disp_pd>; 929 #iommu-cells = <0>; 930 }; 931 932 sysmmu_gscl0: sysmmu@13e80000 { 933 compatible = "samsung,exynos-sysmmu"; 934 reg = <0x13E80000 0x1000>; 935 interrupt-parent = <&combiner>; 936 interrupts = <2 0>; 937 clock-names = "sysmmu", "master"; 938 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 939 power-domains = <&gsc_pd>; 940 #iommu-cells = <0>; 941 }; 942 943 sysmmu_gscl1: sysmmu@13e90000 { 944 compatible = "samsung,exynos-sysmmu"; 945 reg = <0x13E90000 0x1000>; 946 interrupt-parent = <&combiner>; 947 interrupts = <2 2>; 948 clock-names = "sysmmu", "master"; 949 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 950 power-domains = <&gsc_pd>; 951 #iommu-cells = <0>; 952 }; 953 954 sysmmu_scaler0r: sysmmu@12880000 { 955 compatible = "samsung,exynos-sysmmu"; 956 reg = <0x12880000 0x1000>; 957 interrupt-parent = <&combiner>; 958 interrupts = <22 4>; 959 clock-names = "sysmmu", "master"; 960 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 961 power-domains = <&msc_pd>; 962 #iommu-cells = <0>; 963 }; 964 965 sysmmu_scaler1r: sysmmu@12890000 { 966 compatible = "samsung,exynos-sysmmu"; 967 reg = <0x12890000 0x1000>; 968 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 969 clock-names = "sysmmu", "master"; 970 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 971 power-domains = <&msc_pd>; 972 #iommu-cells = <0>; 973 }; 974 975 sysmmu_scaler2r: sysmmu@128a0000 { 976 compatible = "samsung,exynos-sysmmu"; 977 reg = <0x128A0000 0x1000>; 978 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 979 clock-names = "sysmmu", "master"; 980 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 981 power-domains = <&msc_pd>; 982 #iommu-cells = <0>; 983 }; 984 985 sysmmu_scaler0w: sysmmu@128c0000 { 986 compatible = "samsung,exynos-sysmmu"; 987 reg = <0x128C0000 0x1000>; 988 interrupt-parent = <&combiner>; 989 interrupts = <27 2>; 990 clock-names = "sysmmu", "master"; 991 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 992 power-domains = <&msc_pd>; 993 #iommu-cells = <0>; 994 }; 995 996 sysmmu_scaler1w: sysmmu@128d0000 { 997 compatible = "samsung,exynos-sysmmu"; 998 reg = <0x128D0000 0x1000>; 999 interrupt-parent = <&combiner>; 1000 interrupts = <22 6>; 1001 clock-names = "sysmmu", "master"; 1002 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 1003 power-domains = <&msc_pd>; 1004 #iommu-cells = <0>; 1005 }; 1006 1007 sysmmu_scaler2w: sysmmu@128e0000 { 1008 compatible = "samsung,exynos-sysmmu"; 1009 reg = <0x128E0000 0x1000>; 1010 interrupt-parent = <&combiner>; 1011 interrupts = <19 6>; 1012 clock-names = "sysmmu", "master"; 1013 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 1014 power-domains = <&msc_pd>; 1015 #iommu-cells = <0>; 1016 }; 1017 1018 sysmmu_rotator: sysmmu@11d40000 { 1019 compatible = "samsung,exynos-sysmmu"; 1020 reg = <0x11D40000 0x1000>; 1021 interrupt-parent = <&combiner>; 1022 interrupts = <4 0>; 1023 clock-names = "sysmmu", "master"; 1024 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 1025 #iommu-cells = <0>; 1026 }; 1027 1028 sysmmu_jpeg0: sysmmu@11f10000 { 1029 compatible = "samsung,exynos-sysmmu"; 1030 reg = <0x11F10000 0x1000>; 1031 interrupt-parent = <&combiner>; 1032 interrupts = <4 2>; 1033 clock-names = "sysmmu", "master"; 1034 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 1035 #iommu-cells = <0>; 1036 }; 1037 1038 sysmmu_jpeg1: sysmmu@11f20000 { 1039 compatible = "samsung,exynos-sysmmu"; 1040 reg = <0x11F20000 0x1000>; 1041 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1042 clock-names = "sysmmu", "master"; 1043 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; 1044 #iommu-cells = <0>; 1045 }; 1046 1047 sysmmu_mfc_l: sysmmu@11200000 { 1048 compatible = "samsung,exynos-sysmmu"; 1049 reg = <0x11200000 0x1000>; 1050 interrupt-parent = <&combiner>; 1051 interrupts = <6 2>; 1052 clock-names = "sysmmu", "master"; 1053 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 1054 power-domains = <&mfc_pd>; 1055 #iommu-cells = <0>; 1056 }; 1057 1058 sysmmu_mfc_r: sysmmu@11210000 { 1059 compatible = "samsung,exynos-sysmmu"; 1060 reg = <0x11210000 0x1000>; 1061 interrupt-parent = <&combiner>; 1062 interrupts = <8 5>; 1063 clock-names = "sysmmu", "master"; 1064 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 1065 power-domains = <&mfc_pd>; 1066 #iommu-cells = <0>; 1067 }; 1068 1069 sysmmu_fimd1_0: sysmmu@14640000 { 1070 compatible = "samsung,exynos-sysmmu"; 1071 reg = <0x14640000 0x1000>; 1072 interrupt-parent = <&combiner>; 1073 interrupts = <3 2>; 1074 clock-names = "sysmmu", "master"; 1075 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; 1076 power-domains = <&disp_pd>; 1077 #iommu-cells = <0>; 1078 }; 1079 1080 sysmmu_fimd1_1: sysmmu@14680000 { 1081 compatible = "samsung,exynos-sysmmu"; 1082 reg = <0x14680000 0x1000>; 1083 interrupt-parent = <&combiner>; 1084 interrupts = <3 0>; 1085 clock-names = "sysmmu", "master"; 1086 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; 1087 power-domains = <&disp_pd>; 1088 #iommu-cells = <0>; 1089 }; 1090 1091 bus_wcore: bus_wcore { 1092 compatible = "samsung,exynos-bus"; 1093 clocks = <&clock CLK_DOUT_ACLK400_WCORE>; 1094 clock-names = "bus"; 1095 status = "disabled"; 1096 }; 1097 1098 bus_noc: bus_noc { 1099 compatible = "samsung,exynos-bus"; 1100 clocks = <&clock CLK_DOUT_ACLK100_NOC>; 1101 clock-names = "bus"; 1102 status = "disabled"; 1103 }; 1104 1105 bus_fsys_apb: bus_fsys_apb { 1106 compatible = "samsung,exynos-bus"; 1107 clocks = <&clock CLK_DOUT_PCLK200_FSYS>; 1108 clock-names = "bus"; 1109 status = "disabled"; 1110 }; 1111 1112 bus_fsys: bus_fsys { 1113 compatible = "samsung,exynos-bus"; 1114 clocks = <&clock CLK_DOUT_ACLK200_FSYS>; 1115 clock-names = "bus"; 1116 status = "disabled"; 1117 }; 1118 1119 bus_fsys2: bus_fsys2 { 1120 compatible = "samsung,exynos-bus"; 1121 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; 1122 clock-names = "bus"; 1123 status = "disabled"; 1124 }; 1125 1126 bus_mfc: bus_mfc { 1127 compatible = "samsung,exynos-bus"; 1128 clocks = <&clock CLK_DOUT_ACLK333>; 1129 clock-names = "bus"; 1130 status = "disabled"; 1131 }; 1132 1133 bus_gen: bus_gen { 1134 compatible = "samsung,exynos-bus"; 1135 clocks = <&clock CLK_DOUT_ACLK266>; 1136 clock-names = "bus"; 1137 status = "disabled"; 1138 }; 1139 1140 bus_peri: bus_peri { 1141 compatible = "samsung,exynos-bus"; 1142 clocks = <&clock CLK_DOUT_ACLK66>; 1143 clock-names = "bus"; 1144 status = "disabled"; 1145 }; 1146 1147 bus_g2d: bus_g2d { 1148 compatible = "samsung,exynos-bus"; 1149 clocks = <&clock CLK_DOUT_ACLK333_G2D>; 1150 clock-names = "bus"; 1151 status = "disabled"; 1152 }; 1153 1154 bus_g2d_acp: bus_g2d_acp { 1155 compatible = "samsung,exynos-bus"; 1156 clocks = <&clock CLK_DOUT_ACLK266_G2D>; 1157 clock-names = "bus"; 1158 status = "disabled"; 1159 }; 1160 1161 bus_jpeg: bus_jpeg { 1162 compatible = "samsung,exynos-bus"; 1163 clocks = <&clock CLK_DOUT_ACLK300_JPEG>; 1164 clock-names = "bus"; 1165 status = "disabled"; 1166 }; 1167 1168 bus_jpeg_apb: bus_jpeg_apb { 1169 compatible = "samsung,exynos-bus"; 1170 clocks = <&clock CLK_DOUT_ACLK166>; 1171 clock-names = "bus"; 1172 status = "disabled"; 1173 }; 1174 1175 bus_disp1_fimd: bus_disp1_fimd { 1176 compatible = "samsung,exynos-bus"; 1177 clocks = <&clock CLK_DOUT_ACLK300_DISP1>; 1178 clock-names = "bus"; 1179 status = "disabled"; 1180 }; 1181 1182 bus_disp1: bus_disp1 { 1183 compatible = "samsung,exynos-bus"; 1184 clocks = <&clock CLK_DOUT_ACLK400_DISP1>; 1185 clock-names = "bus"; 1186 status = "disabled"; 1187 }; 1188 1189 bus_gscl_scaler: bus_gscl_scaler { 1190 compatible = "samsung,exynos-bus"; 1191 clocks = <&clock CLK_DOUT_ACLK300_GSCL>; 1192 clock-names = "bus"; 1193 status = "disabled"; 1194 }; 1195 1196 bus_mscl: bus_mscl { 1197 compatible = "samsung,exynos-bus"; 1198 clocks = <&clock CLK_DOUT_ACLK400_MSCL>; 1199 clock-names = "bus"; 1200 status = "disabled"; 1201 }; 1202 }; 1203 1204 thermal-zones { 1205 cpu0_thermal: cpu0-thermal { 1206 thermal-sensors = <&tmu_cpu0>; 1207 #include "exynos5420-trip-points.dtsi" 1208 }; 1209 cpu1_thermal: cpu1-thermal { 1210 thermal-sensors = <&tmu_cpu1>; 1211 #include "exynos5420-trip-points.dtsi" 1212 }; 1213 cpu2_thermal: cpu2-thermal { 1214 thermal-sensors = <&tmu_cpu2>; 1215 #include "exynos5420-trip-points.dtsi" 1216 }; 1217 cpu3_thermal: cpu3-thermal { 1218 thermal-sensors = <&tmu_cpu3>; 1219 #include "exynos5420-trip-points.dtsi" 1220 }; 1221 gpu_thermal: gpu-thermal { 1222 thermal-sensors = <&tmu_gpu>; 1223 #include "exynos5420-trip-points.dtsi" 1224 }; 1225 }; 1226}; 1227 1228&adc { 1229 clocks = <&clock CLK_TSADC>; 1230 clock-names = "adc"; 1231 samsung,syscon-phandle = <&pmu_system_controller>; 1232}; 1233 1234&dp { 1235 clocks = <&clock CLK_DP1>; 1236 clock-names = "dp"; 1237 phys = <&dp_phy>; 1238 phy-names = "dp"; 1239 power-domains = <&disp_pd>; 1240}; 1241 1242&fimd { 1243 compatible = "samsung,exynos5420-fimd"; 1244 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1245 clock-names = "sclk_fimd", "fimd"; 1246 power-domains = <&disp_pd>; 1247 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; 1248 iommu-names = "m0", "m1"; 1249}; 1250 1251&g2d { 1252 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>; 1253 clocks = <&clock CLK_G2D>; 1254 clock-names = "fimg2d"; 1255 status = "okay"; 1256}; 1257 1258&i2c_0 { 1259 clocks = <&clock CLK_I2C0>; 1260 clock-names = "i2c"; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&i2c0_bus>; 1263}; 1264 1265&i2c_1 { 1266 clocks = <&clock CLK_I2C1>; 1267 clock-names = "i2c"; 1268 pinctrl-names = "default"; 1269 pinctrl-0 = <&i2c1_bus>; 1270}; 1271 1272&i2c_2 { 1273 clocks = <&clock CLK_I2C2>; 1274 clock-names = "i2c"; 1275 pinctrl-names = "default"; 1276 pinctrl-0 = <&i2c2_bus>; 1277}; 1278 1279&i2c_3 { 1280 clocks = <&clock CLK_I2C3>; 1281 clock-names = "i2c"; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&i2c3_bus>; 1284}; 1285 1286&hsi2c_4 { 1287 clocks = <&clock CLK_USI0>; 1288 clock-names = "hsi2c"; 1289 pinctrl-names = "default"; 1290 pinctrl-0 = <&i2c4_hs_bus>; 1291}; 1292 1293&hsi2c_5 { 1294 clocks = <&clock CLK_USI1>; 1295 clock-names = "hsi2c"; 1296 pinctrl-names = "default"; 1297 pinctrl-0 = <&i2c5_hs_bus>; 1298}; 1299 1300&hsi2c_6 { 1301 clocks = <&clock CLK_USI2>; 1302 clock-names = "hsi2c"; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&i2c6_hs_bus>; 1305}; 1306 1307&hsi2c_7 { 1308 clocks = <&clock CLK_USI3>; 1309 clock-names = "hsi2c"; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&i2c7_hs_bus>; 1312}; 1313 1314&mct { 1315 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 1316 clock-names = "fin_pll", "mct"; 1317}; 1318 1319&prng { 1320 clocks = <&clock CLK_SSS>; 1321 clock-names = "secss"; 1322}; 1323 1324&pwm { 1325 clocks = <&clock CLK_PWM>; 1326 clock-names = "timers"; 1327}; 1328 1329&rtc { 1330 clocks = <&clock CLK_RTC>; 1331 clock-names = "rtc"; 1332 interrupt-parent = <&pmu_system_controller>; 1333 status = "disabled"; 1334}; 1335 1336&serial_0 { 1337 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1338 clock-names = "uart", "clk_uart_baud0"; 1339 dmas = <&pdma0 13>, <&pdma0 14>; 1340 dma-names = "rx", "tx"; 1341}; 1342 1343&serial_1 { 1344 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1345 clock-names = "uart", "clk_uart_baud0"; 1346 dmas = <&pdma1 15>, <&pdma1 16>; 1347 dma-names = "rx", "tx"; 1348}; 1349 1350&serial_2 { 1351 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1352 clock-names = "uart", "clk_uart_baud0"; 1353 dmas = <&pdma0 15>, <&pdma0 16>; 1354 dma-names = "rx", "tx"; 1355}; 1356 1357&serial_3 { 1358 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1359 clock-names = "uart", "clk_uart_baud0"; 1360 dmas = <&pdma1 17>, <&pdma1 18>; 1361 dma-names = "rx", "tx"; 1362}; 1363 1364&sss { 1365 clocks = <&clock CLK_SSS>; 1366 clock-names = "secss"; 1367}; 1368 1369&trng { 1370 clocks = <&clock CLK_SSS>; 1371 clock-names = "secss"; 1372}; 1373 1374&usbdrd3_0 { 1375 clocks = <&clock CLK_USBD300>; 1376 clock-names = "usbdrd30"; 1377}; 1378 1379&usbdrd_phy0 { 1380 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; 1381 clock-names = "phy", "ref"; 1382 samsung,pmu-syscon = <&pmu_system_controller>; 1383}; 1384 1385&usbdrd3_1 { 1386 clocks = <&clock CLK_USBD301>; 1387 clock-names = "usbdrd30"; 1388}; 1389 1390&usbdrd_dwc3_1 { 1391 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1392}; 1393 1394&usbdrd_phy1 { 1395 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; 1396 clock-names = "phy", "ref"; 1397 samsung,pmu-syscon = <&pmu_system_controller>; 1398}; 1399 1400&usbhost1 { 1401 clocks = <&clock CLK_USBH20>; 1402 clock-names = "usbhost"; 1403}; 1404 1405&usbhost2 { 1406 clocks = <&clock CLK_USBH20>; 1407 clock-names = "usbhost"; 1408}; 1409 1410&usb2_phy { 1411 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; 1412 clock-names = "phy", "ref"; 1413 samsung,sysreg-phandle = <&sysreg_system_controller>; 1414 samsung,pmureg-phandle = <&pmu_system_controller>; 1415}; 1416 1417&watchdog { 1418 clocks = <&clock CLK_WDT>; 1419 clock-names = "watchdog"; 1420 samsung,syscon-phandle = <&pmu_system_controller>; 1421}; 1422 1423#include "exynos5420-pinctrl.dtsi" 1424#include "exynos-syscon-restart.dtsi" 1425