1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * This driver exists largely as a result of other people's efforts.
31 * Much of register handling is based on NetBSD CMI8x38 audio driver
32 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
33 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
34 * registers and the 8738 mixer devices. His Linux driver was also a
35 * useful reference point.
36 *
37 * TODO: MIDI
38 *
39 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
40 *
41 * This card/code does not always manage to sample at 44100 - actual
42 * rate drifts slightly between recordings (usually 0-3%). No
43 * differences visible in register dumps between times that work and
44 * those that don't.
45 */
46
47 #ifdef HAVE_KERNEL_OPTION_HEADERS
48 #include "opt_snd.h"
49 #endif
50
51 #include <dev/sound/pcm/sound.h>
52 #include <dev/sound/pci/cmireg.h>
53 #include <dev/sound/isa/sb.h>
54
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcivar.h>
57
58 #include <sys/sysctl.h>
59 #include <dev/sound/midi/mpu401.h>
60
61 #include "mixer_if.h"
62 #include "mpufoi_if.h"
63
64 SND_DECLARE_FILE("$FreeBSD: stable/12/sys/dev/sound/pci/cmi.c 326255 2017-11-27 14:52:40Z pfg $");
65
66 /* Supported chip ID's */
67 #define CMI8338A_PCI_ID 0x010013f6
68 #define CMI8338B_PCI_ID 0x010113f6
69 #define CMI8738_PCI_ID 0x011113f6
70 #define CMI8738B_PCI_ID 0x011213f6
71 #define CMI120_USB_ID 0x01030d8c
72
73 /* Buffer size max is 64k for permitted DMA boundaries */
74 #define CMI_DEFAULT_BUFSZ 16384
75
76 /* Interrupts per length of buffer */
77 #define CMI_INTR_PER_BUFFER 2
78
79 /* Clarify meaning of named defines in cmireg.h */
80 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
81 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
82 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
83 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
84
85 /* Our indication of custom mixer control */
86 #define CMPCI_NON_SB16_CONTROL 0xff
87
88 /* Debugging macro's */
89 #undef DEB
90 #ifndef DEB
91 #define DEB(x) /* x */
92 #endif /* DEB */
93
94 #ifndef DEBMIX
95 #define DEBMIX(x) /* x */
96 #endif /* DEBMIX */
97
98 /* ------------------------------------------------------------------------- */
99 /* Structures */
100
101 struct sc_info;
102
103 struct sc_chinfo {
104 struct sc_info *parent;
105 struct pcm_channel *channel;
106 struct snd_dbuf *buffer;
107 u_int32_t fmt, spd, phys_buf, bps;
108 u_int32_t dma_active:1, dma_was_active:1;
109 int dir;
110 };
111
112 struct sc_info {
113 device_t dev;
114
115 bus_space_tag_t st;
116 bus_space_handle_t sh;
117 bus_dma_tag_t parent_dmat;
118 struct resource *reg, *irq;
119 int regid, irqid;
120 void *ih;
121 struct mtx *lock;
122
123 int spdif_enabled;
124 unsigned int bufsz;
125 struct sc_chinfo pch, rch;
126
127 struct mpu401 *mpu;
128 mpu401_intr_t *mpu_intr;
129 struct resource *mpu_reg;
130 int mpu_regid;
131 bus_space_tag_t mpu_bt;
132 bus_space_handle_t mpu_bh;
133 };
134
135 /* Channel caps */
136
137 static u_int32_t cmi_fmt[] = {
138 SND_FORMAT(AFMT_U8, 1, 0),
139 SND_FORMAT(AFMT_U8, 2, 0),
140 SND_FORMAT(AFMT_S16_LE, 1, 0),
141 SND_FORMAT(AFMT_S16_LE, 2, 0),
142 0
143 };
144
145 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
146
147 /* ------------------------------------------------------------------------- */
148 /* Register Utilities */
149
150 static u_int32_t
cmi_rd(struct sc_info * sc,int regno,int size)151 cmi_rd(struct sc_info *sc, int regno, int size)
152 {
153 switch (size) {
154 case 1:
155 return bus_space_read_1(sc->st, sc->sh, regno);
156 case 2:
157 return bus_space_read_2(sc->st, sc->sh, regno);
158 case 4:
159 return bus_space_read_4(sc->st, sc->sh, regno);
160 default:
161 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size));
162 return 0xFFFFFFFF;
163 }
164 }
165
166 static void
cmi_wr(struct sc_info * sc,int regno,u_int32_t data,int size)167 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
168 {
169 switch (size) {
170 case 1:
171 bus_space_write_1(sc->st, sc->sh, regno, data);
172 break;
173 case 2:
174 bus_space_write_2(sc->st, sc->sh, regno, data);
175 break;
176 case 4:
177 bus_space_write_4(sc->st, sc->sh, regno, data);
178 break;
179 }
180 }
181
182 static void
cmi_partial_wr4(struct sc_info * sc,int reg,int shift,u_int32_t mask,u_int32_t val)183 cmi_partial_wr4(struct sc_info *sc,
184 int reg, int shift, u_int32_t mask, u_int32_t val)
185 {
186 u_int32_t r;
187
188 r = cmi_rd(sc, reg, 4);
189 r &= ~(mask << shift);
190 r |= val << shift;
191 cmi_wr(sc, reg, r, 4);
192 }
193
194 static void
cmi_clr4(struct sc_info * sc,int reg,u_int32_t mask)195 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
196 {
197 u_int32_t r;
198
199 r = cmi_rd(sc, reg, 4);
200 r &= ~mask;
201 cmi_wr(sc, reg, r, 4);
202 }
203
204 static void
cmi_set4(struct sc_info * sc,int reg,u_int32_t mask)205 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
206 {
207 u_int32_t r;
208
209 r = cmi_rd(sc, reg, 4);
210 r |= mask;
211 cmi_wr(sc, reg, r, 4);
212 }
213
214 /* ------------------------------------------------------------------------- */
215 /* Rate Mapping */
216
217 static int cmi_rates[] = {5512, 8000, 11025, 16000,
218 22050, 32000, 44100, 48000};
219 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
220
221 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
222 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
223
224 static u_int32_t
cmpci_rate_to_regvalue(int rate)225 cmpci_rate_to_regvalue(int rate)
226 {
227 int i, r;
228
229 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
230 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
231 break;
232 }
233 }
234
235 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
236
237 r = ((i >> 1) | (i << 2)) & 0x07;
238 return r;
239 }
240
241 static int
cmpci_regvalue_to_rate(u_int32_t r)242 cmpci_regvalue_to_rate(u_int32_t r)
243 {
244 int i;
245
246 i = ((r << 1) | (r >> 2)) & 0x07;
247 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
248 return cmi_rates[i];
249 }
250
251 /* ------------------------------------------------------------------------- */
252 /* ADC/DAC control - there are 2 dma channels on 8738, either can be
253 * playback or capture. We use ch0 for playback and ch1 for capture. */
254
255 static void
cmi_dma_prog(struct sc_info * sc,struct sc_chinfo * ch,u_int32_t base)256 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
257 {
258 u_int32_t s, i, sz;
259
260 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
261
262 cmi_wr(sc, base, ch->phys_buf, 4);
263 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
264
265 s = sz / ch->bps - 1;
266 cmi_wr(sc, base + 4, s, 2);
267
268 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
269 cmi_wr(sc, base + 6, i, 2);
270 }
271
272
273 static void
cmi_ch0_start(struct sc_info * sc,struct sc_chinfo * ch)274 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
275 {
276 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
277
278 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
279 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
280 CMPCI_REG_CH0_INTR_ENABLE);
281
282 ch->dma_active = 1;
283 }
284
285 static u_int32_t
cmi_ch0_stop(struct sc_info * sc,struct sc_chinfo * ch)286 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
287 {
288 u_int32_t r = ch->dma_active;
289
290 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
291 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
292 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
293 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
294 ch->dma_active = 0;
295 return r;
296 }
297
298 static void
cmi_ch1_start(struct sc_info * sc,struct sc_chinfo * ch)299 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
300 {
301 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
302 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
303 /* Enable Interrupts */
304 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
305 CMPCI_REG_CH1_INTR_ENABLE);
306 DEB(printf("cmi_ch1_start: dma prog\n"));
307 ch->dma_active = 1;
308 }
309
310 static u_int32_t
cmi_ch1_stop(struct sc_info * sc,struct sc_chinfo * ch)311 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
312 {
313 u_int32_t r = ch->dma_active;
314
315 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
316 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
317 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
318 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
319 ch->dma_active = 0;
320 return r;
321 }
322
323 static void
cmi_spdif_speed(struct sc_info * sc,int speed)324 cmi_spdif_speed(struct sc_info *sc, int speed) {
325 u_int32_t fcr1, lcr, mcr;
326
327 if (speed >= 44100) {
328 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
329 lcr = CMPCI_REG_XSPDIF_ENABLE;
330 mcr = (speed == 48000) ?
331 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
332 } else {
333 fcr1 = mcr = lcr = 0;
334 }
335
336 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
337 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
338 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
339 CMPCI_REG_SPDIF0_ENABLE, fcr1);
340 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
341 CMPCI_REG_XSPDIF_ENABLE, lcr);
342 }
343
344 /* ------------------------------------------------------------------------- */
345 /* Channel Interface implementation */
346
347 static void *
cmichan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)348 cmichan_init(kobj_t obj, void *devinfo,
349 struct snd_dbuf *b, struct pcm_channel *c, int dir)
350 {
351 struct sc_info *sc = devinfo;
352 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
353
354 ch->parent = sc;
355 ch->channel = c;
356 ch->bps = 1;
357 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
358 ch->spd = DSP_DEFAULT_SPEED;
359 ch->buffer = b;
360 ch->dma_active = 0;
361 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
362 DEB(printf("cmichan_init failed\n"));
363 return NULL;
364 }
365
366 ch->dir = dir;
367 snd_mtxlock(sc->lock);
368 if (ch->dir == PCMDIR_PLAY) {
369 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
370 } else {
371 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
372 }
373 snd_mtxunlock(sc->lock);
374
375 return ch;
376 }
377
378 static int
cmichan_setformat(kobj_t obj,void * data,u_int32_t format)379 cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
380 {
381 struct sc_chinfo *ch = data;
382 struct sc_info *sc = ch->parent;
383 u_int32_t f;
384
385 if (format & AFMT_S16_LE) {
386 f = CMPCI_REG_FORMAT_16BIT;
387 ch->bps = 2;
388 } else {
389 f = CMPCI_REG_FORMAT_8BIT;
390 ch->bps = 1;
391 }
392
393 if (AFMT_CHANNEL(format) > 1) {
394 f |= CMPCI_REG_FORMAT_STEREO;
395 ch->bps *= 2;
396 } else {
397 f |= CMPCI_REG_FORMAT_MONO;
398 }
399
400 snd_mtxlock(sc->lock);
401 if (ch->dir == PCMDIR_PLAY) {
402 cmi_partial_wr4(ch->parent,
403 CMPCI_REG_CHANNEL_FORMAT,
404 CMPCI_REG_CH0_FORMAT_SHIFT,
405 CMPCI_REG_CH0_FORMAT_MASK,
406 f);
407 } else {
408 cmi_partial_wr4(ch->parent,
409 CMPCI_REG_CHANNEL_FORMAT,
410 CMPCI_REG_CH1_FORMAT_SHIFT,
411 CMPCI_REG_CH1_FORMAT_MASK,
412 f);
413 }
414 snd_mtxunlock(sc->lock);
415 ch->fmt = format;
416
417 return 0;
418 }
419
420 static u_int32_t
cmichan_setspeed(kobj_t obj,void * data,u_int32_t speed)421 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
422 {
423 struct sc_chinfo *ch = data;
424 struct sc_info *sc = ch->parent;
425 u_int32_t r, rsp;
426
427 r = cmpci_rate_to_regvalue(speed);
428 snd_mtxlock(sc->lock);
429 if (ch->dir == PCMDIR_PLAY) {
430 if (speed < 44100) {
431 /* disable if req before rate change */
432 cmi_spdif_speed(ch->parent, speed);
433 }
434 cmi_partial_wr4(ch->parent,
435 CMPCI_REG_FUNC_1,
436 CMPCI_REG_DAC_FS_SHIFT,
437 CMPCI_REG_DAC_FS_MASK,
438 r);
439 if (speed >= 44100 && ch->parent->spdif_enabled) {
440 /* enable if req after rate change */
441 cmi_spdif_speed(ch->parent, speed);
442 }
443 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
444 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
445 rsp &= CMPCI_REG_DAC_FS_MASK;
446 } else {
447 cmi_partial_wr4(ch->parent,
448 CMPCI_REG_FUNC_1,
449 CMPCI_REG_ADC_FS_SHIFT,
450 CMPCI_REG_ADC_FS_MASK,
451 r);
452 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
453 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
454 rsp &= CMPCI_REG_ADC_FS_MASK;
455 }
456 snd_mtxunlock(sc->lock);
457 ch->spd = cmpci_regvalue_to_rate(r);
458
459 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n",
460 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
461 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
462
463 return ch->spd;
464 }
465
466 static u_int32_t
cmichan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)467 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
468 {
469 struct sc_chinfo *ch = data;
470 struct sc_info *sc = ch->parent;
471
472 /* user has requested interrupts every blocksize bytes */
473 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
474 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
475 }
476 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
477
478 return blocksize;
479 }
480
481 static int
cmichan_trigger(kobj_t obj,void * data,int go)482 cmichan_trigger(kobj_t obj, void *data, int go)
483 {
484 struct sc_chinfo *ch = data;
485 struct sc_info *sc = ch->parent;
486
487 if (!PCMTRIG_COMMON(go))
488 return 0;
489
490 snd_mtxlock(sc->lock);
491 if (ch->dir == PCMDIR_PLAY) {
492 switch(go) {
493 case PCMTRIG_START:
494 cmi_ch0_start(sc, ch);
495 break;
496 case PCMTRIG_STOP:
497 case PCMTRIG_ABORT:
498 cmi_ch0_stop(sc, ch);
499 break;
500 }
501 } else {
502 switch(go) {
503 case PCMTRIG_START:
504 cmi_ch1_start(sc, ch);
505 break;
506 case PCMTRIG_STOP:
507 case PCMTRIG_ABORT:
508 cmi_ch1_stop(sc, ch);
509 break;
510 }
511 }
512 snd_mtxunlock(sc->lock);
513 return 0;
514 }
515
516 static u_int32_t
cmichan_getptr(kobj_t obj,void * data)517 cmichan_getptr(kobj_t obj, void *data)
518 {
519 struct sc_chinfo *ch = data;
520 struct sc_info *sc = ch->parent;
521 u_int32_t physptr, bufptr, sz;
522
523 snd_mtxlock(sc->lock);
524 if (ch->dir == PCMDIR_PLAY) {
525 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
526 } else {
527 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
528 }
529 snd_mtxunlock(sc->lock);
530
531 sz = sndbuf_getsize(ch->buffer);
532 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
533
534 return bufptr;
535 }
536
537 static void
cmi_intr(void * data)538 cmi_intr(void *data)
539 {
540 struct sc_info *sc = data;
541 u_int32_t intrstat;
542 u_int32_t toclear;
543
544 snd_mtxlock(sc->lock);
545 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
546 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
547
548 toclear = 0;
549 if (intrstat & CMPCI_REG_CH0_INTR) {
550 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
551 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
552 }
553
554 if (intrstat & CMPCI_REG_CH1_INTR) {
555 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
556 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
557 }
558
559 if (toclear) {
560 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
561 snd_mtxunlock(sc->lock);
562
563 /* Signal interrupts to channel */
564 if (intrstat & CMPCI_REG_CH0_INTR) {
565 chn_intr(sc->pch.channel);
566 }
567
568 if (intrstat & CMPCI_REG_CH1_INTR) {
569 chn_intr(sc->rch.channel);
570 }
571
572 snd_mtxlock(sc->lock);
573 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
574
575 }
576 }
577 if(sc->mpu_intr) {
578 (sc->mpu_intr)(sc->mpu);
579 }
580 snd_mtxunlock(sc->lock);
581 return;
582 }
583
584 static struct pcmchan_caps *
cmichan_getcaps(kobj_t obj,void * data)585 cmichan_getcaps(kobj_t obj, void *data)
586 {
587 return &cmi_caps;
588 }
589
590 static kobj_method_t cmichan_methods[] = {
591 KOBJMETHOD(channel_init, cmichan_init),
592 KOBJMETHOD(channel_setformat, cmichan_setformat),
593 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
594 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
595 KOBJMETHOD(channel_trigger, cmichan_trigger),
596 KOBJMETHOD(channel_getptr, cmichan_getptr),
597 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
598 KOBJMETHOD_END
599 };
600 CHANNEL_DECLARE(cmichan);
601
602 /* ------------------------------------------------------------------------- */
603 /* Mixer - sb16 with kinks */
604
605 static void
cmimix_wr(struct sc_info * sc,u_int8_t port,u_int8_t val)606 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
607 {
608 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
609 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
610 }
611
612 static u_int8_t
cmimix_rd(struct sc_info * sc,u_int8_t port)613 cmimix_rd(struct sc_info *sc, u_int8_t port)
614 {
615 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
616 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
617 }
618
619 struct sb16props {
620 u_int8_t rreg; /* right reg chan register */
621 u_int8_t stereo:1; /* (no explanation needed, honest) */
622 u_int8_t rec:1; /* recording source */
623 u_int8_t bits:3; /* num bits to represent maximum gain rep */
624 u_int8_t oselect; /* output select mask */
625 u_int8_t iselect; /* right input select mask */
626 } static const cmt[SOUND_MIXER_NRDEVICES] = {
627 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
628 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
629 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
630 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
631 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
632 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
633 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
634 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
635 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
636 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
637 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
638 /* These controls are not implemented in CMI8738, but maybe at a
639 future date. They are not documented in C-Media documentation,
640 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
641 */
642 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
643 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
644 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
645 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
646 /* The mic pre-amp is implemented with non-SB16 compatible
647 registers. */
648 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
649 };
650
651 #define MIXER_GAIN_REG_RTOL(r) (r - 1)
652
653 static int
cmimix_init(struct snd_mixer * m)654 cmimix_init(struct snd_mixer *m)
655 {
656 struct sc_info *sc = mix_getdevinfo(m);
657 u_int32_t i,v;
658
659 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
660 if (cmt[i].bits) v |= 1 << i;
661 }
662 mix_setdevs(m, v);
663
664 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
665 if (cmt[i].rec) v |= 1 << i;
666 }
667 mix_setrecdevs(m, v);
668
669 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
670 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
671 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
672 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
673 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
674 return 0;
675 }
676
677 static int
cmimix_set(struct snd_mixer * m,unsigned dev,unsigned left,unsigned right)678 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
679 {
680 struct sc_info *sc = mix_getdevinfo(m);
681 u_int32_t r, l, max;
682 u_int8_t v;
683
684 max = (1 << cmt[dev].bits) - 1;
685
686 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
687 /* For time being this can only be one thing (mic in
688 * mic/aux reg) */
689 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
690 l = left * max / 100;
691 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
692 v |= ((l << 1) | (~l >> 3)) & 0x0f;
693 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
694 return 0;
695 }
696
697 l = (left * max / 100) << (8 - cmt[dev].bits);
698 if (cmt[dev].stereo) {
699 r = (right * max / 100) << (8 - cmt[dev].bits);
700 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
701 cmimix_wr(sc, cmt[dev].rreg, r);
702 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\
703 "value 0x%02x:0x%02x\n",
704 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
705 } else {
706 r = l;
707 cmimix_wr(sc, cmt[dev].rreg, l);
708 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \
709 "value 0x%02x:0x%02x\n",
710 dev, cmt[dev].rreg, l, l));
711 }
712
713 /* Zero gain does not mute channel from output, but this does... */
714 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
715 if (l == 0 && r == 0) {
716 v &= ~cmt[dev].oselect;
717 } else {
718 v |= cmt[dev].oselect;
719 }
720 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
721
722 return 0;
723 }
724
725 static u_int32_t
cmimix_setrecsrc(struct snd_mixer * m,u_int32_t src)726 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
727 {
728 struct sc_info *sc = mix_getdevinfo(m);
729 u_int32_t i, ml, sl;
730
731 ml = sl = 0;
732 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
733 if ((1<<i) & src) {
734 if (cmt[i].stereo) {
735 sl |= cmt[i].iselect;
736 } else {
737 ml |= cmt[i].iselect;
738 }
739 }
740 }
741 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
742 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
743 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
744 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
745 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
746 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
747 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
748
749 return src;
750 }
751
752 /* Optional SPDIF support. */
753
754 static int
cmi_initsys(struct sc_info * sc)755 cmi_initsys(struct sc_info* sc)
756 {
757 /* XXX: an user should be able to set this with a control tool,
758 if not done before 7.0-RELEASE, this needs to be converted
759 to a device specific sysctl "dev.pcm.X.yyy" via
760 device_get_sysctl_*() as discussed on multimedia@ in msg-id
761 <861wujij2q.fsf@xps.des.no> */
762 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
763 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
764 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
765 &sc->spdif_enabled, 0,
766 "enable SPDIF output at 44.1 kHz and above");
767
768 return 0;
769 }
770
771 /* ------------------------------------------------------------------------- */
772 static kobj_method_t cmi_mixer_methods[] = {
773 KOBJMETHOD(mixer_init, cmimix_init),
774 KOBJMETHOD(mixer_set, cmimix_set),
775 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
776 KOBJMETHOD_END
777 };
778 MIXER_DECLARE(cmi_mixer);
779
780 /*
781 * mpu401 functions
782 */
783
784 static unsigned char
cmi_mread(struct mpu401 * arg,void * sc,int reg)785 cmi_mread(struct mpu401 *arg, void *sc, int reg)
786 {
787 unsigned int d;
788
789 d = bus_space_read_1(0,0, 0x330 + reg);
790 /* printf("cmi_mread: reg %x %x\n",reg, d);
791 */
792 return d;
793 }
794
795 static void
cmi_mwrite(struct mpu401 * arg,void * sc,int reg,unsigned char b)796 cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)
797 {
798
799 bus_space_write_1(0,0,0x330 + reg , b);
800 }
801
802 static int
cmi_muninit(struct mpu401 * arg,void * cookie)803 cmi_muninit(struct mpu401 *arg, void *cookie)
804 {
805 struct sc_info *sc = cookie;
806
807 snd_mtxlock(sc->lock);
808 sc->mpu_intr = NULL;
809 sc->mpu = NULL;
810 snd_mtxunlock(sc->lock);
811
812 return 0;
813 }
814
815 static kobj_method_t cmi_mpu_methods[] = {
816 KOBJMETHOD(mpufoi_read, cmi_mread),
817 KOBJMETHOD(mpufoi_write, cmi_mwrite),
818 KOBJMETHOD(mpufoi_uninit, cmi_muninit),
819 KOBJMETHOD_END
820 };
821
822 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0);
823
824 static void
cmi_midiattach(struct sc_info * sc)825 cmi_midiattach(struct sc_info *sc) {
826 /*
827 const struct {
828 int port,bits;
829 } *p, ports[] = {
830 {0x330,0},
831 {0x320,1},
832 {0x310,2},
833 {0x300,3},
834 {0,0} } ;
835 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does
836 anyone know how to bus_space tag?
837 */
838 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
839 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL,
840 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT);
841 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL,
842 0 << CMPCI_REG_VMPUSEL_SHIFT );
843 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
844 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr);
845 }
846
847
848
849 /* ------------------------------------------------------------------------- */
850 /* Power and reset */
851
852 static void
cmi_power(struct sc_info * sc,int state)853 cmi_power(struct sc_info *sc, int state)
854 {
855 switch (state) {
856 case 0: /* full power */
857 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
858 break;
859 default:
860 /* power off */
861 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
862 break;
863 }
864 }
865
866 static int
cmi_init(struct sc_info * sc)867 cmi_init(struct sc_info *sc)
868 {
869 /* Effect reset */
870 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
871 DELAY(100);
872 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
873
874 /* Disable interrupts and channels */
875 cmi_clr4(sc, CMPCI_REG_FUNC_0,
876 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
877 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
878 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
879
880 /* Configure DMA channels, ch0 = play, ch1 = capture */
881 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
882 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
883
884 /* Attempt to enable 4 Channel output */
885 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
886
887 /* Disable SPDIF1 - not compatible with config */
888 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
889 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
890
891 return 0;
892 }
893
894 static void
cmi_uninit(struct sc_info * sc)895 cmi_uninit(struct sc_info *sc)
896 {
897 /* Disable interrupts and channels */
898 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
899 CMPCI_REG_CH0_INTR_ENABLE |
900 CMPCI_REG_CH1_INTR_ENABLE |
901 CMPCI_REG_TDMA_INTR_ENABLE);
902 cmi_clr4(sc, CMPCI_REG_FUNC_0,
903 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
904 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
905
906 if( sc->mpu )
907 sc->mpu_intr = NULL;
908 }
909
910 /* ------------------------------------------------------------------------- */
911 /* Bus and device registration */
912 static int
cmi_probe(device_t dev)913 cmi_probe(device_t dev)
914 {
915 switch(pci_get_devid(dev)) {
916 case CMI8338A_PCI_ID:
917 device_set_desc(dev, "CMedia CMI8338A");
918 return BUS_PROBE_DEFAULT;
919 case CMI8338B_PCI_ID:
920 device_set_desc(dev, "CMedia CMI8338B");
921 return BUS_PROBE_DEFAULT;
922 case CMI8738_PCI_ID:
923 device_set_desc(dev, "CMedia CMI8738");
924 return BUS_PROBE_DEFAULT;
925 case CMI8738B_PCI_ID:
926 device_set_desc(dev, "CMedia CMI8738B");
927 return BUS_PROBE_DEFAULT;
928 case CMI120_USB_ID:
929 device_set_desc(dev, "CMedia CMI120");
930 return BUS_PROBE_DEFAULT;
931 default:
932 return ENXIO;
933 }
934 }
935
936 static int
cmi_attach(device_t dev)937 cmi_attach(device_t dev)
938 {
939 struct sc_info *sc;
940 char status[SND_STATUSLEN];
941
942 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
943 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc");
944 pci_enable_busmaster(dev);
945
946 sc->dev = dev;
947 sc->regid = PCIR_BAR(0);
948 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
949 RF_ACTIVE);
950 if (!sc->reg) {
951 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
952 goto bad;
953 }
954 sc->st = rman_get_bustag(sc->reg);
955 sc->sh = rman_get_bushandle(sc->reg);
956
957 if (0)
958 cmi_midiattach(sc);
959
960 sc->irqid = 0;
961 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
962 RF_ACTIVE | RF_SHAREABLE);
963 if (!sc->irq ||
964 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
965 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
966 goto bad;
967 }
968
969 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
970
971 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
972 /*boundary*/0,
973 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
974 /*highaddr*/BUS_SPACE_MAXADDR,
975 /*filter*/NULL, /*filterarg*/NULL,
976 /*maxsize*/sc->bufsz, /*nsegments*/1,
977 /*maxsegz*/0x3ffff, /*flags*/0,
978 /*lockfunc*/NULL,
979 /*lockfunc*/NULL,
980 &sc->parent_dmat) != 0) {
981 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
982 goto bad;
983 }
984
985 cmi_power(sc, 0);
986 if (cmi_init(sc))
987 goto bad;
988
989 if (mixer_init(dev, &cmi_mixer_class, sc))
990 goto bad;
991
992 if (pcm_register(dev, sc, 1, 1))
993 goto bad;
994
995 cmi_initsys(sc);
996
997 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
998 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
999
1000 snprintf(status, SND_STATUSLEN, "at io 0x%jx irq %jd %s",
1001 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
1002 pcm_setstatus(dev, status);
1003
1004 DEB(printf("cmi_attach: succeeded\n"));
1005 return 0;
1006
1007 bad:
1008 if (sc->parent_dmat)
1009 bus_dma_tag_destroy(sc->parent_dmat);
1010 if (sc->ih)
1011 bus_teardown_intr(dev, sc->irq, sc->ih);
1012 if (sc->irq)
1013 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1014 if (sc->reg)
1015 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1016 if (sc->lock)
1017 snd_mtxfree(sc->lock);
1018 if (sc)
1019 free(sc, M_DEVBUF);
1020
1021 return ENXIO;
1022 }
1023
1024 static int
cmi_detach(device_t dev)1025 cmi_detach(device_t dev)
1026 {
1027 struct sc_info *sc;
1028 int r;
1029
1030 r = pcm_unregister(dev);
1031 if (r) return r;
1032
1033 sc = pcm_getdevinfo(dev);
1034 cmi_uninit(sc);
1035 cmi_power(sc, 3);
1036
1037 bus_dma_tag_destroy(sc->parent_dmat);
1038 bus_teardown_intr(dev, sc->irq, sc->ih);
1039 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1040 if(sc->mpu)
1041 mpu401_uninit(sc->mpu);
1042 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
1043 if (sc->mpu_reg)
1044 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg);
1045
1046 snd_mtxfree(sc->lock);
1047 free(sc, M_DEVBUF);
1048
1049 return 0;
1050 }
1051
1052 static int
cmi_suspend(device_t dev)1053 cmi_suspend(device_t dev)
1054 {
1055 struct sc_info *sc = pcm_getdevinfo(dev);
1056
1057 snd_mtxlock(sc->lock);
1058 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
1059 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
1060 cmi_power(sc, 3);
1061 snd_mtxunlock(sc->lock);
1062 return 0;
1063 }
1064
1065 static int
cmi_resume(device_t dev)1066 cmi_resume(device_t dev)
1067 {
1068 struct sc_info *sc = pcm_getdevinfo(dev);
1069
1070 snd_mtxlock(sc->lock);
1071 cmi_power(sc, 0);
1072 if (cmi_init(sc) != 0) {
1073 device_printf(dev, "unable to reinitialize the card\n");
1074 snd_mtxunlock(sc->lock);
1075 return ENXIO;
1076 }
1077
1078 if (mixer_reinit(dev) == -1) {
1079 device_printf(dev, "unable to reinitialize the mixer\n");
1080 snd_mtxunlock(sc->lock);
1081 return ENXIO;
1082 }
1083
1084 if (sc->pch.dma_was_active) {
1085 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
1086 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
1087 cmi_ch0_start(sc, &sc->pch);
1088 }
1089
1090 if (sc->rch.dma_was_active) {
1091 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
1092 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
1093 cmi_ch1_start(sc, &sc->rch);
1094 }
1095 snd_mtxunlock(sc->lock);
1096 return 0;
1097 }
1098
1099 static device_method_t cmi_methods[] = {
1100 DEVMETHOD(device_probe, cmi_probe),
1101 DEVMETHOD(device_attach, cmi_attach),
1102 DEVMETHOD(device_detach, cmi_detach),
1103 DEVMETHOD(device_resume, cmi_resume),
1104 DEVMETHOD(device_suspend, cmi_suspend),
1105 { 0, 0 }
1106 };
1107
1108 static driver_t cmi_driver = {
1109 "pcm",
1110 cmi_methods,
1111 PCM_SOFTC_SIZE
1112 };
1113
1114 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0);
1115 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1116 MODULE_DEPEND(snd_cmi, midi, 1,1,1);
1117 MODULE_VERSION(snd_cmi, 1);
1118