1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010-2016 Solarflare Communications Inc.
5 * All rights reserved.
6 *
7 * This software was developed in part by Philip Paeps under contract for
8 * Solarflare Communications, Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * The views and conclusions contained in the software and documentation are
32 * those of the authors and should not be interpreted as representing official
33 * policies, either expressed or implied, of the FreeBSD Project.
34 */
35
36 /* Theory of operation:
37 *
38 * Tx queues allocation and mapping on Siena
39 *
40 * One Tx queue with enabled checksum offload is allocated per Rx channel
41 * (event queue). Also 2 Tx queues (one without checksum offload and one
42 * with IP checksum offload only) are allocated and bound to event queue 0.
43 * sfxge_txq_type is used as Tx queue label.
44 *
45 * So, event queue plus label mapping to Tx queue index is:
46 * if event queue index is 0, TxQ-index = TxQ-label * [0..SFXGE_TXQ_NTYPES)
47 * else TxQ-index = SFXGE_TXQ_NTYPES + EvQ-index - 1
48 * See sfxge_get_txq_by_label() sfxge_ev.c
49 *
50 * Tx queue allocation and mapping on EF10
51 *
52 * One Tx queue with enabled checksum offload is allocated per Rx
53 * channel (event queue). Checksum offload on all Tx queues is enabled or
54 * disabled dynamically by inserting option descriptors, so the additional
55 * queues used on Siena are not required.
56 *
57 * TxQ label is always set to zero on EF10 hardware.
58 * So, event queue to Tx queue mapping is simple:
59 * TxQ-index = EvQ-index
60 */
61
62 #include <sys/cdefs.h>
63 __FBSDID("$FreeBSD: stable/12/sys/dev/sfxge/sfxge_tx.c 342352 2018-12-21 17:26:22Z arybchik $");
64
65 #include "opt_rss.h"
66
67 #include <sys/param.h>
68 #include <sys/malloc.h>
69 #include <sys/mbuf.h>
70 #include <sys/smp.h>
71 #include <sys/socket.h>
72 #include <sys/sysctl.h>
73 #include <sys/syslog.h>
74 #include <sys/limits.h>
75
76 #include <net/bpf.h>
77 #include <net/ethernet.h>
78 #include <net/if.h>
79 #include <net/if_vlan_var.h>
80
81 #include <netinet/in.h>
82 #include <netinet/ip.h>
83 #include <netinet/ip6.h>
84 #include <netinet/tcp.h>
85
86 #ifdef RSS
87 #include <net/rss_config.h>
88 #endif
89
90 #include "common/efx.h"
91
92 #include "sfxge.h"
93 #include "sfxge_tx.h"
94
95
96 #define SFXGE_PARAM_TX_DPL_GET_MAX SFXGE_PARAM(tx_dpl_get_max)
97 static int sfxge_tx_dpl_get_max = SFXGE_TX_DPL_GET_PKT_LIMIT_DEFAULT;
98 TUNABLE_INT(SFXGE_PARAM_TX_DPL_GET_MAX, &sfxge_tx_dpl_get_max);
99 SYSCTL_INT(_hw_sfxge, OID_AUTO, tx_dpl_get_max, CTLFLAG_RDTUN,
100 &sfxge_tx_dpl_get_max, 0,
101 "Maximum number of any packets in deferred packet get-list");
102
103 #define SFXGE_PARAM_TX_DPL_GET_NON_TCP_MAX \
104 SFXGE_PARAM(tx_dpl_get_non_tcp_max)
105 static int sfxge_tx_dpl_get_non_tcp_max =
106 SFXGE_TX_DPL_GET_NON_TCP_PKT_LIMIT_DEFAULT;
107 TUNABLE_INT(SFXGE_PARAM_TX_DPL_GET_NON_TCP_MAX, &sfxge_tx_dpl_get_non_tcp_max);
108 SYSCTL_INT(_hw_sfxge, OID_AUTO, tx_dpl_get_non_tcp_max, CTLFLAG_RDTUN,
109 &sfxge_tx_dpl_get_non_tcp_max, 0,
110 "Maximum number of non-TCP packets in deferred packet get-list");
111
112 #define SFXGE_PARAM_TX_DPL_PUT_MAX SFXGE_PARAM(tx_dpl_put_max)
113 static int sfxge_tx_dpl_put_max = SFXGE_TX_DPL_PUT_PKT_LIMIT_DEFAULT;
114 TUNABLE_INT(SFXGE_PARAM_TX_DPL_PUT_MAX, &sfxge_tx_dpl_put_max);
115 SYSCTL_INT(_hw_sfxge, OID_AUTO, tx_dpl_put_max, CTLFLAG_RDTUN,
116 &sfxge_tx_dpl_put_max, 0,
117 "Maximum number of any packets in deferred packet put-list");
118
119 #define SFXGE_PARAM_TSO_FW_ASSISTED SFXGE_PARAM(tso_fw_assisted)
120 static int sfxge_tso_fw_assisted = (SFXGE_FATSOV1 | SFXGE_FATSOV2);
121 TUNABLE_INT(SFXGE_PARAM_TSO_FW_ASSISTED, &sfxge_tso_fw_assisted);
122 SYSCTL_INT(_hw_sfxge, OID_AUTO, tso_fw_assisted, CTLFLAG_RDTUN,
123 &sfxge_tso_fw_assisted, 0,
124 "Bitmask of FW-assisted TSO allowed to use if supported by NIC firmware");
125
126
127 static const struct {
128 const char *name;
129 size_t offset;
130 } sfxge_tx_stats[] = {
131 #define SFXGE_TX_STAT(name, member) \
132 { #name, offsetof(struct sfxge_txq, member) }
133 SFXGE_TX_STAT(tso_bursts, tso_bursts),
134 SFXGE_TX_STAT(tso_packets, tso_packets),
135 SFXGE_TX_STAT(tso_long_headers, tso_long_headers),
136 SFXGE_TX_STAT(tso_pdrop_too_many, tso_pdrop_too_many),
137 SFXGE_TX_STAT(tso_pdrop_no_rsrc, tso_pdrop_no_rsrc),
138 SFXGE_TX_STAT(tx_collapses, collapses),
139 SFXGE_TX_STAT(tx_drops, drops),
140 SFXGE_TX_STAT(tx_get_overflow, get_overflow),
141 SFXGE_TX_STAT(tx_get_non_tcp_overflow, get_non_tcp_overflow),
142 SFXGE_TX_STAT(tx_put_overflow, put_overflow),
143 SFXGE_TX_STAT(tx_netdown_drops, netdown_drops),
144 };
145
146
147 /* Forward declarations. */
148 static void sfxge_tx_qdpl_service(struct sfxge_txq *txq);
149 static void sfxge_tx_qlist_post(struct sfxge_txq *txq);
150 static void sfxge_tx_qunblock(struct sfxge_txq *txq);
151 static int sfxge_tx_queue_tso(struct sfxge_txq *txq, struct mbuf *mbuf,
152 const bus_dma_segment_t *dma_seg, int n_dma_seg,
153 int n_extra_descs);
154
155 static inline void
sfxge_next_stmp(struct sfxge_txq * txq,struct sfxge_tx_mapping ** pstmp)156 sfxge_next_stmp(struct sfxge_txq *txq, struct sfxge_tx_mapping **pstmp)
157 {
158 KASSERT((*pstmp)->flags == 0, ("stmp flags are not 0"));
159 if (__predict_false(*pstmp ==
160 &txq->stmp[txq->ptr_mask]))
161 *pstmp = &txq->stmp[0];
162 else
163 (*pstmp)++;
164 }
165
166 static int
sfxge_tx_maybe_toggle_cksum_offload(struct sfxge_txq * txq,struct mbuf * mbuf,struct sfxge_tx_mapping ** pstmp)167 sfxge_tx_maybe_toggle_cksum_offload(struct sfxge_txq *txq, struct mbuf *mbuf,
168 struct sfxge_tx_mapping **pstmp)
169 {
170 uint16_t new_hw_cksum_flags;
171 efx_desc_t *desc;
172
173 if (mbuf->m_pkthdr.csum_flags &
174 (CSUM_DELAY_DATA | CSUM_DELAY_DATA_IPV6 | CSUM_TSO)) {
175 /*
176 * We always set EFX_TXQ_CKSUM_IPV4 here because this
177 * configuration is the most useful, and this won't
178 * cause any trouble in case of IPv6 traffic anyway.
179 */
180 new_hw_cksum_flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
181 } else if (mbuf->m_pkthdr.csum_flags & CSUM_DELAY_IP) {
182 new_hw_cksum_flags = EFX_TXQ_CKSUM_IPV4;
183 } else {
184 new_hw_cksum_flags = 0;
185 }
186
187 if (new_hw_cksum_flags == txq->hw_cksum_flags)
188 return (0);
189
190 desc = &txq->pend_desc[txq->n_pend_desc];
191 efx_tx_qdesc_checksum_create(txq->common, new_hw_cksum_flags, desc);
192 txq->hw_cksum_flags = new_hw_cksum_flags;
193 txq->n_pend_desc++;
194
195 sfxge_next_stmp(txq, pstmp);
196
197 return (1);
198 }
199
200 static int
sfxge_tx_maybe_insert_tag(struct sfxge_txq * txq,struct mbuf * mbuf,struct sfxge_tx_mapping ** pstmp)201 sfxge_tx_maybe_insert_tag(struct sfxge_txq *txq, struct mbuf *mbuf,
202 struct sfxge_tx_mapping **pstmp)
203 {
204 uint16_t this_tag = ((mbuf->m_flags & M_VLANTAG) ?
205 mbuf->m_pkthdr.ether_vtag :
206 0);
207 efx_desc_t *desc;
208
209 if (this_tag == txq->hw_vlan_tci)
210 return (0);
211
212 desc = &txq->pend_desc[txq->n_pend_desc];
213 efx_tx_qdesc_vlantci_create(txq->common, bswap16(this_tag), desc);
214 txq->hw_vlan_tci = this_tag;
215 txq->n_pend_desc++;
216
217 sfxge_next_stmp(txq, pstmp);
218
219 return (1);
220 }
221
222 void
sfxge_tx_qcomplete(struct sfxge_txq * txq,struct sfxge_evq * evq)223 sfxge_tx_qcomplete(struct sfxge_txq *txq, struct sfxge_evq *evq)
224 {
225 unsigned int completed;
226
227 SFXGE_EVQ_LOCK_ASSERT_OWNED(evq);
228
229 completed = txq->completed;
230 while (completed != txq->pending) {
231 struct sfxge_tx_mapping *stmp;
232 unsigned int id;
233
234 id = completed++ & txq->ptr_mask;
235
236 stmp = &txq->stmp[id];
237 if (stmp->flags & TX_BUF_UNMAP) {
238 bus_dmamap_unload(txq->packet_dma_tag, stmp->map);
239 if (stmp->flags & TX_BUF_MBUF) {
240 struct mbuf *m = stmp->u.mbuf;
241 do
242 m = m_free(m);
243 while (m != NULL);
244 } else {
245 free(stmp->u.heap_buf, M_SFXGE);
246 }
247 stmp->flags = 0;
248 }
249 }
250 txq->completed = completed;
251
252 /* Check whether we need to unblock the queue. */
253 mb();
254 if (txq->blocked) {
255 unsigned int level;
256
257 level = txq->added - txq->completed;
258 if (level <= SFXGE_TXQ_UNBLOCK_LEVEL(txq->entries))
259 sfxge_tx_qunblock(txq);
260 }
261 }
262
263 static unsigned int
sfxge_is_mbuf_non_tcp(struct mbuf * mbuf)264 sfxge_is_mbuf_non_tcp(struct mbuf *mbuf)
265 {
266 /* Absence of TCP checksum flags does not mean that it is non-TCP
267 * but it should be true if user wants to achieve high throughput.
268 */
269 return (!(mbuf->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)));
270 }
271
272 /*
273 * Reorder the put list and append it to the get list.
274 */
275 static void
sfxge_tx_qdpl_swizzle(struct sfxge_txq * txq)276 sfxge_tx_qdpl_swizzle(struct sfxge_txq *txq)
277 {
278 struct sfxge_tx_dpl *stdp;
279 struct mbuf *mbuf, *get_next, **get_tailp;
280 volatile uintptr_t *putp;
281 uintptr_t put;
282 unsigned int count;
283 unsigned int non_tcp_count;
284
285 SFXGE_TXQ_LOCK_ASSERT_OWNED(txq);
286
287 stdp = &txq->dpl;
288
289 /* Acquire the put list. */
290 putp = &stdp->std_put;
291 put = atomic_readandclear_ptr(putp);
292 mbuf = (void *)put;
293
294 if (mbuf == NULL)
295 return;
296
297 /* Reverse the put list. */
298 get_tailp = &mbuf->m_nextpkt;
299 get_next = NULL;
300
301 count = 0;
302 non_tcp_count = 0;
303 do {
304 struct mbuf *put_next;
305
306 non_tcp_count += sfxge_is_mbuf_non_tcp(mbuf);
307 put_next = mbuf->m_nextpkt;
308 mbuf->m_nextpkt = get_next;
309 get_next = mbuf;
310 mbuf = put_next;
311
312 count++;
313 } while (mbuf != NULL);
314
315 if (count > stdp->std_put_hiwat)
316 stdp->std_put_hiwat = count;
317
318 /* Append the reversed put list to the get list. */
319 KASSERT(*get_tailp == NULL, ("*get_tailp != NULL"));
320 *stdp->std_getp = get_next;
321 stdp->std_getp = get_tailp;
322 stdp->std_get_count += count;
323 stdp->std_get_non_tcp_count += non_tcp_count;
324 }
325
326 static void
sfxge_tx_qreap(struct sfxge_txq * txq)327 sfxge_tx_qreap(struct sfxge_txq *txq)
328 {
329 SFXGE_TXQ_LOCK_ASSERT_OWNED(txq);
330
331 txq->reaped = txq->completed;
332 }
333
334 static void
sfxge_tx_qlist_post(struct sfxge_txq * txq)335 sfxge_tx_qlist_post(struct sfxge_txq *txq)
336 {
337 unsigned int old_added;
338 unsigned int block_level;
339 unsigned int level;
340 int rc;
341
342 SFXGE_TXQ_LOCK_ASSERT_OWNED(txq);
343
344 KASSERT(txq->n_pend_desc != 0, ("txq->n_pend_desc == 0"));
345 KASSERT(txq->n_pend_desc <= txq->max_pkt_desc,
346 ("txq->n_pend_desc too large"));
347 KASSERT(!txq->blocked, ("txq->blocked"));
348
349 old_added = txq->added;
350
351 /* Post the fragment list. */
352 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc, txq->n_pend_desc,
353 txq->reaped, &txq->added);
354 KASSERT(rc == 0, ("efx_tx_qdesc_post() failed"));
355
356 /* If efx_tx_qdesc_post() had to refragment, our information about
357 * buffers to free may be associated with the wrong
358 * descriptors.
359 */
360 KASSERT(txq->added - old_added == txq->n_pend_desc,
361 ("efx_tx_qdesc_post() refragmented descriptors"));
362
363 level = txq->added - txq->reaped;
364 KASSERT(level <= txq->entries, ("overfilled TX queue"));
365
366 /* Clear the fragment list. */
367 txq->n_pend_desc = 0;
368
369 /*
370 * Set the block level to ensure there is space to generate a
371 * large number of descriptors for TSO.
372 */
373 block_level = EFX_TXQ_LIMIT(txq->entries) - txq->max_pkt_desc;
374
375 /* Have we reached the block level? */
376 if (level < block_level)
377 return;
378
379 /* Reap, and check again */
380 sfxge_tx_qreap(txq);
381 level = txq->added - txq->reaped;
382 if (level < block_level)
383 return;
384
385 txq->blocked = 1;
386
387 /*
388 * Avoid a race with completion interrupt handling that could leave
389 * the queue blocked.
390 */
391 mb();
392 sfxge_tx_qreap(txq);
393 level = txq->added - txq->reaped;
394 if (level < block_level) {
395 mb();
396 txq->blocked = 0;
397 }
398 }
399
sfxge_tx_queue_mbuf(struct sfxge_txq * txq,struct mbuf * mbuf)400 static int sfxge_tx_queue_mbuf(struct sfxge_txq *txq, struct mbuf *mbuf)
401 {
402 bus_dmamap_t *used_map;
403 bus_dmamap_t map;
404 bus_dma_segment_t dma_seg[SFXGE_TX_MAPPING_MAX_SEG];
405 unsigned int id;
406 struct sfxge_tx_mapping *stmp;
407 efx_desc_t *desc;
408 int n_dma_seg;
409 int rc;
410 int i;
411 int eop;
412 uint16_t hw_cksum_flags_prev;
413 uint16_t hw_vlan_tci_prev;
414 int n_extra_descs;
415
416 KASSERT(!txq->blocked, ("txq->blocked"));
417
418 #if SFXGE_TX_PARSE_EARLY
419 /*
420 * If software TSO is used, we still need to copy packet header,
421 * even if we have already parsed it early before enqueue.
422 */
423 if ((mbuf->m_pkthdr.csum_flags & CSUM_TSO) &&
424 (txq->tso_fw_assisted == 0))
425 prefetch_read_many(mbuf->m_data);
426 #else
427 /*
428 * Prefetch packet header since we need to parse it and extract
429 * IP ID, TCP sequence number and flags.
430 */
431 if (mbuf->m_pkthdr.csum_flags & CSUM_TSO)
432 prefetch_read_many(mbuf->m_data);
433 #endif
434
435 if (__predict_false(txq->init_state != SFXGE_TXQ_STARTED)) {
436 rc = EINTR;
437 goto reject;
438 }
439
440 /* Load the packet for DMA. */
441 id = txq->added & txq->ptr_mask;
442 stmp = &txq->stmp[id];
443 rc = bus_dmamap_load_mbuf_sg(txq->packet_dma_tag, stmp->map,
444 mbuf, dma_seg, &n_dma_seg, 0);
445 if (rc == EFBIG) {
446 /* Try again. */
447 struct mbuf *new_mbuf = m_collapse(mbuf, M_NOWAIT,
448 SFXGE_TX_MAPPING_MAX_SEG);
449 if (new_mbuf == NULL)
450 goto reject;
451 ++txq->collapses;
452 mbuf = new_mbuf;
453 rc = bus_dmamap_load_mbuf_sg(txq->packet_dma_tag,
454 stmp->map, mbuf,
455 dma_seg, &n_dma_seg, 0);
456 }
457 if (rc != 0)
458 goto reject;
459
460 /* Make the packet visible to the hardware. */
461 bus_dmamap_sync(txq->packet_dma_tag, stmp->map, BUS_DMASYNC_PREWRITE);
462
463 used_map = &stmp->map;
464
465 hw_cksum_flags_prev = txq->hw_cksum_flags;
466 hw_vlan_tci_prev = txq->hw_vlan_tci;
467
468 /*
469 * The order of option descriptors, which are used to leverage VLAN tag
470 * and checksum offloads, might be important. Changing checksum offload
471 * between VLAN option and packet descriptors probably does not work.
472 */
473 n_extra_descs = sfxge_tx_maybe_toggle_cksum_offload(txq, mbuf, &stmp);
474 n_extra_descs += sfxge_tx_maybe_insert_tag(txq, mbuf, &stmp);
475
476 if (mbuf->m_pkthdr.csum_flags & CSUM_TSO) {
477 rc = sfxge_tx_queue_tso(txq, mbuf, dma_seg, n_dma_seg,
478 n_extra_descs);
479 if (rc < 0)
480 goto reject_mapped;
481 stmp = &txq->stmp[(rc - 1) & txq->ptr_mask];
482 } else {
483 /* Add the mapping to the fragment list, and set flags
484 * for the buffer.
485 */
486
487 i = 0;
488 for (;;) {
489 desc = &txq->pend_desc[i + n_extra_descs];
490 eop = (i == n_dma_seg - 1);
491 efx_tx_qdesc_dma_create(txq->common,
492 dma_seg[i].ds_addr,
493 dma_seg[i].ds_len,
494 eop,
495 desc);
496 if (eop)
497 break;
498 i++;
499 sfxge_next_stmp(txq, &stmp);
500 }
501 txq->n_pend_desc = n_dma_seg + n_extra_descs;
502 }
503
504 /*
505 * If the mapping required more than one descriptor
506 * then we need to associate the DMA map with the last
507 * descriptor, not the first.
508 */
509 if (used_map != &stmp->map) {
510 map = stmp->map;
511 stmp->map = *used_map;
512 *used_map = map;
513 }
514
515 stmp->u.mbuf = mbuf;
516 stmp->flags = TX_BUF_UNMAP | TX_BUF_MBUF;
517
518 /* Post the fragment list. */
519 sfxge_tx_qlist_post(txq);
520
521 return (0);
522
523 reject_mapped:
524 txq->hw_vlan_tci = hw_vlan_tci_prev;
525 txq->hw_cksum_flags = hw_cksum_flags_prev;
526 bus_dmamap_unload(txq->packet_dma_tag, *used_map);
527 reject:
528 /* Drop the packet on the floor. */
529 m_freem(mbuf);
530 ++txq->drops;
531
532 return (rc);
533 }
534
535 /*
536 * Drain the deferred packet list into the transmit queue.
537 */
538 static void
sfxge_tx_qdpl_drain(struct sfxge_txq * txq)539 sfxge_tx_qdpl_drain(struct sfxge_txq *txq)
540 {
541 struct sfxge_softc *sc;
542 struct sfxge_tx_dpl *stdp;
543 struct mbuf *mbuf, *next;
544 unsigned int count;
545 unsigned int non_tcp_count;
546 unsigned int pushed;
547 int rc;
548
549 SFXGE_TXQ_LOCK_ASSERT_OWNED(txq);
550
551 sc = txq->sc;
552 stdp = &txq->dpl;
553 pushed = txq->added;
554
555 if (__predict_true(txq->init_state == SFXGE_TXQ_STARTED)) {
556 prefetch_read_many(sc->enp);
557 prefetch_read_many(txq->common);
558 }
559
560 mbuf = stdp->std_get;
561 count = stdp->std_get_count;
562 non_tcp_count = stdp->std_get_non_tcp_count;
563
564 if (count > stdp->std_get_hiwat)
565 stdp->std_get_hiwat = count;
566
567 while (count != 0) {
568 KASSERT(mbuf != NULL, ("mbuf == NULL"));
569
570 next = mbuf->m_nextpkt;
571 mbuf->m_nextpkt = NULL;
572
573 ETHER_BPF_MTAP(sc->ifnet, mbuf); /* packet capture */
574
575 if (next != NULL)
576 prefetch_read_many(next);
577
578 rc = sfxge_tx_queue_mbuf(txq, mbuf);
579 --count;
580 non_tcp_count -= sfxge_is_mbuf_non_tcp(mbuf);
581 mbuf = next;
582 if (rc != 0)
583 continue;
584
585 if (txq->blocked)
586 break;
587
588 /* Push the fragments to the hardware in batches. */
589 if (txq->added - pushed >= SFXGE_TX_BATCH) {
590 efx_tx_qpush(txq->common, txq->added, pushed);
591 pushed = txq->added;
592 }
593 }
594
595 if (count == 0) {
596 KASSERT(mbuf == NULL, ("mbuf != NULL"));
597 KASSERT(non_tcp_count == 0,
598 ("inconsistent TCP/non-TCP detection"));
599 stdp->std_get = NULL;
600 stdp->std_get_count = 0;
601 stdp->std_get_non_tcp_count = 0;
602 stdp->std_getp = &stdp->std_get;
603 } else {
604 stdp->std_get = mbuf;
605 stdp->std_get_count = count;
606 stdp->std_get_non_tcp_count = non_tcp_count;
607 }
608
609 if (txq->added != pushed)
610 efx_tx_qpush(txq->common, txq->added, pushed);
611
612 KASSERT(txq->blocked || stdp->std_get_count == 0,
613 ("queue unblocked but count is non-zero"));
614 }
615
616 #define SFXGE_TX_QDPL_PENDING(_txq) ((_txq)->dpl.std_put != 0)
617
618 /*
619 * Service the deferred packet list.
620 *
621 * NOTE: drops the txq mutex!
622 */
623 static void
sfxge_tx_qdpl_service(struct sfxge_txq * txq)624 sfxge_tx_qdpl_service(struct sfxge_txq *txq)
625 {
626 SFXGE_TXQ_LOCK_ASSERT_OWNED(txq);
627
628 do {
629 if (SFXGE_TX_QDPL_PENDING(txq))
630 sfxge_tx_qdpl_swizzle(txq);
631
632 if (!txq->blocked)
633 sfxge_tx_qdpl_drain(txq);
634
635 SFXGE_TXQ_UNLOCK(txq);
636 } while (SFXGE_TX_QDPL_PENDING(txq) &&
637 SFXGE_TXQ_TRYLOCK(txq));
638 }
639
640 /*
641 * Put a packet on the deferred packet get-list.
642 */
643 static int
sfxge_tx_qdpl_put_locked(struct sfxge_txq * txq,struct mbuf * mbuf)644 sfxge_tx_qdpl_put_locked(struct sfxge_txq *txq, struct mbuf *mbuf)
645 {
646 struct sfxge_tx_dpl *stdp;
647
648 stdp = &txq->dpl;
649
650 KASSERT(mbuf->m_nextpkt == NULL, ("mbuf->m_nextpkt != NULL"));
651
652 SFXGE_TXQ_LOCK_ASSERT_OWNED(txq);
653
654 if (stdp->std_get_count >= stdp->std_get_max) {
655 txq->get_overflow++;
656 return (ENOBUFS);
657 }
658 if (sfxge_is_mbuf_non_tcp(mbuf)) {
659 if (stdp->std_get_non_tcp_count >=
660 stdp->std_get_non_tcp_max) {
661 txq->get_non_tcp_overflow++;
662 return (ENOBUFS);
663 }
664 stdp->std_get_non_tcp_count++;
665 }
666
667 *(stdp->std_getp) = mbuf;
668 stdp->std_getp = &mbuf->m_nextpkt;
669 stdp->std_get_count++;
670
671 return (0);
672 }
673
674 /*
675 * Put a packet on the deferred packet put-list.
676 *
677 * We overload the csum_data field in the mbuf to keep track of this length
678 * because there is no cheap alternative to avoid races.
679 */
680 static int
sfxge_tx_qdpl_put_unlocked(struct sfxge_txq * txq,struct mbuf * mbuf)681 sfxge_tx_qdpl_put_unlocked(struct sfxge_txq *txq, struct mbuf *mbuf)
682 {
683 struct sfxge_tx_dpl *stdp;
684 volatile uintptr_t *putp;
685 uintptr_t old;
686 uintptr_t new;
687 unsigned int put_count;
688
689 KASSERT(mbuf->m_nextpkt == NULL, ("mbuf->m_nextpkt != NULL"));
690
691 SFXGE_TXQ_LOCK_ASSERT_NOTOWNED(txq);
692
693 stdp = &txq->dpl;
694 putp = &stdp->std_put;
695 new = (uintptr_t)mbuf;
696
697 do {
698 old = *putp;
699 if (old != 0) {
700 struct mbuf *mp = (struct mbuf *)old;
701 put_count = mp->m_pkthdr.csum_data;
702 } else
703 put_count = 0;
704 if (put_count >= stdp->std_put_max) {
705 atomic_add_long(&txq->put_overflow, 1);
706 return (ENOBUFS);
707 }
708 mbuf->m_pkthdr.csum_data = put_count + 1;
709 mbuf->m_nextpkt = (void *)old;
710 } while (atomic_cmpset_ptr(putp, old, new) == 0);
711
712 return (0);
713 }
714
715 /*
716 * Called from if_transmit - will try to grab the txq lock and enqueue to the
717 * put list if it succeeds, otherwise try to push onto the defer list if space.
718 */
719 static int
sfxge_tx_packet_add(struct sfxge_txq * txq,struct mbuf * m)720 sfxge_tx_packet_add(struct sfxge_txq *txq, struct mbuf *m)
721 {
722 int rc;
723
724 if (!SFXGE_LINK_UP(txq->sc)) {
725 atomic_add_long(&txq->netdown_drops, 1);
726 return (ENETDOWN);
727 }
728
729 /*
730 * Try to grab the txq lock. If we are able to get the lock,
731 * the packet will be appended to the "get list" of the deferred
732 * packet list. Otherwise, it will be pushed on the "put list".
733 */
734 if (SFXGE_TXQ_TRYLOCK(txq)) {
735 /* First swizzle put-list to get-list to keep order */
736 sfxge_tx_qdpl_swizzle(txq);
737
738 rc = sfxge_tx_qdpl_put_locked(txq, m);
739
740 /* Try to service the list. */
741 sfxge_tx_qdpl_service(txq);
742 /* Lock has been dropped. */
743 } else {
744 rc = sfxge_tx_qdpl_put_unlocked(txq, m);
745
746 /*
747 * Try to grab the lock again.
748 *
749 * If we are able to get the lock, we need to process
750 * the deferred packet list. If we are not able to get
751 * the lock, another thread is processing the list.
752 */
753 if ((rc == 0) && SFXGE_TXQ_TRYLOCK(txq)) {
754 sfxge_tx_qdpl_service(txq);
755 /* Lock has been dropped. */
756 }
757 }
758
759 SFXGE_TXQ_LOCK_ASSERT_NOTOWNED(txq);
760
761 return (rc);
762 }
763
764 static void
sfxge_tx_qdpl_flush(struct sfxge_txq * txq)765 sfxge_tx_qdpl_flush(struct sfxge_txq *txq)
766 {
767 struct sfxge_tx_dpl *stdp = &txq->dpl;
768 struct mbuf *mbuf, *next;
769
770 SFXGE_TXQ_LOCK(txq);
771
772 sfxge_tx_qdpl_swizzle(txq);
773 for (mbuf = stdp->std_get; mbuf != NULL; mbuf = next) {
774 next = mbuf->m_nextpkt;
775 m_freem(mbuf);
776 }
777 stdp->std_get = NULL;
778 stdp->std_get_count = 0;
779 stdp->std_get_non_tcp_count = 0;
780 stdp->std_getp = &stdp->std_get;
781
782 SFXGE_TXQ_UNLOCK(txq);
783 }
784
785 void
sfxge_if_qflush(struct ifnet * ifp)786 sfxge_if_qflush(struct ifnet *ifp)
787 {
788 struct sfxge_softc *sc;
789 unsigned int i;
790
791 sc = ifp->if_softc;
792
793 for (i = 0; i < sc->txq_count; i++)
794 sfxge_tx_qdpl_flush(sc->txq[i]);
795 }
796
797 #if SFXGE_TX_PARSE_EARLY
798
799 /* There is little space for user data in mbuf pkthdr, so we
800 * use l*hlen fields which are not used by the driver otherwise
801 * to store header offsets.
802 * The fields are 8-bit, but it's ok, no header may be longer than 255 bytes.
803 */
804
805
806 #define TSO_MBUF_PROTO(_mbuf) ((_mbuf)->m_pkthdr.PH_loc.sixteen[0])
807 /* We abuse l5hlen here because PH_loc can hold only 64 bits of data */
808 #define TSO_MBUF_FLAGS(_mbuf) ((_mbuf)->m_pkthdr.l5hlen)
809 #define TSO_MBUF_PACKETID(_mbuf) ((_mbuf)->m_pkthdr.PH_loc.sixteen[1])
810 #define TSO_MBUF_SEQNUM(_mbuf) ((_mbuf)->m_pkthdr.PH_loc.thirtytwo[1])
811
sfxge_parse_tx_packet(struct mbuf * mbuf)812 static void sfxge_parse_tx_packet(struct mbuf *mbuf)
813 {
814 struct ether_header *eh = mtod(mbuf, struct ether_header *);
815 const struct tcphdr *th;
816 struct tcphdr th_copy;
817
818 /* Find network protocol and header */
819 TSO_MBUF_PROTO(mbuf) = eh->ether_type;
820 if (TSO_MBUF_PROTO(mbuf) == htons(ETHERTYPE_VLAN)) {
821 struct ether_vlan_header *veh =
822 mtod(mbuf, struct ether_vlan_header *);
823 TSO_MBUF_PROTO(mbuf) = veh->evl_proto;
824 mbuf->m_pkthdr.l2hlen = sizeof(*veh);
825 } else {
826 mbuf->m_pkthdr.l2hlen = sizeof(*eh);
827 }
828
829 /* Find TCP header */
830 if (TSO_MBUF_PROTO(mbuf) == htons(ETHERTYPE_IP)) {
831 const struct ip *iph = (const struct ip *)mtodo(mbuf, mbuf->m_pkthdr.l2hlen);
832
833 KASSERT(iph->ip_p == IPPROTO_TCP,
834 ("TSO required on non-TCP packet"));
835 mbuf->m_pkthdr.l3hlen = mbuf->m_pkthdr.l2hlen + 4 * iph->ip_hl;
836 TSO_MBUF_PACKETID(mbuf) = iph->ip_id;
837 } else {
838 KASSERT(TSO_MBUF_PROTO(mbuf) == htons(ETHERTYPE_IPV6),
839 ("TSO required on non-IP packet"));
840 KASSERT(((const struct ip6_hdr *)mtodo(mbuf, mbuf->m_pkthdr.l2hlen))->ip6_nxt ==
841 IPPROTO_TCP,
842 ("TSO required on non-TCP packet"));
843 mbuf->m_pkthdr.l3hlen = mbuf->m_pkthdr.l2hlen + sizeof(struct ip6_hdr);
844 TSO_MBUF_PACKETID(mbuf) = 0;
845 }
846
847 KASSERT(mbuf->m_len >= mbuf->m_pkthdr.l3hlen,
848 ("network header is fragmented in mbuf"));
849
850 /* We need TCP header including flags (window is the next) */
851 if (mbuf->m_len < mbuf->m_pkthdr.l3hlen + offsetof(struct tcphdr, th_win)) {
852 m_copydata(mbuf, mbuf->m_pkthdr.l3hlen, sizeof(th_copy),
853 (caddr_t)&th_copy);
854 th = &th_copy;
855 } else {
856 th = (const struct tcphdr *)mtodo(mbuf, mbuf->m_pkthdr.l3hlen);
857 }
858
859 mbuf->m_pkthdr.l4hlen = mbuf->m_pkthdr.l3hlen + 4 * th->th_off;
860 TSO_MBUF_SEQNUM(mbuf) = ntohl(th->th_seq);
861
862 /* These flags must not be duplicated */
863 /*
864 * RST should not be duplicated as well, but FreeBSD kernel
865 * generates TSO packets with RST flag. So, do not assert
866 * its absence.
867 */
868 KASSERT(!(th->th_flags & (TH_URG | TH_SYN)),
869 ("incompatible TCP flag 0x%x on TSO packet",
870 th->th_flags & (TH_URG | TH_SYN)));
871 TSO_MBUF_FLAGS(mbuf) = th->th_flags;
872 }
873 #endif
874
875 /*
876 * TX start -- called by the stack.
877 */
878 int
sfxge_if_transmit(struct ifnet * ifp,struct mbuf * m)879 sfxge_if_transmit(struct ifnet *ifp, struct mbuf *m)
880 {
881 struct sfxge_softc *sc;
882 struct sfxge_txq *txq;
883 int rc;
884
885 sc = (struct sfxge_softc *)ifp->if_softc;
886
887 /*
888 * Transmit may be called when interface is up from the kernel
889 * point of view, but not yet up (in progress) from the driver
890 * point of view. I.e. link aggregation bring up.
891 * Transmit may be called when interface is up from the driver
892 * point of view, but already down from the kernel point of
893 * view. I.e. Rx when interface shutdown is in progress.
894 */
895 KASSERT((ifp->if_flags & IFF_UP) || (sc->if_flags & IFF_UP),
896 ("interface not up"));
897
898 /* Pick the desired transmit queue. */
899 if (sc->txq_dynamic_cksum_toggle_supported |
900 (m->m_pkthdr.csum_flags &
901 (CSUM_DELAY_DATA | CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_TSO))) {
902 int index = 0;
903
904 #ifdef RSS
905 uint32_t bucket_id;
906
907 /*
908 * Select a TX queue which matches the corresponding
909 * RX queue for the hash in order to assign both
910 * TX and RX parts of the flow to the same CPU
911 */
912 if (rss_m2bucket(m, &bucket_id) == 0)
913 index = bucket_id % (sc->txq_count - (SFXGE_TXQ_NTYPES - 1));
914 #else
915 /* check if flowid is set */
916 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) {
917 uint32_t hash = m->m_pkthdr.flowid;
918 uint32_t idx = hash % nitems(sc->rx_indir_table);
919
920 index = sc->rx_indir_table[idx];
921 }
922 #endif
923 #if SFXGE_TX_PARSE_EARLY
924 if (m->m_pkthdr.csum_flags & CSUM_TSO)
925 sfxge_parse_tx_packet(m);
926 #endif
927 index += (sc->txq_dynamic_cksum_toggle_supported == B_FALSE) ?
928 SFXGE_TXQ_IP_TCP_UDP_CKSUM : 0;
929 txq = sc->txq[index];
930 } else if (m->m_pkthdr.csum_flags & CSUM_DELAY_IP) {
931 txq = sc->txq[SFXGE_TXQ_IP_CKSUM];
932 } else {
933 txq = sc->txq[SFXGE_TXQ_NON_CKSUM];
934 }
935
936 rc = sfxge_tx_packet_add(txq, m);
937 if (rc != 0)
938 m_freem(m);
939
940 return (rc);
941 }
942
943 /*
944 * Software "TSO". Not quite as good as doing it in hardware, but
945 * still faster than segmenting in the stack.
946 */
947
948 struct sfxge_tso_state {
949 /* Output position */
950 unsigned out_len; /* Remaining length in current segment */
951 unsigned seqnum; /* Current sequence number */
952 unsigned packet_space; /* Remaining space in current packet */
953 unsigned segs_space; /* Remaining number of DMA segments
954 for the packet (FATSOv2 only) */
955
956 /* Input position */
957 uint64_t dma_addr; /* DMA address of current position */
958 unsigned in_len; /* Remaining length in current mbuf */
959
960 const struct mbuf *mbuf; /* Input mbuf (head of chain) */
961 u_short protocol; /* Network protocol (after VLAN decap) */
962 ssize_t nh_off; /* Offset of network header */
963 ssize_t tcph_off; /* Offset of TCP header */
964 unsigned header_len; /* Number of bytes of header */
965 unsigned seg_size; /* TCP segment size */
966 int fw_assisted; /* Use FW-assisted TSO */
967 u_short packet_id; /* IPv4 packet ID from the original packet */
968 uint8_t tcp_flags; /* TCP flags */
969 efx_desc_t header_desc; /* Precomputed header descriptor for
970 * FW-assisted TSO */
971 };
972
973 #if !SFXGE_TX_PARSE_EARLY
tso_iph(const struct sfxge_tso_state * tso)974 static const struct ip *tso_iph(const struct sfxge_tso_state *tso)
975 {
976 KASSERT(tso->protocol == htons(ETHERTYPE_IP),
977 ("tso_iph() in non-IPv4 state"));
978 return (const struct ip *)(tso->mbuf->m_data + tso->nh_off);
979 }
980
tso_ip6h(const struct sfxge_tso_state * tso)981 static __unused const struct ip6_hdr *tso_ip6h(const struct sfxge_tso_state *tso)
982 {
983 KASSERT(tso->protocol == htons(ETHERTYPE_IPV6),
984 ("tso_ip6h() in non-IPv6 state"));
985 return (const struct ip6_hdr *)(tso->mbuf->m_data + tso->nh_off);
986 }
987
tso_tcph(const struct sfxge_tso_state * tso)988 static const struct tcphdr *tso_tcph(const struct sfxge_tso_state *tso)
989 {
990 return (const struct tcphdr *)(tso->mbuf->m_data + tso->tcph_off);
991 }
992 #endif
993
994
995 /* Size of preallocated TSO header buffers. Larger blocks must be
996 * allocated from the heap.
997 */
998 #define TSOH_STD_SIZE 128
999
1000 /* At most half the descriptors in the queue at any time will refer to
1001 * a TSO header buffer, since they must always be followed by a
1002 * payload descriptor referring to an mbuf.
1003 */
1004 #define TSOH_COUNT(_txq_entries) ((_txq_entries) / 2u)
1005 #define TSOH_PER_PAGE (PAGE_SIZE / TSOH_STD_SIZE)
1006 #define TSOH_PAGE_COUNT(_txq_entries) \
1007 howmany(TSOH_COUNT(_txq_entries), TSOH_PER_PAGE)
1008
tso_init(struct sfxge_txq * txq)1009 static int tso_init(struct sfxge_txq *txq)
1010 {
1011 struct sfxge_softc *sc = txq->sc;
1012 unsigned int tsoh_page_count = TSOH_PAGE_COUNT(sc->txq_entries);
1013 int i, rc;
1014
1015 /* Allocate TSO header buffers */
1016 txq->tsoh_buffer = malloc(tsoh_page_count * sizeof(txq->tsoh_buffer[0]),
1017 M_SFXGE, M_WAITOK);
1018
1019 for (i = 0; i < tsoh_page_count; i++) {
1020 rc = sfxge_dma_alloc(sc, PAGE_SIZE, &txq->tsoh_buffer[i]);
1021 if (rc != 0)
1022 goto fail;
1023 }
1024
1025 return (0);
1026
1027 fail:
1028 while (i-- > 0)
1029 sfxge_dma_free(&txq->tsoh_buffer[i]);
1030 free(txq->tsoh_buffer, M_SFXGE);
1031 txq->tsoh_buffer = NULL;
1032 return (rc);
1033 }
1034
tso_fini(struct sfxge_txq * txq)1035 static void tso_fini(struct sfxge_txq *txq)
1036 {
1037 int i;
1038
1039 if (txq->tsoh_buffer != NULL) {
1040 for (i = 0; i < TSOH_PAGE_COUNT(txq->sc->txq_entries); i++)
1041 sfxge_dma_free(&txq->tsoh_buffer[i]);
1042 free(txq->tsoh_buffer, M_SFXGE);
1043 }
1044 }
1045
tso_start(struct sfxge_txq * txq,struct sfxge_tso_state * tso,const bus_dma_segment_t * hdr_dma_seg,struct mbuf * mbuf)1046 static void tso_start(struct sfxge_txq *txq, struct sfxge_tso_state *tso,
1047 const bus_dma_segment_t *hdr_dma_seg,
1048 struct mbuf *mbuf)
1049 {
1050 const efx_nic_cfg_t *encp = efx_nic_cfg_get(txq->sc->enp);
1051 #if !SFXGE_TX_PARSE_EARLY
1052 struct ether_header *eh = mtod(mbuf, struct ether_header *);
1053 const struct tcphdr *th;
1054 struct tcphdr th_copy;
1055 #endif
1056
1057 tso->fw_assisted = txq->tso_fw_assisted;
1058 tso->mbuf = mbuf;
1059
1060 /* Find network protocol and header */
1061 #if !SFXGE_TX_PARSE_EARLY
1062 tso->protocol = eh->ether_type;
1063 if (tso->protocol == htons(ETHERTYPE_VLAN)) {
1064 struct ether_vlan_header *veh =
1065 mtod(mbuf, struct ether_vlan_header *);
1066 tso->protocol = veh->evl_proto;
1067 tso->nh_off = sizeof(*veh);
1068 } else {
1069 tso->nh_off = sizeof(*eh);
1070 }
1071 #else
1072 tso->protocol = TSO_MBUF_PROTO(mbuf);
1073 tso->nh_off = mbuf->m_pkthdr.l2hlen;
1074 tso->tcph_off = mbuf->m_pkthdr.l3hlen;
1075 tso->packet_id = ntohs(TSO_MBUF_PACKETID(mbuf));
1076 #endif
1077
1078 #if !SFXGE_TX_PARSE_EARLY
1079 /* Find TCP header */
1080 if (tso->protocol == htons(ETHERTYPE_IP)) {
1081 KASSERT(tso_iph(tso)->ip_p == IPPROTO_TCP,
1082 ("TSO required on non-TCP packet"));
1083 tso->tcph_off = tso->nh_off + 4 * tso_iph(tso)->ip_hl;
1084 tso->packet_id = ntohs(tso_iph(tso)->ip_id);
1085 } else {
1086 KASSERT(tso->protocol == htons(ETHERTYPE_IPV6),
1087 ("TSO required on non-IP packet"));
1088 KASSERT(tso_ip6h(tso)->ip6_nxt == IPPROTO_TCP,
1089 ("TSO required on non-TCP packet"));
1090 tso->tcph_off = tso->nh_off + sizeof(struct ip6_hdr);
1091 tso->packet_id = 0;
1092 }
1093 #endif
1094
1095
1096 if (tso->fw_assisted &&
1097 __predict_false(tso->tcph_off >
1098 encp->enc_tx_tso_tcp_header_offset_limit)) {
1099 tso->fw_assisted = 0;
1100 }
1101
1102
1103 #if !SFXGE_TX_PARSE_EARLY
1104 KASSERT(mbuf->m_len >= tso->tcph_off,
1105 ("network header is fragmented in mbuf"));
1106 /* We need TCP header including flags (window is the next) */
1107 if (mbuf->m_len < tso->tcph_off + offsetof(struct tcphdr, th_win)) {
1108 m_copydata(tso->mbuf, tso->tcph_off, sizeof(th_copy),
1109 (caddr_t)&th_copy);
1110 th = &th_copy;
1111 } else {
1112 th = tso_tcph(tso);
1113 }
1114 tso->header_len = tso->tcph_off + 4 * th->th_off;
1115 #else
1116 tso->header_len = mbuf->m_pkthdr.l4hlen;
1117 #endif
1118 tso->seg_size = mbuf->m_pkthdr.tso_segsz;
1119
1120 #if !SFXGE_TX_PARSE_EARLY
1121 tso->seqnum = ntohl(th->th_seq);
1122
1123 /* These flags must not be duplicated */
1124 /*
1125 * RST should not be duplicated as well, but FreeBSD kernel
1126 * generates TSO packets with RST flag. So, do not assert
1127 * its absence.
1128 */
1129 KASSERT(!(th->th_flags & (TH_URG | TH_SYN)),
1130 ("incompatible TCP flag 0x%x on TSO packet",
1131 th->th_flags & (TH_URG | TH_SYN)));
1132 tso->tcp_flags = th->th_flags;
1133 #else
1134 tso->seqnum = TSO_MBUF_SEQNUM(mbuf);
1135 tso->tcp_flags = TSO_MBUF_FLAGS(mbuf);
1136 #endif
1137
1138 tso->out_len = mbuf->m_pkthdr.len - tso->header_len;
1139
1140 if (tso->fw_assisted) {
1141 if (hdr_dma_seg->ds_len >= tso->header_len)
1142 efx_tx_qdesc_dma_create(txq->common,
1143 hdr_dma_seg->ds_addr,
1144 tso->header_len,
1145 B_FALSE,
1146 &tso->header_desc);
1147 else
1148 tso->fw_assisted = 0;
1149 }
1150 }
1151
1152 /*
1153 * tso_fill_packet_with_fragment - form descriptors for the current fragment
1154 *
1155 * Form descriptors for the current fragment, until we reach the end
1156 * of fragment or end-of-packet. Return 0 on success, 1 if not enough
1157 * space.
1158 */
tso_fill_packet_with_fragment(struct sfxge_txq * txq,struct sfxge_tso_state * tso)1159 static void tso_fill_packet_with_fragment(struct sfxge_txq *txq,
1160 struct sfxge_tso_state *tso)
1161 {
1162 efx_desc_t *desc;
1163 int n;
1164 uint64_t dma_addr = tso->dma_addr;
1165 boolean_t eop;
1166
1167 if (tso->in_len == 0 || tso->packet_space == 0)
1168 return;
1169
1170 KASSERT(tso->in_len > 0, ("TSO input length went negative"));
1171 KASSERT(tso->packet_space > 0, ("TSO packet space went negative"));
1172
1173 if (tso->fw_assisted & SFXGE_FATSOV2) {
1174 n = tso->in_len;
1175 tso->out_len -= n;
1176 tso->seqnum += n;
1177 tso->in_len = 0;
1178 if (n < tso->packet_space) {
1179 tso->packet_space -= n;
1180 tso->segs_space--;
1181 } else {
1182 tso->packet_space = tso->seg_size -
1183 (n - tso->packet_space) % tso->seg_size;
1184 tso->segs_space =
1185 EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX - 1 -
1186 (tso->packet_space != tso->seg_size);
1187 }
1188 } else {
1189 n = min(tso->in_len, tso->packet_space);
1190 tso->packet_space -= n;
1191 tso->out_len -= n;
1192 tso->dma_addr += n;
1193 tso->in_len -= n;
1194 }
1195
1196 /*
1197 * It is OK to use binary OR below to avoid extra branching
1198 * since all conditions may always be checked.
1199 */
1200 eop = (tso->out_len == 0) | (tso->packet_space == 0) |
1201 (tso->segs_space == 0);
1202
1203 desc = &txq->pend_desc[txq->n_pend_desc++];
1204 efx_tx_qdesc_dma_create(txq->common, dma_addr, n, eop, desc);
1205 }
1206
1207 /* Callback from bus_dmamap_load() for long TSO headers. */
tso_map_long_header(void * dma_addr_ret,bus_dma_segment_t * segs,int nseg,int error)1208 static void tso_map_long_header(void *dma_addr_ret,
1209 bus_dma_segment_t *segs, int nseg,
1210 int error)
1211 {
1212 *(uint64_t *)dma_addr_ret = ((__predict_true(error == 0) &&
1213 __predict_true(nseg == 1)) ?
1214 segs->ds_addr : 0);
1215 }
1216
1217 /*
1218 * tso_start_new_packet - generate a new header and prepare for the new packet
1219 *
1220 * Generate a new header and prepare for the new packet. Return 0 on
1221 * success, or an error code if failed to alloc header.
1222 */
tso_start_new_packet(struct sfxge_txq * txq,struct sfxge_tso_state * tso,unsigned int * idp)1223 static int tso_start_new_packet(struct sfxge_txq *txq,
1224 struct sfxge_tso_state *tso,
1225 unsigned int *idp)
1226 {
1227 unsigned int id = *idp;
1228 struct tcphdr *tsoh_th;
1229 unsigned ip_length;
1230 caddr_t header;
1231 uint64_t dma_addr;
1232 bus_dmamap_t map;
1233 efx_desc_t *desc;
1234 int rc;
1235
1236 if (tso->fw_assisted) {
1237 if (tso->fw_assisted & SFXGE_FATSOV2) {
1238 /* Add 2 FATSOv2 option descriptors */
1239 desc = &txq->pend_desc[txq->n_pend_desc];
1240 efx_tx_qdesc_tso2_create(txq->common,
1241 tso->packet_id,
1242 tso->seqnum,
1243 tso->seg_size,
1244 desc,
1245 EFX_TX_FATSOV2_OPT_NDESCS);
1246 desc += EFX_TX_FATSOV2_OPT_NDESCS;
1247 txq->n_pend_desc += EFX_TX_FATSOV2_OPT_NDESCS;
1248 KASSERT(txq->stmp[id].flags == 0, ("stmp flags are not 0"));
1249 id = (id + EFX_TX_FATSOV2_OPT_NDESCS) & txq->ptr_mask;
1250
1251 tso->segs_space =
1252 EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX - 1;
1253 } else {
1254 uint8_t tcp_flags = tso->tcp_flags;
1255
1256 if (tso->out_len > tso->seg_size)
1257 tcp_flags &= ~(TH_FIN | TH_PUSH);
1258
1259 /* Add FATSOv1 option descriptor */
1260 desc = &txq->pend_desc[txq->n_pend_desc++];
1261 efx_tx_qdesc_tso_create(txq->common,
1262 tso->packet_id,
1263 tso->seqnum,
1264 tcp_flags,
1265 desc++);
1266 KASSERT(txq->stmp[id].flags == 0, ("stmp flags are not 0"));
1267 id = (id + 1) & txq->ptr_mask;
1268
1269 tso->seqnum += tso->seg_size;
1270 tso->segs_space = UINT_MAX;
1271 }
1272
1273 /* Header DMA descriptor */
1274 *desc = tso->header_desc;
1275 txq->n_pend_desc++;
1276 KASSERT(txq->stmp[id].flags == 0, ("stmp flags are not 0"));
1277 id = (id + 1) & txq->ptr_mask;
1278 } else {
1279 /* Allocate a DMA-mapped header buffer. */
1280 if (__predict_true(tso->header_len <= TSOH_STD_SIZE)) {
1281 unsigned int page_index = (id / 2) / TSOH_PER_PAGE;
1282 unsigned int buf_index = (id / 2) % TSOH_PER_PAGE;
1283
1284 header = (txq->tsoh_buffer[page_index].esm_base +
1285 buf_index * TSOH_STD_SIZE);
1286 dma_addr = (txq->tsoh_buffer[page_index].esm_addr +
1287 buf_index * TSOH_STD_SIZE);
1288 map = txq->tsoh_buffer[page_index].esm_map;
1289
1290 KASSERT(txq->stmp[id].flags == 0,
1291 ("stmp flags are not 0"));
1292 } else {
1293 struct sfxge_tx_mapping *stmp = &txq->stmp[id];
1294
1295 /* We cannot use bus_dmamem_alloc() as that may sleep */
1296 header = malloc(tso->header_len, M_SFXGE, M_NOWAIT);
1297 if (__predict_false(!header))
1298 return (ENOMEM);
1299 rc = bus_dmamap_load(txq->packet_dma_tag, stmp->map,
1300 header, tso->header_len,
1301 tso_map_long_header, &dma_addr,
1302 BUS_DMA_NOWAIT);
1303 if (__predict_false(dma_addr == 0)) {
1304 if (rc == 0) {
1305 /* Succeeded but got >1 segment */
1306 bus_dmamap_unload(txq->packet_dma_tag,
1307 stmp->map);
1308 rc = EINVAL;
1309 }
1310 free(header, M_SFXGE);
1311 return (rc);
1312 }
1313 map = stmp->map;
1314
1315 txq->tso_long_headers++;
1316 stmp->u.heap_buf = header;
1317 stmp->flags = TX_BUF_UNMAP;
1318 }
1319
1320 tsoh_th = (struct tcphdr *)(header + tso->tcph_off);
1321
1322 /* Copy and update the headers. */
1323 m_copydata(tso->mbuf, 0, tso->header_len, header);
1324
1325 tsoh_th->th_seq = htonl(tso->seqnum);
1326 tso->seqnum += tso->seg_size;
1327 if (tso->out_len > tso->seg_size) {
1328 /* This packet will not finish the TSO burst. */
1329 ip_length = tso->header_len - tso->nh_off + tso->seg_size;
1330 tsoh_th->th_flags &= ~(TH_FIN | TH_PUSH);
1331 } else {
1332 /* This packet will be the last in the TSO burst. */
1333 ip_length = tso->header_len - tso->nh_off + tso->out_len;
1334 }
1335
1336 if (tso->protocol == htons(ETHERTYPE_IP)) {
1337 struct ip *tsoh_iph = (struct ip *)(header + tso->nh_off);
1338 tsoh_iph->ip_len = htons(ip_length);
1339 /* XXX We should increment ip_id, but FreeBSD doesn't
1340 * currently allocate extra IDs for multiple segments.
1341 */
1342 } else {
1343 struct ip6_hdr *tsoh_iph =
1344 (struct ip6_hdr *)(header + tso->nh_off);
1345 tsoh_iph->ip6_plen = htons(ip_length - sizeof(*tsoh_iph));
1346 }
1347
1348 /* Make the header visible to the hardware. */
1349 bus_dmamap_sync(txq->packet_dma_tag, map, BUS_DMASYNC_PREWRITE);
1350
1351 /* Form a descriptor for this header. */
1352 desc = &txq->pend_desc[txq->n_pend_desc++];
1353 efx_tx_qdesc_dma_create(txq->common,
1354 dma_addr,
1355 tso->header_len,
1356 0,
1357 desc);
1358 id = (id + 1) & txq->ptr_mask;
1359
1360 tso->segs_space = UINT_MAX;
1361 }
1362 tso->packet_space = tso->seg_size;
1363 txq->tso_packets++;
1364 *idp = id;
1365
1366 return (0);
1367 }
1368
1369 static int
sfxge_tx_queue_tso(struct sfxge_txq * txq,struct mbuf * mbuf,const bus_dma_segment_t * dma_seg,int n_dma_seg,int n_extra_descs)1370 sfxge_tx_queue_tso(struct sfxge_txq *txq, struct mbuf *mbuf,
1371 const bus_dma_segment_t *dma_seg, int n_dma_seg,
1372 int n_extra_descs)
1373 {
1374 struct sfxge_tso_state tso;
1375 unsigned int id;
1376 unsigned skipped = 0;
1377
1378 tso_start(txq, &tso, dma_seg, mbuf);
1379
1380 while (dma_seg->ds_len + skipped <= tso.header_len) {
1381 skipped += dma_seg->ds_len;
1382 --n_dma_seg;
1383 KASSERT(n_dma_seg, ("no payload found in TSO packet"));
1384 ++dma_seg;
1385 }
1386 tso.in_len = dma_seg->ds_len - (tso.header_len - skipped);
1387 tso.dma_addr = dma_seg->ds_addr + (tso.header_len - skipped);
1388
1389 id = (txq->added + n_extra_descs) & txq->ptr_mask;
1390 if (__predict_false(tso_start_new_packet(txq, &tso, &id)))
1391 return (-1);
1392
1393 while (1) {
1394 tso_fill_packet_with_fragment(txq, &tso);
1395 /* Exactly one DMA descriptor is added */
1396 KASSERT(txq->stmp[id].flags == 0, ("stmp flags are not 0"));
1397 id = (id + 1) & txq->ptr_mask;
1398
1399 /* Move onto the next fragment? */
1400 if (tso.in_len == 0) {
1401 --n_dma_seg;
1402 if (n_dma_seg == 0)
1403 break;
1404 ++dma_seg;
1405 tso.in_len = dma_seg->ds_len;
1406 tso.dma_addr = dma_seg->ds_addr;
1407 }
1408
1409 /* End of packet? */
1410 if ((tso.packet_space == 0) | (tso.segs_space == 0)) {
1411 unsigned int n_fatso_opt_desc =
1412 (tso.fw_assisted & SFXGE_FATSOV2) ?
1413 EFX_TX_FATSOV2_OPT_NDESCS :
1414 (tso.fw_assisted & SFXGE_FATSOV1) ? 1 : 0;
1415
1416 /* If the queue is now full due to tiny MSS,
1417 * or we can't create another header, discard
1418 * the remainder of the input mbuf but do not
1419 * roll back the work we have done.
1420 */
1421 if (txq->n_pend_desc + n_fatso_opt_desc +
1422 1 /* header */ + n_dma_seg > txq->max_pkt_desc) {
1423 txq->tso_pdrop_too_many++;
1424 break;
1425 }
1426 if (__predict_false(tso_start_new_packet(txq, &tso,
1427 &id))) {
1428 txq->tso_pdrop_no_rsrc++;
1429 break;
1430 }
1431 }
1432 }
1433
1434 txq->tso_bursts++;
1435 return (id);
1436 }
1437
1438 static void
sfxge_tx_qunblock(struct sfxge_txq * txq)1439 sfxge_tx_qunblock(struct sfxge_txq *txq)
1440 {
1441 struct sfxge_softc *sc;
1442 struct sfxge_evq *evq;
1443
1444 sc = txq->sc;
1445 evq = sc->evq[txq->evq_index];
1446
1447 SFXGE_EVQ_LOCK_ASSERT_OWNED(evq);
1448
1449 if (__predict_false(txq->init_state != SFXGE_TXQ_STARTED))
1450 return;
1451
1452 SFXGE_TXQ_LOCK(txq);
1453
1454 if (txq->blocked) {
1455 unsigned int level;
1456
1457 level = txq->added - txq->completed;
1458 if (level <= SFXGE_TXQ_UNBLOCK_LEVEL(txq->entries)) {
1459 /* reaped must be in sync with blocked */
1460 sfxge_tx_qreap(txq);
1461 txq->blocked = 0;
1462 }
1463 }
1464
1465 sfxge_tx_qdpl_service(txq);
1466 /* note: lock has been dropped */
1467 }
1468
1469 void
sfxge_tx_qflush_done(struct sfxge_txq * txq)1470 sfxge_tx_qflush_done(struct sfxge_txq *txq)
1471 {
1472
1473 txq->flush_state = SFXGE_FLUSH_DONE;
1474 }
1475
1476 static void
sfxge_tx_qstop(struct sfxge_softc * sc,unsigned int index)1477 sfxge_tx_qstop(struct sfxge_softc *sc, unsigned int index)
1478 {
1479 struct sfxge_txq *txq;
1480 struct sfxge_evq *evq;
1481 unsigned int count;
1482
1483 SFXGE_ADAPTER_LOCK_ASSERT_OWNED(sc);
1484
1485 txq = sc->txq[index];
1486 evq = sc->evq[txq->evq_index];
1487
1488 SFXGE_EVQ_LOCK(evq);
1489 SFXGE_TXQ_LOCK(txq);
1490
1491 KASSERT(txq->init_state == SFXGE_TXQ_STARTED,
1492 ("txq->init_state != SFXGE_TXQ_STARTED"));
1493
1494 txq->init_state = SFXGE_TXQ_INITIALIZED;
1495
1496 if (txq->flush_state != SFXGE_FLUSH_DONE) {
1497 txq->flush_state = SFXGE_FLUSH_PENDING;
1498
1499 SFXGE_EVQ_UNLOCK(evq);
1500 SFXGE_TXQ_UNLOCK(txq);
1501
1502 /* Flush the transmit queue. */
1503 if (efx_tx_qflush(txq->common) != 0) {
1504 log(LOG_ERR, "%s: Flushing Tx queue %u failed\n",
1505 device_get_nameunit(sc->dev), index);
1506 txq->flush_state = SFXGE_FLUSH_DONE;
1507 } else {
1508 count = 0;
1509 do {
1510 /* Spin for 100ms. */
1511 DELAY(100000);
1512 if (txq->flush_state != SFXGE_FLUSH_PENDING)
1513 break;
1514 } while (++count < 20);
1515 }
1516 SFXGE_EVQ_LOCK(evq);
1517 SFXGE_TXQ_LOCK(txq);
1518
1519 KASSERT(txq->flush_state != SFXGE_FLUSH_FAILED,
1520 ("txq->flush_state == SFXGE_FLUSH_FAILED"));
1521
1522 if (txq->flush_state != SFXGE_FLUSH_DONE) {
1523 /* Flush timeout */
1524 log(LOG_ERR, "%s: Cannot flush Tx queue %u\n",
1525 device_get_nameunit(sc->dev), index);
1526 txq->flush_state = SFXGE_FLUSH_DONE;
1527 }
1528 }
1529
1530 txq->blocked = 0;
1531 txq->pending = txq->added;
1532
1533 sfxge_tx_qcomplete(txq, evq);
1534 KASSERT(txq->completed == txq->added,
1535 ("txq->completed != txq->added"));
1536
1537 sfxge_tx_qreap(txq);
1538 KASSERT(txq->reaped == txq->completed,
1539 ("txq->reaped != txq->completed"));
1540
1541 txq->added = 0;
1542 txq->pending = 0;
1543 txq->completed = 0;
1544 txq->reaped = 0;
1545
1546 /* Destroy the common code transmit queue. */
1547 efx_tx_qdestroy(txq->common);
1548 txq->common = NULL;
1549
1550 efx_sram_buf_tbl_clear(sc->enp, txq->buf_base_id,
1551 EFX_TXQ_NBUFS(sc->txq_entries));
1552
1553 txq->hw_cksum_flags = 0;
1554
1555 SFXGE_EVQ_UNLOCK(evq);
1556 SFXGE_TXQ_UNLOCK(txq);
1557 }
1558
1559 /*
1560 * Estimate maximum number of Tx descriptors required for TSO packet.
1561 * With minimum MSS and maximum mbuf length we might need more (even
1562 * than a ring-ful of descriptors), but this should not happen in
1563 * practice except due to deliberate attack. In that case we will
1564 * truncate the output at a packet boundary.
1565 */
1566 static unsigned int
sfxge_tx_max_pkt_desc(const struct sfxge_softc * sc,enum sfxge_txq_type type,unsigned int tso_fw_assisted)1567 sfxge_tx_max_pkt_desc(const struct sfxge_softc *sc, enum sfxge_txq_type type,
1568 unsigned int tso_fw_assisted)
1569 {
1570 /* One descriptor for every input fragment */
1571 unsigned int max_descs = SFXGE_TX_MAPPING_MAX_SEG;
1572 unsigned int sw_tso_max_descs;
1573 unsigned int fa_tso_v1_max_descs = 0;
1574 unsigned int fa_tso_v2_max_descs = 0;
1575
1576 /* Checksum offload Tx option descriptor may be required */
1577 if (sc->txq_dynamic_cksum_toggle_supported)
1578 max_descs++;
1579
1580 /* VLAN tagging Tx option descriptor may be required */
1581 if (efx_nic_cfg_get(sc->enp)->enc_hw_tx_insert_vlan_enabled)
1582 max_descs++;
1583
1584 if (type == SFXGE_TXQ_IP_TCP_UDP_CKSUM) {
1585 /*
1586 * Plus header and payload descriptor for each output segment.
1587 * Minus one since header fragment is already counted.
1588 * Even if FATSO is used, we should be ready to fallback
1589 * to do it in the driver.
1590 */
1591 sw_tso_max_descs = SFXGE_TSO_MAX_SEGS * 2 - 1;
1592
1593 /* FW assisted TSOv1 requires one more descriptor per segment
1594 * in comparison to SW TSO */
1595 if (tso_fw_assisted & SFXGE_FATSOV1)
1596 fa_tso_v1_max_descs =
1597 sw_tso_max_descs + SFXGE_TSO_MAX_SEGS;
1598
1599 /* FW assisted TSOv2 requires 3 (2 FATSO plus header) extra
1600 * descriptors per superframe limited by number of DMA fetches
1601 * per packet. The first packet header is already counted.
1602 */
1603 if (tso_fw_assisted & SFXGE_FATSOV2) {
1604 fa_tso_v2_max_descs =
1605 howmany(SFXGE_TX_MAPPING_MAX_SEG,
1606 EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX - 1) *
1607 (EFX_TX_FATSOV2_OPT_NDESCS + 1) - 1;
1608 }
1609
1610 max_descs += MAX(sw_tso_max_descs,
1611 MAX(fa_tso_v1_max_descs, fa_tso_v2_max_descs));
1612 }
1613
1614 return (max_descs);
1615 }
1616
1617 static int
sfxge_tx_qstart(struct sfxge_softc * sc,unsigned int index)1618 sfxge_tx_qstart(struct sfxge_softc *sc, unsigned int index)
1619 {
1620 struct sfxge_txq *txq;
1621 efsys_mem_t *esmp;
1622 uint16_t flags;
1623 unsigned int tso_fw_assisted;
1624 unsigned int label;
1625 struct sfxge_evq *evq;
1626 unsigned int desc_index;
1627 int rc;
1628
1629 SFXGE_ADAPTER_LOCK_ASSERT_OWNED(sc);
1630
1631 txq = sc->txq[index];
1632 esmp = &txq->mem;
1633 evq = sc->evq[txq->evq_index];
1634
1635 KASSERT(txq->init_state == SFXGE_TXQ_INITIALIZED,
1636 ("txq->init_state != SFXGE_TXQ_INITIALIZED"));
1637 KASSERT(evq->init_state == SFXGE_EVQ_STARTED,
1638 ("evq->init_state != SFXGE_EVQ_STARTED"));
1639
1640 /* Program the buffer table. */
1641 if ((rc = efx_sram_buf_tbl_set(sc->enp, txq->buf_base_id, esmp,
1642 EFX_TXQ_NBUFS(sc->txq_entries))) != 0)
1643 return (rc);
1644
1645 /* Determine the kind of queue we are creating. */
1646 tso_fw_assisted = 0;
1647 switch (txq->type) {
1648 case SFXGE_TXQ_NON_CKSUM:
1649 flags = 0;
1650 break;
1651 case SFXGE_TXQ_IP_CKSUM:
1652 flags = EFX_TXQ_CKSUM_IPV4;
1653 break;
1654 case SFXGE_TXQ_IP_TCP_UDP_CKSUM:
1655 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
1656 tso_fw_assisted = sc->tso_fw_assisted;
1657 if (tso_fw_assisted & SFXGE_FATSOV2)
1658 flags |= EFX_TXQ_FATSOV2;
1659 break;
1660 default:
1661 KASSERT(0, ("Impossible TX queue"));
1662 flags = 0;
1663 break;
1664 }
1665
1666 label = (sc->txq_dynamic_cksum_toggle_supported) ? 0 : txq->type;
1667
1668 /* Create the common code transmit queue. */
1669 if ((rc = efx_tx_qcreate(sc->enp, index, label, esmp,
1670 sc->txq_entries, txq->buf_base_id, flags, evq->common,
1671 &txq->common, &desc_index)) != 0) {
1672 /* Retry if no FATSOv2 resources, otherwise fail */
1673 if ((rc != ENOSPC) || (~flags & EFX_TXQ_FATSOV2))
1674 goto fail;
1675
1676 /* Looks like all FATSOv2 contexts are used */
1677 flags &= ~EFX_TXQ_FATSOV2;
1678 tso_fw_assisted &= ~SFXGE_FATSOV2;
1679 if ((rc = efx_tx_qcreate(sc->enp, index, label, esmp,
1680 sc->txq_entries, txq->buf_base_id, flags, evq->common,
1681 &txq->common, &desc_index)) != 0)
1682 goto fail;
1683 }
1684
1685 /* Initialise queue descriptor indexes */
1686 txq->added = txq->pending = txq->completed = txq->reaped = desc_index;
1687
1688 SFXGE_TXQ_LOCK(txq);
1689
1690 /* Enable the transmit queue. */
1691 efx_tx_qenable(txq->common);
1692
1693 txq->init_state = SFXGE_TXQ_STARTED;
1694 txq->flush_state = SFXGE_FLUSH_REQUIRED;
1695 txq->tso_fw_assisted = tso_fw_assisted;
1696
1697 txq->max_pkt_desc = sfxge_tx_max_pkt_desc(sc, txq->type,
1698 tso_fw_assisted);
1699
1700 txq->hw_vlan_tci = 0;
1701
1702 txq->hw_cksum_flags = flags &
1703 (EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP);
1704
1705 SFXGE_TXQ_UNLOCK(txq);
1706
1707 return (0);
1708
1709 fail:
1710 efx_sram_buf_tbl_clear(sc->enp, txq->buf_base_id,
1711 EFX_TXQ_NBUFS(sc->txq_entries));
1712 return (rc);
1713 }
1714
1715 void
sfxge_tx_stop(struct sfxge_softc * sc)1716 sfxge_tx_stop(struct sfxge_softc *sc)
1717 {
1718 int index;
1719
1720 index = sc->txq_count;
1721 while (--index >= 0)
1722 sfxge_tx_qstop(sc, index);
1723
1724 /* Tear down the transmit module */
1725 efx_tx_fini(sc->enp);
1726 }
1727
1728 int
sfxge_tx_start(struct sfxge_softc * sc)1729 sfxge_tx_start(struct sfxge_softc *sc)
1730 {
1731 int index;
1732 int rc;
1733
1734 /* Initialize the common code transmit module. */
1735 if ((rc = efx_tx_init(sc->enp)) != 0)
1736 return (rc);
1737
1738 for (index = 0; index < sc->txq_count; index++) {
1739 if ((rc = sfxge_tx_qstart(sc, index)) != 0)
1740 goto fail;
1741 }
1742
1743 return (0);
1744
1745 fail:
1746 while (--index >= 0)
1747 sfxge_tx_qstop(sc, index);
1748
1749 efx_tx_fini(sc->enp);
1750
1751 return (rc);
1752 }
1753
1754 static int
sfxge_txq_stat_init(struct sfxge_txq * txq,struct sysctl_oid * txq_node)1755 sfxge_txq_stat_init(struct sfxge_txq *txq, struct sysctl_oid *txq_node)
1756 {
1757 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(txq->sc->dev);
1758 struct sysctl_oid *stat_node;
1759 unsigned int id;
1760
1761 stat_node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(txq_node), OID_AUTO,
1762 "stats", CTLFLAG_RD, NULL,
1763 "Tx queue statistics");
1764 if (stat_node == NULL)
1765 return (ENOMEM);
1766
1767 for (id = 0; id < nitems(sfxge_tx_stats); id++) {
1768 SYSCTL_ADD_ULONG(
1769 ctx, SYSCTL_CHILDREN(stat_node), OID_AUTO,
1770 sfxge_tx_stats[id].name, CTLFLAG_RD | CTLFLAG_STATS,
1771 (unsigned long *)((caddr_t)txq + sfxge_tx_stats[id].offset),
1772 "");
1773 }
1774
1775 return (0);
1776 }
1777
1778 /**
1779 * Destroy a transmit queue.
1780 */
1781 static void
sfxge_tx_qfini(struct sfxge_softc * sc,unsigned int index)1782 sfxge_tx_qfini(struct sfxge_softc *sc, unsigned int index)
1783 {
1784 struct sfxge_txq *txq;
1785 unsigned int nmaps;
1786
1787 txq = sc->txq[index];
1788
1789 KASSERT(txq->init_state == SFXGE_TXQ_INITIALIZED,
1790 ("txq->init_state != SFXGE_TXQ_INITIALIZED"));
1791
1792 if (txq->type == SFXGE_TXQ_IP_TCP_UDP_CKSUM)
1793 tso_fini(txq);
1794
1795 /* Free the context arrays. */
1796 free(txq->pend_desc, M_SFXGE);
1797 nmaps = sc->txq_entries;
1798 while (nmaps-- != 0)
1799 bus_dmamap_destroy(txq->packet_dma_tag, txq->stmp[nmaps].map);
1800 free(txq->stmp, M_SFXGE);
1801
1802 /* Release DMA memory mapping. */
1803 sfxge_dma_free(&txq->mem);
1804
1805 sc->txq[index] = NULL;
1806
1807 SFXGE_TXQ_LOCK_DESTROY(txq);
1808
1809 free(txq, M_SFXGE);
1810 }
1811
1812 static int
sfxge_tx_qinit(struct sfxge_softc * sc,unsigned int txq_index,enum sfxge_txq_type type,unsigned int evq_index)1813 sfxge_tx_qinit(struct sfxge_softc *sc, unsigned int txq_index,
1814 enum sfxge_txq_type type, unsigned int evq_index)
1815 {
1816 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sc->enp);
1817 char name[16];
1818 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
1819 struct sysctl_oid *txq_node;
1820 struct sfxge_txq *txq;
1821 struct sfxge_evq *evq;
1822 struct sfxge_tx_dpl *stdp;
1823 struct sysctl_oid *dpl_node;
1824 efsys_mem_t *esmp;
1825 unsigned int nmaps;
1826 int rc;
1827
1828 txq = malloc(sizeof(struct sfxge_txq), M_SFXGE, M_ZERO | M_WAITOK);
1829 txq->sc = sc;
1830 txq->entries = sc->txq_entries;
1831 txq->ptr_mask = txq->entries - 1;
1832
1833 sc->txq[txq_index] = txq;
1834 esmp = &txq->mem;
1835
1836 evq = sc->evq[evq_index];
1837
1838 /* Allocate and zero DMA space for the descriptor ring. */
1839 if ((rc = sfxge_dma_alloc(sc, EFX_TXQ_SIZE(sc->txq_entries), esmp)) != 0)
1840 return (rc);
1841
1842 /* Allocate buffer table entries. */
1843 sfxge_sram_buf_tbl_alloc(sc, EFX_TXQ_NBUFS(sc->txq_entries),
1844 &txq->buf_base_id);
1845
1846 /* Create a DMA tag for packet mappings. */
1847 if (bus_dma_tag_create(sc->parent_dma_tag, 1,
1848 encp->enc_tx_dma_desc_boundary,
1849 MIN(0x3FFFFFFFFFFFUL, BUS_SPACE_MAXADDR), BUS_SPACE_MAXADDR, NULL,
1850 NULL, 0x11000, SFXGE_TX_MAPPING_MAX_SEG,
1851 encp->enc_tx_dma_desc_size_max, 0, NULL, NULL,
1852 &txq->packet_dma_tag) != 0) {
1853 device_printf(sc->dev, "Couldn't allocate txq DMA tag\n");
1854 rc = ENOMEM;
1855 goto fail;
1856 }
1857
1858 /* Allocate pending descriptor array for batching writes. */
1859 txq->pend_desc = malloc(sizeof(efx_desc_t) * sc->txq_entries,
1860 M_SFXGE, M_ZERO | M_WAITOK);
1861
1862 /* Allocate and initialise mbuf DMA mapping array. */
1863 txq->stmp = malloc(sizeof(struct sfxge_tx_mapping) * sc->txq_entries,
1864 M_SFXGE, M_ZERO | M_WAITOK);
1865 for (nmaps = 0; nmaps < sc->txq_entries; nmaps++) {
1866 rc = bus_dmamap_create(txq->packet_dma_tag, 0,
1867 &txq->stmp[nmaps].map);
1868 if (rc != 0)
1869 goto fail2;
1870 }
1871
1872 snprintf(name, sizeof(name), "%u", txq_index);
1873 txq_node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(sc->txqs_node),
1874 OID_AUTO, name, CTLFLAG_RD, NULL, "");
1875 if (txq_node == NULL) {
1876 rc = ENOMEM;
1877 goto fail_txq_node;
1878 }
1879
1880 if (type == SFXGE_TXQ_IP_TCP_UDP_CKSUM &&
1881 (rc = tso_init(txq)) != 0)
1882 goto fail3;
1883
1884 /* Initialize the deferred packet list. */
1885 stdp = &txq->dpl;
1886 stdp->std_put_max = sfxge_tx_dpl_put_max;
1887 stdp->std_get_max = sfxge_tx_dpl_get_max;
1888 stdp->std_get_non_tcp_max = sfxge_tx_dpl_get_non_tcp_max;
1889 stdp->std_getp = &stdp->std_get;
1890
1891 SFXGE_TXQ_LOCK_INIT(txq, device_get_nameunit(sc->dev), txq_index);
1892
1893 dpl_node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(txq_node), OID_AUTO,
1894 "dpl", CTLFLAG_RD, NULL,
1895 "Deferred packet list statistics");
1896 if (dpl_node == NULL) {
1897 rc = ENOMEM;
1898 goto fail_dpl_node;
1899 }
1900
1901 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(dpl_node), OID_AUTO,
1902 "get_count", CTLFLAG_RD | CTLFLAG_STATS,
1903 &stdp->std_get_count, 0, "");
1904 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(dpl_node), OID_AUTO,
1905 "get_non_tcp_count", CTLFLAG_RD | CTLFLAG_STATS,
1906 &stdp->std_get_non_tcp_count, 0, "");
1907 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(dpl_node), OID_AUTO,
1908 "get_hiwat", CTLFLAG_RD | CTLFLAG_STATS,
1909 &stdp->std_get_hiwat, 0, "");
1910 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(dpl_node), OID_AUTO,
1911 "put_hiwat", CTLFLAG_RD | CTLFLAG_STATS,
1912 &stdp->std_put_hiwat, 0, "");
1913
1914 rc = sfxge_txq_stat_init(txq, txq_node);
1915 if (rc != 0)
1916 goto fail_txq_stat_init;
1917
1918 txq->type = type;
1919 txq->evq_index = evq_index;
1920 txq->init_state = SFXGE_TXQ_INITIALIZED;
1921
1922 return (0);
1923
1924 fail_txq_stat_init:
1925 fail_dpl_node:
1926 fail3:
1927 fail_txq_node:
1928 free(txq->pend_desc, M_SFXGE);
1929 fail2:
1930 while (nmaps-- != 0)
1931 bus_dmamap_destroy(txq->packet_dma_tag, txq->stmp[nmaps].map);
1932 free(txq->stmp, M_SFXGE);
1933 bus_dma_tag_destroy(txq->packet_dma_tag);
1934
1935 fail:
1936 sfxge_dma_free(esmp);
1937
1938 return (rc);
1939 }
1940
1941 static int
sfxge_tx_stat_handler(SYSCTL_HANDLER_ARGS)1942 sfxge_tx_stat_handler(SYSCTL_HANDLER_ARGS)
1943 {
1944 struct sfxge_softc *sc = arg1;
1945 unsigned int id = arg2;
1946 unsigned long sum;
1947 unsigned int index;
1948
1949 /* Sum across all TX queues */
1950 sum = 0;
1951 for (index = 0; index < sc->txq_count; index++)
1952 sum += *(unsigned long *)((caddr_t)sc->txq[index] +
1953 sfxge_tx_stats[id].offset);
1954
1955 return (SYSCTL_OUT(req, &sum, sizeof(sum)));
1956 }
1957
1958 static void
sfxge_tx_stat_init(struct sfxge_softc * sc)1959 sfxge_tx_stat_init(struct sfxge_softc *sc)
1960 {
1961 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
1962 struct sysctl_oid_list *stat_list;
1963 unsigned int id;
1964
1965 stat_list = SYSCTL_CHILDREN(sc->stats_node);
1966
1967 for (id = 0; id < nitems(sfxge_tx_stats); id++) {
1968 SYSCTL_ADD_PROC(
1969 ctx, stat_list,
1970 OID_AUTO, sfxge_tx_stats[id].name,
1971 CTLTYPE_ULONG|CTLFLAG_RD,
1972 sc, id, sfxge_tx_stat_handler, "LU",
1973 "");
1974 }
1975 }
1976
1977 uint64_t
sfxge_tx_get_drops(struct sfxge_softc * sc)1978 sfxge_tx_get_drops(struct sfxge_softc *sc)
1979 {
1980 unsigned int index;
1981 uint64_t drops = 0;
1982 struct sfxge_txq *txq;
1983
1984 /* Sum across all TX queues */
1985 for (index = 0; index < sc->txq_count; index++) {
1986 txq = sc->txq[index];
1987 /*
1988 * In theory, txq->put_overflow and txq->netdown_drops
1989 * should use atomic operation and other should be
1990 * obtained under txq lock, but it is just statistics.
1991 */
1992 drops += txq->drops + txq->get_overflow +
1993 txq->get_non_tcp_overflow +
1994 txq->put_overflow + txq->netdown_drops +
1995 txq->tso_pdrop_too_many + txq->tso_pdrop_no_rsrc;
1996 }
1997 return (drops);
1998 }
1999
2000 void
sfxge_tx_fini(struct sfxge_softc * sc)2001 sfxge_tx_fini(struct sfxge_softc *sc)
2002 {
2003 int index;
2004
2005 index = sc->txq_count;
2006 while (--index >= 0)
2007 sfxge_tx_qfini(sc, index);
2008
2009 sc->txq_count = 0;
2010 }
2011
2012
2013 int
sfxge_tx_init(struct sfxge_softc * sc)2014 sfxge_tx_init(struct sfxge_softc *sc)
2015 {
2016 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sc->enp);
2017 struct sfxge_intr *intr;
2018 int index;
2019 int rc;
2020
2021 intr = &sc->intr;
2022
2023 KASSERT(intr->state == SFXGE_INTR_INITIALIZED,
2024 ("intr->state != SFXGE_INTR_INITIALIZED"));
2025
2026 if (sfxge_tx_dpl_get_max <= 0) {
2027 log(LOG_ERR, "%s=%d must be greater than 0",
2028 SFXGE_PARAM_TX_DPL_GET_MAX, sfxge_tx_dpl_get_max);
2029 rc = EINVAL;
2030 goto fail_tx_dpl_get_max;
2031 }
2032 if (sfxge_tx_dpl_get_non_tcp_max <= 0) {
2033 log(LOG_ERR, "%s=%d must be greater than 0",
2034 SFXGE_PARAM_TX_DPL_GET_NON_TCP_MAX,
2035 sfxge_tx_dpl_get_non_tcp_max);
2036 rc = EINVAL;
2037 goto fail_tx_dpl_get_non_tcp_max;
2038 }
2039 if (sfxge_tx_dpl_put_max < 0) {
2040 log(LOG_ERR, "%s=%d must be greater or equal to 0",
2041 SFXGE_PARAM_TX_DPL_PUT_MAX, sfxge_tx_dpl_put_max);
2042 rc = EINVAL;
2043 goto fail_tx_dpl_put_max;
2044 }
2045
2046 sc->txq_count = SFXGE_EVQ0_N_TXQ(sc) - 1 + sc->intr.n_alloc;
2047
2048 sc->tso_fw_assisted = sfxge_tso_fw_assisted;
2049 if ((~encp->enc_features & EFX_FEATURE_FW_ASSISTED_TSO) ||
2050 (!encp->enc_fw_assisted_tso_enabled))
2051 sc->tso_fw_assisted &= ~SFXGE_FATSOV1;
2052 if ((~encp->enc_features & EFX_FEATURE_FW_ASSISTED_TSO_V2) ||
2053 (!encp->enc_fw_assisted_tso_v2_enabled))
2054 sc->tso_fw_assisted &= ~SFXGE_FATSOV2;
2055
2056 sc->txqs_node = SYSCTL_ADD_NODE(
2057 device_get_sysctl_ctx(sc->dev),
2058 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
2059 OID_AUTO, "txq", CTLFLAG_RD, NULL, "Tx queues");
2060 if (sc->txqs_node == NULL) {
2061 rc = ENOMEM;
2062 goto fail_txq_node;
2063 }
2064
2065 /* Initialize the transmit queues */
2066 if (sc->txq_dynamic_cksum_toggle_supported == B_FALSE) {
2067 if ((rc = sfxge_tx_qinit(sc, SFXGE_TXQ_NON_CKSUM,
2068 SFXGE_TXQ_NON_CKSUM, 0)) != 0)
2069 goto fail;
2070
2071 if ((rc = sfxge_tx_qinit(sc, SFXGE_TXQ_IP_CKSUM,
2072 SFXGE_TXQ_IP_CKSUM, 0)) != 0)
2073 goto fail2;
2074 }
2075
2076 for (index = 0;
2077 index < sc->txq_count - SFXGE_EVQ0_N_TXQ(sc) + 1;
2078 index++) {
2079 if ((rc = sfxge_tx_qinit(sc, SFXGE_EVQ0_N_TXQ(sc) - 1 + index,
2080 SFXGE_TXQ_IP_TCP_UDP_CKSUM, index)) != 0)
2081 goto fail3;
2082 }
2083
2084 sfxge_tx_stat_init(sc);
2085
2086 return (0);
2087
2088 fail3:
2089 while (--index >= 0)
2090 sfxge_tx_qfini(sc, SFXGE_TXQ_IP_TCP_UDP_CKSUM + index);
2091
2092 sfxge_tx_qfini(sc, SFXGE_TXQ_IP_CKSUM);
2093
2094 fail2:
2095 sfxge_tx_qfini(sc, SFXGE_TXQ_NON_CKSUM);
2096
2097 fail:
2098 fail_txq_node:
2099 sc->txq_count = 0;
2100 fail_tx_dpl_put_max:
2101 fail_tx_dpl_get_non_tcp_max:
2102 fail_tx_dpl_get_max:
2103 return (rc);
2104 }
2105