1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010-2016 Solarflare Communications Inc.
5 * All rights reserved.
6 *
7 * This software was developed in part by Philip Paeps under contract for
8 * Solarflare Communications, Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * The views and conclusions contained in the software and documentation are
32 * those of the authors and should not be interpreted as representing official
33 * policies, either expressed or implied, of the FreeBSD Project.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD: stable/12/sys/dev/sfxge/sfxge_port.c 333813 2018-05-18 20:13:34Z mmacy $");
38
39 #include <sys/types.h>
40 #include <sys/limits.h>
41 #include <net/ethernet.h>
42 #include <net/if_dl.h>
43
44 #include "common/efx.h"
45
46 #include "sfxge.h"
47
48 #define SFXGE_PARAM_STATS_UPDATE_PERIOD_MS \
49 SFXGE_PARAM(stats_update_period_ms)
50 static int sfxge_stats_update_period_ms = SFXGE_STATS_UPDATE_PERIOD_MS;
51 TUNABLE_INT(SFXGE_PARAM_STATS_UPDATE_PERIOD_MS,
52 &sfxge_stats_update_period_ms);
53 SYSCTL_INT(_hw_sfxge, OID_AUTO, stats_update_period_ms, CTLFLAG_RDTUN,
54 &sfxge_stats_update_period_ms, 0,
55 "netstat interface statistics update period in milliseconds");
56
57 static int sfxge_phy_cap_mask(struct sfxge_softc *, int, uint32_t *);
58
59 static int
sfxge_mac_stat_update(struct sfxge_softc * sc)60 sfxge_mac_stat_update(struct sfxge_softc *sc)
61 {
62 struct sfxge_port *port = &sc->port;
63 efsys_mem_t *esmp = &(port->mac_stats.dma_buf);
64 clock_t now;
65 unsigned int min_ticks;
66 unsigned int count;
67 int rc;
68
69 SFXGE_PORT_LOCK_ASSERT_OWNED(port);
70
71 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) {
72 rc = 0;
73 goto out;
74 }
75
76 min_ticks = (unsigned int)hz * port->stats_update_period_ms / 1000;
77
78 now = ticks;
79 if ((unsigned int)(now - port->mac_stats.update_time) < min_ticks) {
80 rc = 0;
81 goto out;
82 }
83
84 port->mac_stats.update_time = now;
85
86 /* If we're unlucky enough to read statistics wduring the DMA, wait
87 * up to 10ms for it to finish (typically takes <500us) */
88 for (count = 0; count < 100; ++count) {
89 EFSYS_PROBE1(wait, unsigned int, count);
90
91 /* Try to update the cached counters */
92 if ((rc = efx_mac_stats_update(sc->enp, esmp,
93 port->mac_stats.decode_buf, NULL)) != EAGAIN)
94 goto out;
95
96 DELAY(100);
97 }
98
99 rc = ETIMEDOUT;
100 out:
101 return (rc);
102 }
103
104 uint64_t
sfxge_get_counter(struct ifnet * ifp,ift_counter c)105 sfxge_get_counter(struct ifnet *ifp, ift_counter c)
106 {
107 struct sfxge_softc *sc = ifp->if_softc;
108 uint64_t *mac_stats;
109 uint64_t val;
110
111 SFXGE_PORT_LOCK(&sc->port);
112
113 /* Ignore error and use old values */
114 (void)sfxge_mac_stat_update(sc);
115
116 mac_stats = (uint64_t *)sc->port.mac_stats.decode_buf;
117
118 switch (c) {
119 case IFCOUNTER_IPACKETS:
120 val = mac_stats[EFX_MAC_RX_PKTS];
121 break;
122 case IFCOUNTER_IERRORS:
123 val = mac_stats[EFX_MAC_RX_ERRORS];
124 break;
125 case IFCOUNTER_OPACKETS:
126 val = mac_stats[EFX_MAC_TX_PKTS];
127 break;
128 case IFCOUNTER_OERRORS:
129 val = mac_stats[EFX_MAC_TX_ERRORS];
130 break;
131 case IFCOUNTER_COLLISIONS:
132 val = mac_stats[EFX_MAC_TX_SGL_COL_PKTS] +
133 mac_stats[EFX_MAC_TX_MULT_COL_PKTS] +
134 mac_stats[EFX_MAC_TX_EX_COL_PKTS] +
135 mac_stats[EFX_MAC_TX_LATE_COL_PKTS];
136 break;
137 case IFCOUNTER_IBYTES:
138 val = mac_stats[EFX_MAC_RX_OCTETS];
139 break;
140 case IFCOUNTER_OBYTES:
141 val = mac_stats[EFX_MAC_TX_OCTETS];
142 break;
143 case IFCOUNTER_OMCASTS:
144 val = mac_stats[EFX_MAC_TX_MULTICST_PKTS] +
145 mac_stats[EFX_MAC_TX_BRDCST_PKTS];
146 break;
147 case IFCOUNTER_OQDROPS:
148 SFXGE_PORT_UNLOCK(&sc->port);
149 return (sfxge_tx_get_drops(sc));
150 case IFCOUNTER_IMCASTS:
151 /* if_imcasts is maintained in net/if_ethersubr.c */
152 case IFCOUNTER_IQDROPS:
153 /* if_iqdrops is maintained in net/if_ethersubr.c */
154 case IFCOUNTER_NOPROTO:
155 /* if_noproto is maintained in net/if_ethersubr.c */
156 default:
157 SFXGE_PORT_UNLOCK(&sc->port);
158 return (if_get_counter_default(ifp, c));
159 }
160
161 SFXGE_PORT_UNLOCK(&sc->port);
162
163 return (val);
164 }
165
166 static int
sfxge_mac_stat_handler(SYSCTL_HANDLER_ARGS)167 sfxge_mac_stat_handler(SYSCTL_HANDLER_ARGS)
168 {
169 struct sfxge_softc *sc = arg1;
170 unsigned int id = arg2;
171 int rc;
172 uint64_t val;
173
174 SFXGE_PORT_LOCK(&sc->port);
175 if ((rc = sfxge_mac_stat_update(sc)) == 0)
176 val = ((uint64_t *)sc->port.mac_stats.decode_buf)[id];
177 SFXGE_PORT_UNLOCK(&sc->port);
178
179 if (rc == 0)
180 rc = SYSCTL_OUT(req, &val, sizeof(val));
181 return (rc);
182 }
183
184 static void
sfxge_mac_stat_init(struct sfxge_softc * sc)185 sfxge_mac_stat_init(struct sfxge_softc *sc)
186 {
187 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
188 struct sysctl_oid_list *stat_list;
189 unsigned int id;
190 const char *name;
191
192 stat_list = SYSCTL_CHILDREN(sc->stats_node);
193
194 /* Initialise the named stats */
195 for (id = 0; id < EFX_MAC_NSTATS; id++) {
196 name = efx_mac_stat_name(sc->enp, id);
197 SYSCTL_ADD_PROC(
198 ctx, stat_list,
199 OID_AUTO, name, CTLTYPE_U64|CTLFLAG_RD,
200 sc, id, sfxge_mac_stat_handler, "Q",
201 "");
202 }
203 }
204
205 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS
206
207 static unsigned int
sfxge_port_wanted_fc(struct sfxge_softc * sc)208 sfxge_port_wanted_fc(struct sfxge_softc *sc)
209 {
210 struct ifmedia_entry *ifm = sc->media.ifm_cur;
211
212 if (ifm->ifm_media == (IFM_ETHER | IFM_AUTO))
213 return (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE);
214 return (((ifm->ifm_media & IFM_ETH_RXPAUSE) ? EFX_FCNTL_RESPOND : 0) |
215 ((ifm->ifm_media & IFM_ETH_TXPAUSE) ? EFX_FCNTL_GENERATE : 0));
216 }
217
218 static unsigned int
sfxge_port_link_fc_ifm(struct sfxge_softc * sc)219 sfxge_port_link_fc_ifm(struct sfxge_softc *sc)
220 {
221 unsigned int wanted_fc, link_fc;
222
223 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc);
224 return ((link_fc & EFX_FCNTL_RESPOND) ? IFM_ETH_RXPAUSE : 0) |
225 ((link_fc & EFX_FCNTL_GENERATE) ? IFM_ETH_TXPAUSE : 0);
226 }
227
228 #else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */
229
230 static unsigned int
sfxge_port_wanted_fc(struct sfxge_softc * sc)231 sfxge_port_wanted_fc(struct sfxge_softc *sc)
232 {
233 return (sc->port.wanted_fc);
234 }
235
236 static unsigned int
sfxge_port_link_fc_ifm(struct sfxge_softc * sc)237 sfxge_port_link_fc_ifm(struct sfxge_softc *sc)
238 {
239 return (0);
240 }
241
242 static int
sfxge_port_wanted_fc_handler(SYSCTL_HANDLER_ARGS)243 sfxge_port_wanted_fc_handler(SYSCTL_HANDLER_ARGS)
244 {
245 struct sfxge_softc *sc;
246 struct sfxge_port *port;
247 unsigned int fcntl;
248 int error;
249
250 sc = arg1;
251 port = &sc->port;
252
253 if (req->newptr != NULL) {
254 if ((error = SYSCTL_IN(req, &fcntl, sizeof(fcntl))) != 0)
255 return (error);
256
257 SFXGE_PORT_LOCK(port);
258
259 if (port->wanted_fc != fcntl) {
260 if (port->init_state == SFXGE_PORT_STARTED)
261 error = efx_mac_fcntl_set(sc->enp,
262 port->wanted_fc,
263 B_TRUE);
264 if (error == 0)
265 port->wanted_fc = fcntl;
266 }
267
268 SFXGE_PORT_UNLOCK(port);
269 } else {
270 SFXGE_PORT_LOCK(port);
271 fcntl = port->wanted_fc;
272 SFXGE_PORT_UNLOCK(port);
273
274 error = SYSCTL_OUT(req, &fcntl, sizeof(fcntl));
275 }
276
277 return (error);
278 }
279
280 static int
sfxge_port_link_fc_handler(SYSCTL_HANDLER_ARGS)281 sfxge_port_link_fc_handler(SYSCTL_HANDLER_ARGS)
282 {
283 struct sfxge_softc *sc;
284 struct sfxge_port *port;
285 unsigned int wanted_fc, link_fc;
286
287 sc = arg1;
288 port = &sc->port;
289
290 SFXGE_PORT_LOCK(port);
291 if (__predict_true(port->init_state == SFXGE_PORT_STARTED) &&
292 SFXGE_LINK_UP(sc))
293 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc);
294 else
295 link_fc = 0;
296 SFXGE_PORT_UNLOCK(port);
297
298 return (SYSCTL_OUT(req, &link_fc, sizeof(link_fc)));
299 }
300
301 #endif /* SFXGE_HAVE_PAUSE_MEDIAOPTS */
302
303 static const uint64_t sfxge_link_baudrate[EFX_LINK_NMODES] = {
304 [EFX_LINK_10HDX] = IF_Mbps(10),
305 [EFX_LINK_10FDX] = IF_Mbps(10),
306 [EFX_LINK_100HDX] = IF_Mbps(100),
307 [EFX_LINK_100FDX] = IF_Mbps(100),
308 [EFX_LINK_1000HDX] = IF_Gbps(1),
309 [EFX_LINK_1000FDX] = IF_Gbps(1),
310 [EFX_LINK_10000FDX] = IF_Gbps(10),
311 [EFX_LINK_40000FDX] = IF_Gbps(40),
312 };
313
314 void
sfxge_mac_link_update(struct sfxge_softc * sc,efx_link_mode_t mode)315 sfxge_mac_link_update(struct sfxge_softc *sc, efx_link_mode_t mode)
316 {
317 struct sfxge_port *port;
318 int link_state;
319
320 port = &sc->port;
321
322 if (port->link_mode == mode)
323 return;
324
325 port->link_mode = mode;
326
327 /* Push link state update to the OS */
328 link_state = (SFXGE_LINK_UP(sc) ? LINK_STATE_UP : LINK_STATE_DOWN);
329 sc->ifnet->if_baudrate = sfxge_link_baudrate[port->link_mode];
330 if_link_state_change(sc->ifnet, link_state);
331 }
332
333 static void
sfxge_mac_poll_work(void * arg,int npending)334 sfxge_mac_poll_work(void *arg, int npending)
335 {
336 struct sfxge_softc *sc;
337 efx_nic_t *enp;
338 struct sfxge_port *port;
339 efx_link_mode_t mode;
340
341 sc = (struct sfxge_softc *)arg;
342 enp = sc->enp;
343 port = &sc->port;
344
345 SFXGE_PORT_LOCK(port);
346
347 if (__predict_false(port->init_state != SFXGE_PORT_STARTED))
348 goto done;
349
350 /* This may sleep waiting for MCDI completion */
351 (void)efx_port_poll(enp, &mode);
352 sfxge_mac_link_update(sc, mode);
353
354 done:
355 SFXGE_PORT_UNLOCK(port);
356 }
357
358 static int
sfxge_mac_multicast_list_set(struct sfxge_softc * sc)359 sfxge_mac_multicast_list_set(struct sfxge_softc *sc)
360 {
361 struct ifnet *ifp = sc->ifnet;
362 struct sfxge_port *port = &sc->port;
363 uint8_t *mcast_addr = port->mcast_addrs;
364 struct ifmultiaddr *ifma;
365 struct sockaddr_dl *sa;
366 int rc = 0;
367
368 mtx_assert(&port->lock, MA_OWNED);
369
370 port->mcast_count = 0;
371 if_maddr_rlock(ifp);
372 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
373 if (ifma->ifma_addr->sa_family == AF_LINK) {
374 if (port->mcast_count == EFX_MAC_MULTICAST_LIST_MAX) {
375 device_printf(sc->dev,
376 "Too many multicast addresses\n");
377 rc = EINVAL;
378 break;
379 }
380
381 sa = (struct sockaddr_dl *)ifma->ifma_addr;
382 memcpy(mcast_addr, LLADDR(sa), EFX_MAC_ADDR_LEN);
383 mcast_addr += EFX_MAC_ADDR_LEN;
384 ++port->mcast_count;
385 }
386 }
387 if_maddr_runlock(ifp);
388
389 if (rc == 0) {
390 rc = efx_mac_multicast_list_set(sc->enp, port->mcast_addrs,
391 port->mcast_count);
392 if (rc != 0)
393 device_printf(sc->dev,
394 "Cannot set multicast address list\n");
395 }
396
397 return (rc);
398 }
399
400 static int
sfxge_mac_filter_set_locked(struct sfxge_softc * sc)401 sfxge_mac_filter_set_locked(struct sfxge_softc *sc)
402 {
403 struct ifnet *ifp = sc->ifnet;
404 struct sfxge_port *port = &sc->port;
405 boolean_t all_mulcst;
406 int rc;
407
408 mtx_assert(&port->lock, MA_OWNED);
409
410 all_mulcst = !!(ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI));
411
412 rc = sfxge_mac_multicast_list_set(sc);
413 /* Fallback to all multicast if cannot set multicast list */
414 if (rc != 0)
415 all_mulcst = B_TRUE;
416
417 rc = efx_mac_filter_set(sc->enp, !!(ifp->if_flags & IFF_PROMISC),
418 (port->mcast_count > 0), all_mulcst, B_TRUE);
419
420 return (rc);
421 }
422
423 int
sfxge_mac_filter_set(struct sfxge_softc * sc)424 sfxge_mac_filter_set(struct sfxge_softc *sc)
425 {
426 struct sfxge_port *port = &sc->port;
427 int rc;
428
429 SFXGE_PORT_LOCK(port);
430 /*
431 * The function may be called without softc_lock held in the
432 * case of SIOCADDMULTI and SIOCDELMULTI ioctls. ioctl handler
433 * checks IFF_DRV_RUNNING flag which implies port started, but
434 * it is not guaranteed to remain. softc_lock shared lock can't
435 * be held in the case of these ioctls processing, since it
436 * results in failure where kernel complains that non-sleepable
437 * lock is held in sleeping thread. Both problems are repeatable
438 * on LAG with LACP proto bring up.
439 */
440 if (__predict_true(port->init_state == SFXGE_PORT_STARTED))
441 rc = sfxge_mac_filter_set_locked(sc);
442 else
443 rc = 0;
444 SFXGE_PORT_UNLOCK(port);
445 return (rc);
446 }
447
448 void
sfxge_port_stop(struct sfxge_softc * sc)449 sfxge_port_stop(struct sfxge_softc *sc)
450 {
451 struct sfxge_port *port;
452 efx_nic_t *enp;
453
454 port = &sc->port;
455 enp = sc->enp;
456
457 SFXGE_PORT_LOCK(port);
458
459 KASSERT(port->init_state == SFXGE_PORT_STARTED,
460 ("port not started"));
461
462 port->init_state = SFXGE_PORT_INITIALIZED;
463
464 port->mac_stats.update_time = 0;
465
466 /* This may call MCDI */
467 (void)efx_mac_drain(enp, B_TRUE);
468
469 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE);
470
471 port->link_mode = EFX_LINK_UNKNOWN;
472
473 /* Destroy the common code port object. */
474 efx_port_fini(enp);
475
476 efx_filter_fini(enp);
477
478 SFXGE_PORT_UNLOCK(port);
479 }
480
481 int
sfxge_port_start(struct sfxge_softc * sc)482 sfxge_port_start(struct sfxge_softc *sc)
483 {
484 uint8_t mac_addr[ETHER_ADDR_LEN];
485 struct ifnet *ifp = sc->ifnet;
486 struct sfxge_port *port;
487 efx_nic_t *enp;
488 size_t pdu;
489 int rc;
490 uint32_t phy_cap_mask;
491
492 port = &sc->port;
493 enp = sc->enp;
494
495 SFXGE_PORT_LOCK(port);
496
497 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED,
498 ("port not initialized"));
499
500 /* Initialise the required filtering */
501 if ((rc = efx_filter_init(enp)) != 0)
502 goto fail_filter_init;
503
504 /* Initialize the port object in the common code. */
505 if ((rc = efx_port_init(sc->enp)) != 0)
506 goto fail;
507
508 /* Set the SDU */
509 pdu = EFX_MAC_PDU(ifp->if_mtu);
510 if ((rc = efx_mac_pdu_set(enp, pdu)) != 0)
511 goto fail2;
512
513 if ((rc = efx_mac_fcntl_set(enp, sfxge_port_wanted_fc(sc), B_TRUE))
514 != 0)
515 goto fail3;
516
517 /* Set the unicast address */
518 if_addr_rlock(ifp);
519 bcopy(LLADDR((struct sockaddr_dl *)ifp->if_addr->ifa_addr),
520 mac_addr, sizeof(mac_addr));
521 if_addr_runlock(ifp);
522 if ((rc = efx_mac_addr_set(enp, mac_addr)) != 0)
523 goto fail4;
524
525 sfxge_mac_filter_set_locked(sc);
526
527 /* Update MAC stats by DMA every period */
528 if ((rc = efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf,
529 port->stats_update_period_ms,
530 B_FALSE)) != 0)
531 goto fail6;
532
533 if ((rc = efx_mac_drain(enp, B_FALSE)) != 0)
534 goto fail8;
535
536 if ((rc = sfxge_phy_cap_mask(sc, sc->media.ifm_cur->ifm_media,
537 &phy_cap_mask)) != 0)
538 goto fail9;
539
540 if ((rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask)) != 0)
541 goto fail10;
542
543 port->init_state = SFXGE_PORT_STARTED;
544
545 /* Single poll in case there were missing initial events */
546 SFXGE_PORT_UNLOCK(port);
547 sfxge_mac_poll_work(sc, 0);
548
549 return (0);
550
551 fail10:
552 fail9:
553 (void)efx_mac_drain(enp, B_TRUE);
554 fail8:
555 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE);
556 fail6:
557 fail4:
558 fail3:
559
560 fail2:
561 efx_port_fini(enp);
562 fail:
563 efx_filter_fini(enp);
564 fail_filter_init:
565 SFXGE_PORT_UNLOCK(port);
566
567 return (rc);
568 }
569
570 static int
sfxge_phy_stat_update(struct sfxge_softc * sc)571 sfxge_phy_stat_update(struct sfxge_softc *sc)
572 {
573 struct sfxge_port *port = &sc->port;
574 efsys_mem_t *esmp = &port->phy_stats.dma_buf;
575 clock_t now;
576 unsigned int count;
577 int rc;
578
579 SFXGE_PORT_LOCK_ASSERT_OWNED(port);
580
581 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) {
582 rc = 0;
583 goto out;
584 }
585
586 now = ticks;
587 if ((unsigned int)(now - port->phy_stats.update_time) < (unsigned int)hz) {
588 rc = 0;
589 goto out;
590 }
591
592 port->phy_stats.update_time = now;
593
594 /* If we're unlucky enough to read statistics wduring the DMA, wait
595 * up to 10ms for it to finish (typically takes <500us) */
596 for (count = 0; count < 100; ++count) {
597 EFSYS_PROBE1(wait, unsigned int, count);
598
599 /* Synchronize the DMA memory for reading */
600 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map,
601 BUS_DMASYNC_POSTREAD);
602
603 /* Try to update the cached counters */
604 if ((rc = efx_phy_stats_update(sc->enp, esmp,
605 port->phy_stats.decode_buf)) != EAGAIN)
606 goto out;
607
608 DELAY(100);
609 }
610
611 rc = ETIMEDOUT;
612 out:
613 return (rc);
614 }
615
616 static int
sfxge_phy_stat_handler(SYSCTL_HANDLER_ARGS)617 sfxge_phy_stat_handler(SYSCTL_HANDLER_ARGS)
618 {
619 struct sfxge_softc *sc = arg1;
620 unsigned int id = arg2;
621 int rc;
622 uint32_t val;
623
624 SFXGE_PORT_LOCK(&sc->port);
625 if ((rc = sfxge_phy_stat_update(sc)) == 0)
626 val = ((uint32_t *)sc->port.phy_stats.decode_buf)[id];
627 SFXGE_PORT_UNLOCK(&sc->port);
628
629 if (rc == 0)
630 rc = SYSCTL_OUT(req, &val, sizeof(val));
631 return (rc);
632 }
633
634 static void
sfxge_phy_stat_init(struct sfxge_softc * sc)635 sfxge_phy_stat_init(struct sfxge_softc *sc)
636 {
637 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
638 struct sysctl_oid_list *stat_list;
639 unsigned int id;
640 const char *name;
641 uint64_t stat_mask = efx_nic_cfg_get(sc->enp)->enc_phy_stat_mask;
642
643 stat_list = SYSCTL_CHILDREN(sc->stats_node);
644
645 /* Initialise the named stats */
646 for (id = 0; id < EFX_PHY_NSTATS; id++) {
647 if (!(stat_mask & ((uint64_t)1 << id)))
648 continue;
649 name = efx_phy_stat_name(sc->enp, id);
650 SYSCTL_ADD_PROC(
651 ctx, stat_list,
652 OID_AUTO, name, CTLTYPE_UINT|CTLFLAG_RD,
653 sc, id, sfxge_phy_stat_handler,
654 id == EFX_PHY_STAT_OUI ? "IX" : "IU",
655 "");
656 }
657 }
658
659 void
sfxge_port_fini(struct sfxge_softc * sc)660 sfxge_port_fini(struct sfxge_softc *sc)
661 {
662 struct sfxge_port *port;
663 efsys_mem_t *esmp;
664
665 port = &sc->port;
666 esmp = &port->mac_stats.dma_buf;
667
668 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED,
669 ("Port not initialized"));
670
671 port->init_state = SFXGE_PORT_UNINITIALIZED;
672
673 port->link_mode = EFX_LINK_UNKNOWN;
674
675 /* Finish with PHY DMA memory */
676 sfxge_dma_free(&port->phy_stats.dma_buf);
677 free(port->phy_stats.decode_buf, M_SFXGE);
678
679 sfxge_dma_free(esmp);
680 free(port->mac_stats.decode_buf, M_SFXGE);
681
682 SFXGE_PORT_LOCK_DESTROY(port);
683
684 port->sc = NULL;
685 }
686
687 static uint16_t
sfxge_port_stats_update_period_ms(struct sfxge_softc * sc)688 sfxge_port_stats_update_period_ms(struct sfxge_softc *sc)
689 {
690 int period_ms = sfxge_stats_update_period_ms;
691
692 if (period_ms < 0) {
693 device_printf(sc->dev,
694 "treat negative stats update period %d as 0 (disable)\n",
695 period_ms);
696 period_ms = 0;
697 } else if (period_ms > UINT16_MAX) {
698 device_printf(sc->dev,
699 "treat too big stats update period %d as %u\n",
700 period_ms, UINT16_MAX);
701 period_ms = UINT16_MAX;
702 }
703
704 return period_ms;
705 }
706
707 static int
sfxge_port_stats_update_period_ms_handler(SYSCTL_HANDLER_ARGS)708 sfxge_port_stats_update_period_ms_handler(SYSCTL_HANDLER_ARGS)
709 {
710 struct sfxge_softc *sc;
711 struct sfxge_port *port;
712 unsigned int period_ms;
713 int error;
714
715 sc = arg1;
716 port = &sc->port;
717
718 if (req->newptr != NULL) {
719 error = SYSCTL_IN(req, &period_ms, sizeof(period_ms));
720 if (error != 0)
721 return (error);
722
723 if (period_ms > UINT16_MAX)
724 return (EINVAL);
725
726 SFXGE_PORT_LOCK(port);
727
728 if (port->stats_update_period_ms != period_ms) {
729 if (port->init_state == SFXGE_PORT_STARTED)
730 error = efx_mac_stats_periodic(sc->enp,
731 &port->mac_stats.dma_buf,
732 period_ms, B_FALSE);
733 if (error == 0)
734 port->stats_update_period_ms = period_ms;
735 }
736
737 SFXGE_PORT_UNLOCK(port);
738 } else {
739 SFXGE_PORT_LOCK(port);
740 period_ms = port->stats_update_period_ms;
741 SFXGE_PORT_UNLOCK(port);
742
743 error = SYSCTL_OUT(req, &period_ms, sizeof(period_ms));
744 }
745
746 return (error);
747 }
748
749 int
sfxge_port_init(struct sfxge_softc * sc)750 sfxge_port_init(struct sfxge_softc *sc)
751 {
752 struct sfxge_port *port;
753 struct sysctl_ctx_list *sysctl_ctx;
754 struct sysctl_oid *sysctl_tree;
755 efsys_mem_t *mac_stats_buf, *phy_stats_buf;
756 int rc;
757
758 port = &sc->port;
759 mac_stats_buf = &port->mac_stats.dma_buf;
760 phy_stats_buf = &port->phy_stats.dma_buf;
761
762 KASSERT(port->init_state == SFXGE_PORT_UNINITIALIZED,
763 ("Port already initialized"));
764
765 port->sc = sc;
766
767 SFXGE_PORT_LOCK_INIT(port, device_get_nameunit(sc->dev));
768
769 DBGPRINT(sc->dev, "alloc PHY stats");
770 port->phy_stats.decode_buf = malloc(EFX_PHY_NSTATS * sizeof(uint32_t),
771 M_SFXGE, M_WAITOK | M_ZERO);
772 if ((rc = sfxge_dma_alloc(sc, EFX_PHY_STATS_SIZE, phy_stats_buf)) != 0)
773 goto fail;
774 sfxge_phy_stat_init(sc);
775
776 DBGPRINT(sc->dev, "init sysctl");
777 sysctl_ctx = device_get_sysctl_ctx(sc->dev);
778 sysctl_tree = device_get_sysctl_tree(sc->dev);
779
780 #ifndef SFXGE_HAVE_PAUSE_MEDIAOPTS
781 /* If flow control cannot be configured or reported through
782 * ifmedia, provide sysctls for it. */
783 port->wanted_fc = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
784 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
785 "wanted_fc", CTLTYPE_UINT|CTLFLAG_RW, sc, 0,
786 sfxge_port_wanted_fc_handler, "IU", "wanted flow control mode");
787 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
788 "link_fc", CTLTYPE_UINT|CTLFLAG_RD, sc, 0,
789 sfxge_port_link_fc_handler, "IU", "link flow control mode");
790 #endif
791
792 DBGPRINT(sc->dev, "alloc MAC stats");
793 port->mac_stats.decode_buf = malloc(EFX_MAC_NSTATS * sizeof(uint64_t),
794 M_SFXGE, M_WAITOK | M_ZERO);
795 if ((rc = sfxge_dma_alloc(sc, EFX_MAC_STATS_SIZE, mac_stats_buf)) != 0)
796 goto fail2;
797 port->stats_update_period_ms = sfxge_port_stats_update_period_ms(sc);
798 sfxge_mac_stat_init(sc);
799
800 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
801 "stats_update_period_ms", CTLTYPE_UINT|CTLFLAG_RW, sc, 0,
802 sfxge_port_stats_update_period_ms_handler, "IU",
803 "interface statistics refresh period");
804
805 port->init_state = SFXGE_PORT_INITIALIZED;
806
807 DBGPRINT(sc->dev, "success");
808 return (0);
809
810 fail2:
811 free(port->mac_stats.decode_buf, M_SFXGE);
812 sfxge_dma_free(phy_stats_buf);
813 fail:
814 free(port->phy_stats.decode_buf, M_SFXGE);
815 SFXGE_PORT_LOCK_DESTROY(port);
816 port->sc = NULL;
817 DBGPRINT(sc->dev, "failed %d", rc);
818 return (rc);
819 }
820
821 static const int sfxge_link_mode[EFX_PHY_MEDIA_NTYPES][EFX_LINK_NMODES] = {
822 [EFX_PHY_MEDIA_CX4] = {
823 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_CX4,
824 },
825 [EFX_PHY_MEDIA_KX4] = {
826 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_KX4,
827 },
828 [EFX_PHY_MEDIA_XFP] = {
829 /* Don't know the module type, but assume SR for now. */
830 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR,
831 },
832 [EFX_PHY_MEDIA_QSFP_PLUS] = {
833 /* Don't know the module type, but assume SR for now. */
834 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR,
835 [EFX_LINK_40000FDX] = IFM_ETHER | IFM_FDX | IFM_40G_CR4,
836 },
837 [EFX_PHY_MEDIA_SFP_PLUS] = {
838 /* Don't know the module type, but assume SX/SR for now. */
839 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_SX,
840 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR,
841 },
842 [EFX_PHY_MEDIA_BASE_T] = {
843 [EFX_LINK_10HDX] = IFM_ETHER | IFM_HDX | IFM_10_T,
844 [EFX_LINK_10FDX] = IFM_ETHER | IFM_FDX | IFM_10_T,
845 [EFX_LINK_100HDX] = IFM_ETHER | IFM_HDX | IFM_100_TX,
846 [EFX_LINK_100FDX] = IFM_ETHER | IFM_FDX | IFM_100_TX,
847 [EFX_LINK_1000HDX] = IFM_ETHER | IFM_HDX | IFM_1000_T,
848 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_T,
849 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_T,
850 },
851 };
852
853 static void
sfxge_media_status(struct ifnet * ifp,struct ifmediareq * ifmr)854 sfxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
855 {
856 struct sfxge_softc *sc;
857 efx_phy_media_type_t medium_type;
858 efx_link_mode_t mode;
859
860 sc = ifp->if_softc;
861 SFXGE_ADAPTER_LOCK(sc);
862
863 ifmr->ifm_status = IFM_AVALID;
864 ifmr->ifm_active = IFM_ETHER;
865
866 if (SFXGE_RUNNING(sc) && SFXGE_LINK_UP(sc)) {
867 ifmr->ifm_status |= IFM_ACTIVE;
868
869 efx_phy_media_type_get(sc->enp, &medium_type);
870 mode = sc->port.link_mode;
871 ifmr->ifm_active |= sfxge_link_mode[medium_type][mode];
872 ifmr->ifm_active |= sfxge_port_link_fc_ifm(sc);
873 }
874
875 SFXGE_ADAPTER_UNLOCK(sc);
876 }
877
878 static efx_phy_cap_type_t
sfxge_link_mode_to_phy_cap(efx_link_mode_t mode)879 sfxge_link_mode_to_phy_cap(efx_link_mode_t mode)
880 {
881 switch (mode) {
882 case EFX_LINK_10HDX:
883 return (EFX_PHY_CAP_10HDX);
884 case EFX_LINK_10FDX:
885 return (EFX_PHY_CAP_10FDX);
886 case EFX_LINK_100HDX:
887 return (EFX_PHY_CAP_100HDX);
888 case EFX_LINK_100FDX:
889 return (EFX_PHY_CAP_100FDX);
890 case EFX_LINK_1000HDX:
891 return (EFX_PHY_CAP_1000HDX);
892 case EFX_LINK_1000FDX:
893 return (EFX_PHY_CAP_1000FDX);
894 case EFX_LINK_10000FDX:
895 return (EFX_PHY_CAP_10000FDX);
896 case EFX_LINK_40000FDX:
897 return (EFX_PHY_CAP_40000FDX);
898 default:
899 EFSYS_ASSERT(B_FALSE);
900 return (EFX_PHY_CAP_INVALID);
901 }
902 }
903
904 static int
sfxge_phy_cap_mask(struct sfxge_softc * sc,int ifmedia,uint32_t * phy_cap_mask)905 sfxge_phy_cap_mask(struct sfxge_softc *sc, int ifmedia, uint32_t *phy_cap_mask)
906 {
907 /* Get global options (duplex), type and subtype bits */
908 int ifmedia_masked = ifmedia & (IFM_GMASK | IFM_NMASK | IFM_TMASK);
909 efx_phy_media_type_t medium_type;
910 boolean_t mode_found = B_FALSE;
911 uint32_t cap_mask, mode_cap_mask;
912 efx_link_mode_t mode;
913 efx_phy_cap_type_t phy_cap;
914
915 efx_phy_media_type_get(sc->enp, &medium_type);
916 if (medium_type >= nitems(sfxge_link_mode)) {
917 if_printf(sc->ifnet, "unexpected media type %d\n", medium_type);
918 return (EINVAL);
919 }
920
921 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask);
922
923 for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) {
924 if (ifmedia_masked == sfxge_link_mode[medium_type][mode]) {
925 mode_found = B_TRUE;
926 break;
927 }
928 }
929
930 if (!mode_found) {
931 /*
932 * If media is not in the table, it must be IFM_AUTO.
933 */
934 KASSERT((cap_mask & (1 << EFX_PHY_CAP_AN)) &&
935 ifmedia_masked == (IFM_ETHER | IFM_AUTO),
936 ("%s: no mode for media %#x", __func__, ifmedia));
937 *phy_cap_mask = (cap_mask & ~(1 << EFX_PHY_CAP_ASYM));
938 return (0);
939 }
940
941 phy_cap = sfxge_link_mode_to_phy_cap(mode);
942 if (phy_cap == EFX_PHY_CAP_INVALID) {
943 if_printf(sc->ifnet,
944 "cannot map link mode %d to phy capability\n",
945 mode);
946 return (EINVAL);
947 }
948
949 mode_cap_mask = (1 << phy_cap);
950 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_AN);
951 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS
952 if (ifmedia & IFM_ETH_RXPAUSE)
953 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE);
954 if (!(ifmedia & IFM_ETH_TXPAUSE))
955 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_ASYM);
956 #else
957 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE);
958 #endif
959
960 *phy_cap_mask = mode_cap_mask;
961 return (0);
962 }
963
964 static int
sfxge_media_change(struct ifnet * ifp)965 sfxge_media_change(struct ifnet *ifp)
966 {
967 struct sfxge_softc *sc;
968 struct ifmedia_entry *ifm;
969 int rc;
970 uint32_t phy_cap_mask;
971
972 sc = ifp->if_softc;
973 ifm = sc->media.ifm_cur;
974
975 SFXGE_ADAPTER_LOCK(sc);
976
977 if (!SFXGE_RUNNING(sc)) {
978 rc = 0;
979 goto out;
980 }
981
982 rc = efx_mac_fcntl_set(sc->enp, sfxge_port_wanted_fc(sc), B_TRUE);
983 if (rc != 0)
984 goto out;
985
986 if ((rc = sfxge_phy_cap_mask(sc, ifm->ifm_media, &phy_cap_mask)) != 0)
987 goto out;
988
989 rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask);
990 out:
991 SFXGE_ADAPTER_UNLOCK(sc);
992
993 return (rc);
994 }
995
sfxge_port_ifmedia_init(struct sfxge_softc * sc)996 int sfxge_port_ifmedia_init(struct sfxge_softc *sc)
997 {
998 efx_phy_media_type_t medium_type;
999 uint32_t cap_mask, mode_cap_mask;
1000 efx_link_mode_t mode;
1001 efx_phy_cap_type_t phy_cap;
1002 int mode_ifm, best_mode_ifm = 0;
1003 int rc;
1004
1005 /*
1006 * We need port state to initialise the ifmedia list.
1007 * It requires initialized NIC what is already done in
1008 * sfxge_create() when resources are estimated.
1009 */
1010 if ((rc = efx_filter_init(sc->enp)) != 0)
1011 goto out1;
1012 if ((rc = efx_port_init(sc->enp)) != 0)
1013 goto out2;
1014
1015 /*
1016 * Register ifconfig callbacks for querying and setting the
1017 * link mode and link status.
1018 */
1019 ifmedia_init(&sc->media, IFM_IMASK, sfxge_media_change,
1020 sfxge_media_status);
1021
1022 /*
1023 * Map firmware medium type and capabilities to ifmedia types.
1024 * ifmedia does not distinguish between forcing the link mode
1025 * and disabling auto-negotiation. 1000BASE-T and 10GBASE-T
1026 * require AN even if only one link mode is enabled, and for
1027 * 100BASE-TX it is useful even if the link mode is forced.
1028 * Therefore we never disable auto-negotiation.
1029 *
1030 * Also enable and advertise flow control by default.
1031 */
1032
1033 efx_phy_media_type_get(sc->enp, &medium_type);
1034 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask);
1035
1036 for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) {
1037 phy_cap = sfxge_link_mode_to_phy_cap(mode);
1038 if (phy_cap == EFX_PHY_CAP_INVALID)
1039 continue;
1040
1041 mode_cap_mask = (1 << phy_cap);
1042 mode_ifm = sfxge_link_mode[medium_type][mode];
1043
1044 if ((cap_mask & mode_cap_mask) && mode_ifm) {
1045 /* No flow-control */
1046 ifmedia_add(&sc->media, mode_ifm, 0, NULL);
1047
1048 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS
1049 /* Respond-only. If using AN, we implicitly
1050 * offer symmetric as well, but that doesn't
1051 * mean we *have* to generate pause frames.
1052 */
1053 mode_ifm |= IFM_ETH_RXPAUSE;
1054 ifmedia_add(&sc->media, mode_ifm, 0, NULL);
1055
1056 /* Symmetric */
1057 mode_ifm |= IFM_ETH_TXPAUSE;
1058 ifmedia_add(&sc->media, mode_ifm, 0, NULL);
1059 #endif
1060
1061 /* Link modes are numbered in order of speed,
1062 * so assume the last one available is the best.
1063 */
1064 best_mode_ifm = mode_ifm;
1065 }
1066 }
1067
1068 if (cap_mask & (1 << EFX_PHY_CAP_AN)) {
1069 /* Add autoselect mode. */
1070 mode_ifm = IFM_ETHER | IFM_AUTO;
1071 ifmedia_add(&sc->media, mode_ifm, 0, NULL);
1072 best_mode_ifm = mode_ifm;
1073 }
1074
1075 if (best_mode_ifm != 0)
1076 ifmedia_set(&sc->media, best_mode_ifm);
1077
1078 /* Now discard port state until interface is started. */
1079 efx_port_fini(sc->enp);
1080 out2:
1081 efx_filter_fini(sc->enp);
1082 out1:
1083 return (rc);
1084 }
1085