1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * The views and conclusions contained in the software and documentation are
29 * those of the authors and should not be interpreted as representing official
30 * policies, either expressed or implied, of the FreeBSD Project.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: stable/12/sys/dev/sfxge/common/efx_rx.c 342328 2018-12-21 16:10:31Z arybchik $");
35
36 #include "efx.h"
37 #include "efx_impl.h"
38
39
40 #if EFSYS_OPT_SIENA
41
42 static __checkReturn efx_rc_t
43 siena_rx_init(
44 __in efx_nic_t *enp);
45
46 static void
47 siena_rx_fini(
48 __in efx_nic_t *enp);
49
50 #if EFSYS_OPT_RX_SCATTER
51 static __checkReturn efx_rc_t
52 siena_rx_scatter_enable(
53 __in efx_nic_t *enp,
54 __in unsigned int buf_size);
55 #endif /* EFSYS_OPT_RX_SCATTER */
56
57 #if EFSYS_OPT_RX_SCALE
58 static __checkReturn efx_rc_t
59 siena_rx_scale_mode_set(
60 __in efx_nic_t *enp,
61 __in efx_rx_hash_alg_t alg,
62 __in efx_rx_hash_type_t type,
63 __in boolean_t insert);
64
65 static __checkReturn efx_rc_t
66 siena_rx_scale_key_set(
67 __in efx_nic_t *enp,
68 __in_ecount(n) uint8_t *key,
69 __in size_t n);
70
71 static __checkReturn efx_rc_t
72 siena_rx_scale_tbl_set(
73 __in efx_nic_t *enp,
74 __in_ecount(n) unsigned int *table,
75 __in size_t n);
76
77 static __checkReturn uint32_t
78 siena_rx_prefix_hash(
79 __in efx_nic_t *enp,
80 __in efx_rx_hash_alg_t func,
81 __in uint8_t *buffer);
82
83 #endif /* EFSYS_OPT_RX_SCALE */
84
85 static __checkReturn efx_rc_t
86 siena_rx_prefix_pktlen(
87 __in efx_nic_t *enp,
88 __in uint8_t *buffer,
89 __out uint16_t *lengthp);
90
91 static void
92 siena_rx_qpost(
93 __in efx_rxq_t *erp,
94 __in_ecount(n) efsys_dma_addr_t *addrp,
95 __in size_t size,
96 __in unsigned int n,
97 __in unsigned int completed,
98 __in unsigned int added);
99
100 static void
101 siena_rx_qpush(
102 __in efx_rxq_t *erp,
103 __in unsigned int added,
104 __inout unsigned int *pushedp);
105
106 static __checkReturn efx_rc_t
107 siena_rx_qflush(
108 __in efx_rxq_t *erp);
109
110 static void
111 siena_rx_qenable(
112 __in efx_rxq_t *erp);
113
114 static __checkReturn efx_rc_t
115 siena_rx_qcreate(
116 __in efx_nic_t *enp,
117 __in unsigned int index,
118 __in unsigned int label,
119 __in efx_rxq_type_t type,
120 __in efsys_mem_t *esmp,
121 __in size_t n,
122 __in uint32_t id,
123 __in efx_evq_t *eep,
124 __in efx_rxq_t *erp);
125
126 static void
127 siena_rx_qdestroy(
128 __in efx_rxq_t *erp);
129
130 #endif /* EFSYS_OPT_SIENA */
131
132
133 #if EFSYS_OPT_SIENA
134 static const efx_rx_ops_t __efx_rx_siena_ops = {
135 siena_rx_init, /* erxo_init */
136 siena_rx_fini, /* erxo_fini */
137 #if EFSYS_OPT_RX_SCATTER
138 siena_rx_scatter_enable, /* erxo_scatter_enable */
139 #endif
140 #if EFSYS_OPT_RX_SCALE
141 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
142 siena_rx_scale_key_set, /* erxo_scale_key_set */
143 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
144 siena_rx_prefix_hash, /* erxo_prefix_hash */
145 #endif
146 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
147 siena_rx_qpost, /* erxo_qpost */
148 siena_rx_qpush, /* erxo_qpush */
149 siena_rx_qflush, /* erxo_qflush */
150 siena_rx_qenable, /* erxo_qenable */
151 siena_rx_qcreate, /* erxo_qcreate */
152 siena_rx_qdestroy, /* erxo_qdestroy */
153 };
154 #endif /* EFSYS_OPT_SIENA */
155
156 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
157 static const efx_rx_ops_t __efx_rx_ef10_ops = {
158 ef10_rx_init, /* erxo_init */
159 ef10_rx_fini, /* erxo_fini */
160 #if EFSYS_OPT_RX_SCATTER
161 ef10_rx_scatter_enable, /* erxo_scatter_enable */
162 #endif
163 #if EFSYS_OPT_RX_SCALE
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
168 #endif
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 ef10_rx_qflush, /* erxo_qflush */
173 ef10_rx_qenable, /* erxo_qenable */
174 ef10_rx_qcreate, /* erxo_qcreate */
175 ef10_rx_qdestroy, /* erxo_qdestroy */
176 };
177 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
178
179
180 __checkReturn efx_rc_t
efx_rx_init(__inout efx_nic_t * enp)181 efx_rx_init(
182 __inout efx_nic_t *enp)
183 {
184 const efx_rx_ops_t *erxop;
185 efx_rc_t rc;
186
187 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
188 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
189
190 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
191 rc = EINVAL;
192 goto fail1;
193 }
194
195 if (enp->en_mod_flags & EFX_MOD_RX) {
196 rc = EINVAL;
197 goto fail2;
198 }
199
200 switch (enp->en_family) {
201 #if EFSYS_OPT_SIENA
202 case EFX_FAMILY_SIENA:
203 erxop = &__efx_rx_siena_ops;
204 break;
205 #endif /* EFSYS_OPT_SIENA */
206
207 #if EFSYS_OPT_HUNTINGTON
208 case EFX_FAMILY_HUNTINGTON:
209 erxop = &__efx_rx_ef10_ops;
210 break;
211 #endif /* EFSYS_OPT_HUNTINGTON */
212
213 #if EFSYS_OPT_MEDFORD
214 case EFX_FAMILY_MEDFORD:
215 erxop = &__efx_rx_ef10_ops;
216 break;
217 #endif /* EFSYS_OPT_MEDFORD */
218
219 default:
220 EFSYS_ASSERT(0);
221 rc = ENOTSUP;
222 goto fail3;
223 }
224
225 if ((rc = erxop->erxo_init(enp)) != 0)
226 goto fail4;
227
228 enp->en_erxop = erxop;
229 enp->en_mod_flags |= EFX_MOD_RX;
230 return (0);
231
232 fail4:
233 EFSYS_PROBE(fail4);
234 fail3:
235 EFSYS_PROBE(fail3);
236 fail2:
237 EFSYS_PROBE(fail2);
238 fail1:
239 EFSYS_PROBE1(fail1, efx_rc_t, rc);
240
241 enp->en_erxop = NULL;
242 enp->en_mod_flags &= ~EFX_MOD_RX;
243 return (rc);
244 }
245
246 void
efx_rx_fini(__in efx_nic_t * enp)247 efx_rx_fini(
248 __in efx_nic_t *enp)
249 {
250 const efx_rx_ops_t *erxop = enp->en_erxop;
251
252 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
253 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
254 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
255 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
256
257 erxop->erxo_fini(enp);
258
259 enp->en_erxop = NULL;
260 enp->en_mod_flags &= ~EFX_MOD_RX;
261 }
262
263 #if EFSYS_OPT_RX_SCATTER
264 __checkReturn efx_rc_t
efx_rx_scatter_enable(__in efx_nic_t * enp,__in unsigned int buf_size)265 efx_rx_scatter_enable(
266 __in efx_nic_t *enp,
267 __in unsigned int buf_size)
268 {
269 const efx_rx_ops_t *erxop = enp->en_erxop;
270 efx_rc_t rc;
271
272 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
273 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
274
275 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
276 goto fail1;
277
278 return (0);
279
280 fail1:
281 EFSYS_PROBE1(fail1, efx_rc_t, rc);
282 return (rc);
283 }
284 #endif /* EFSYS_OPT_RX_SCATTER */
285
286 #if EFSYS_OPT_RX_SCALE
287 __checkReturn efx_rc_t
efx_rx_hash_support_get(__in efx_nic_t * enp,__out efx_rx_hash_support_t * supportp)288 efx_rx_hash_support_get(
289 __in efx_nic_t *enp,
290 __out efx_rx_hash_support_t *supportp)
291 {
292 efx_rc_t rc;
293
294 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
295 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
296
297 if (supportp == NULL) {
298 rc = EINVAL;
299 goto fail1;
300 }
301
302 /* Report if resources are available to insert RX hash value */
303 *supportp = enp->en_hash_support;
304
305 return (0);
306
307 fail1:
308 EFSYS_PROBE1(fail1, efx_rc_t, rc);
309
310 return (rc);
311 }
312
313 __checkReturn efx_rc_t
efx_rx_scale_support_get(__in efx_nic_t * enp,__out efx_rx_scale_support_t * supportp)314 efx_rx_scale_support_get(
315 __in efx_nic_t *enp,
316 __out efx_rx_scale_support_t *supportp)
317 {
318 efx_rc_t rc;
319
320 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
321 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
322
323 if (supportp == NULL) {
324 rc = EINVAL;
325 goto fail1;
326 }
327
328 /* Report if resources are available to support RSS */
329 *supportp = enp->en_rss_support;
330
331 return (0);
332
333 fail1:
334 EFSYS_PROBE1(fail1, efx_rc_t, rc);
335
336 return (rc);
337 }
338
339 __checkReturn efx_rc_t
efx_rx_scale_mode_set(__in efx_nic_t * enp,__in efx_rx_hash_alg_t alg,__in efx_rx_hash_type_t type,__in boolean_t insert)340 efx_rx_scale_mode_set(
341 __in efx_nic_t *enp,
342 __in efx_rx_hash_alg_t alg,
343 __in efx_rx_hash_type_t type,
344 __in boolean_t insert)
345 {
346 const efx_rx_ops_t *erxop = enp->en_erxop;
347 efx_rc_t rc;
348
349 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
350 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
351
352 if (erxop->erxo_scale_mode_set != NULL) {
353 if ((rc = erxop->erxo_scale_mode_set(enp, alg,
354 type, insert)) != 0)
355 goto fail1;
356 }
357
358 return (0);
359
360 fail1:
361 EFSYS_PROBE1(fail1, efx_rc_t, rc);
362 return (rc);
363 }
364 #endif /* EFSYS_OPT_RX_SCALE */
365
366 #if EFSYS_OPT_RX_SCALE
367 __checkReturn efx_rc_t
efx_rx_scale_key_set(__in efx_nic_t * enp,__in_ecount (n)uint8_t * key,__in size_t n)368 efx_rx_scale_key_set(
369 __in efx_nic_t *enp,
370 __in_ecount(n) uint8_t *key,
371 __in size_t n)
372 {
373 const efx_rx_ops_t *erxop = enp->en_erxop;
374 efx_rc_t rc;
375
376 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
377 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
378
379 if ((rc = erxop->erxo_scale_key_set(enp, key, n)) != 0)
380 goto fail1;
381
382 return (0);
383
384 fail1:
385 EFSYS_PROBE1(fail1, efx_rc_t, rc);
386
387 return (rc);
388 }
389 #endif /* EFSYS_OPT_RX_SCALE */
390
391 #if EFSYS_OPT_RX_SCALE
392 __checkReturn efx_rc_t
efx_rx_scale_tbl_set(__in efx_nic_t * enp,__in_ecount (n)unsigned int * table,__in size_t n)393 efx_rx_scale_tbl_set(
394 __in efx_nic_t *enp,
395 __in_ecount(n) unsigned int *table,
396 __in size_t n)
397 {
398 const efx_rx_ops_t *erxop = enp->en_erxop;
399 efx_rc_t rc;
400
401 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
402 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
403
404 if ((rc = erxop->erxo_scale_tbl_set(enp, table, n)) != 0)
405 goto fail1;
406
407 return (0);
408
409 fail1:
410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
411
412 return (rc);
413 }
414 #endif /* EFSYS_OPT_RX_SCALE */
415
416 void
efx_rx_qpost(__in efx_rxq_t * erp,__in_ecount (n)efsys_dma_addr_t * addrp,__in size_t size,__in unsigned int n,__in unsigned int completed,__in unsigned int added)417 efx_rx_qpost(
418 __in efx_rxq_t *erp,
419 __in_ecount(n) efsys_dma_addr_t *addrp,
420 __in size_t size,
421 __in unsigned int n,
422 __in unsigned int completed,
423 __in unsigned int added)
424 {
425 efx_nic_t *enp = erp->er_enp;
426 const efx_rx_ops_t *erxop = enp->en_erxop;
427
428 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
429
430 erxop->erxo_qpost(erp, addrp, size, n, completed, added);
431 }
432
433 void
efx_rx_qpush(__in efx_rxq_t * erp,__in unsigned int added,__inout unsigned int * pushedp)434 efx_rx_qpush(
435 __in efx_rxq_t *erp,
436 __in unsigned int added,
437 __inout unsigned int *pushedp)
438 {
439 efx_nic_t *enp = erp->er_enp;
440 const efx_rx_ops_t *erxop = enp->en_erxop;
441
442 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
443
444 erxop->erxo_qpush(erp, added, pushedp);
445 }
446
447 __checkReturn efx_rc_t
efx_rx_qflush(__in efx_rxq_t * erp)448 efx_rx_qflush(
449 __in efx_rxq_t *erp)
450 {
451 efx_nic_t *enp = erp->er_enp;
452 const efx_rx_ops_t *erxop = enp->en_erxop;
453 efx_rc_t rc;
454
455 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
456
457 if ((rc = erxop->erxo_qflush(erp)) != 0)
458 goto fail1;
459
460 return (0);
461
462 fail1:
463 EFSYS_PROBE1(fail1, efx_rc_t, rc);
464
465 return (rc);
466 }
467
468 void
efx_rx_qenable(__in efx_rxq_t * erp)469 efx_rx_qenable(
470 __in efx_rxq_t *erp)
471 {
472 efx_nic_t *enp = erp->er_enp;
473 const efx_rx_ops_t *erxop = enp->en_erxop;
474
475 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
476
477 erxop->erxo_qenable(erp);
478 }
479
480 __checkReturn efx_rc_t
efx_rx_qcreate(__in efx_nic_t * enp,__in unsigned int index,__in unsigned int label,__in efx_rxq_type_t type,__in efsys_mem_t * esmp,__in size_t n,__in uint32_t id,__in efx_evq_t * eep,__deref_out efx_rxq_t ** erpp)481 efx_rx_qcreate(
482 __in efx_nic_t *enp,
483 __in unsigned int index,
484 __in unsigned int label,
485 __in efx_rxq_type_t type,
486 __in efsys_mem_t *esmp,
487 __in size_t n,
488 __in uint32_t id,
489 __in efx_evq_t *eep,
490 __deref_out efx_rxq_t **erpp)
491 {
492 const efx_rx_ops_t *erxop = enp->en_erxop;
493 efx_rxq_t *erp;
494 efx_rc_t rc;
495
496 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
497 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
498
499 /* Allocate an RXQ object */
500 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
501
502 if (erp == NULL) {
503 rc = ENOMEM;
504 goto fail1;
505 }
506
507 erp->er_magic = EFX_RXQ_MAGIC;
508 erp->er_enp = enp;
509 erp->er_index = index;
510 erp->er_mask = n - 1;
511 erp->er_esmp = esmp;
512
513 if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
514 eep, erp)) != 0)
515 goto fail2;
516
517 enp->en_rx_qcount++;
518 *erpp = erp;
519
520 return (0);
521
522 fail2:
523 EFSYS_PROBE(fail2);
524
525 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
526 fail1:
527 EFSYS_PROBE1(fail1, efx_rc_t, rc);
528
529 return (rc);
530 }
531
532 void
efx_rx_qdestroy(__in efx_rxq_t * erp)533 efx_rx_qdestroy(
534 __in efx_rxq_t *erp)
535 {
536 efx_nic_t *enp = erp->er_enp;
537 const efx_rx_ops_t *erxop = enp->en_erxop;
538
539 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
540
541 erxop->erxo_qdestroy(erp);
542 }
543
544 __checkReturn efx_rc_t
efx_pseudo_hdr_pkt_length_get(__in efx_rxq_t * erp,__in uint8_t * buffer,__out uint16_t * lengthp)545 efx_pseudo_hdr_pkt_length_get(
546 __in efx_rxq_t *erp,
547 __in uint8_t *buffer,
548 __out uint16_t *lengthp)
549 {
550 efx_nic_t *enp = erp->er_enp;
551 const efx_rx_ops_t *erxop = enp->en_erxop;
552
553 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
554
555 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
556 }
557
558 #if EFSYS_OPT_RX_SCALE
559 __checkReturn uint32_t
efx_pseudo_hdr_hash_get(__in efx_rxq_t * erp,__in efx_rx_hash_alg_t func,__in uint8_t * buffer)560 efx_pseudo_hdr_hash_get(
561 __in efx_rxq_t *erp,
562 __in efx_rx_hash_alg_t func,
563 __in uint8_t *buffer)
564 {
565 efx_nic_t *enp = erp->er_enp;
566 const efx_rx_ops_t *erxop = enp->en_erxop;
567
568 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
569
570 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
571 return (erxop->erxo_prefix_hash(enp, func, buffer));
572 }
573 #endif /* EFSYS_OPT_RX_SCALE */
574
575 #if EFSYS_OPT_SIENA
576
577 static __checkReturn efx_rc_t
siena_rx_init(__in efx_nic_t * enp)578 siena_rx_init(
579 __in efx_nic_t *enp)
580 {
581 efx_oword_t oword;
582 unsigned int index;
583
584 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
585
586 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
587 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
588 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
589 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
590 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
591 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
592 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
593
594 /* Zero the RSS table */
595 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
596 index++) {
597 EFX_ZERO_OWORD(oword);
598 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
599 index, &oword, B_TRUE);
600 }
601
602 #if EFSYS_OPT_RX_SCALE
603 /* The RSS key and indirection table are writable. */
604 enp->en_rss_support = EFX_RX_SCALE_EXCLUSIVE;
605
606 /* Hardware can insert RX hash with/without RSS */
607 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
608 #endif /* EFSYS_OPT_RX_SCALE */
609
610 return (0);
611 }
612
613 #if EFSYS_OPT_RX_SCATTER
614 static __checkReturn efx_rc_t
siena_rx_scatter_enable(__in efx_nic_t * enp,__in unsigned int buf_size)615 siena_rx_scatter_enable(
616 __in efx_nic_t *enp,
617 __in unsigned int buf_size)
618 {
619 unsigned int nbuf32;
620 efx_oword_t oword;
621 efx_rc_t rc;
622
623 nbuf32 = buf_size / 32;
624 if ((nbuf32 == 0) ||
625 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
626 ((buf_size % 32) != 0)) {
627 rc = EINVAL;
628 goto fail1;
629 }
630
631 if (enp->en_rx_qcount > 0) {
632 rc = EBUSY;
633 goto fail2;
634 }
635
636 /* Set scatter buffer size */
637 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
638 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
639 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
640
641 /* Enable scatter for packets not matching a filter */
642 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
643 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
644 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
645
646 return (0);
647
648 fail2:
649 EFSYS_PROBE(fail2);
650 fail1:
651 EFSYS_PROBE1(fail1, efx_rc_t, rc);
652
653 return (rc);
654 }
655 #endif /* EFSYS_OPT_RX_SCATTER */
656
657
658 #define EFX_RX_LFSR_HASH(_enp, _insert) \
659 do { \
660 efx_oword_t oword; \
661 \
662 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
663 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
664 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
665 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
666 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
667 (_insert) ? 1 : 0); \
668 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
669 \
670 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
671 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
672 &oword); \
673 EFX_SET_OWORD_FIELD(oword, \
674 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
675 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
676 &oword); \
677 } \
678 \
679 _NOTE(CONSTANTCONDITION) \
680 } while (B_FALSE)
681
682 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
683 do { \
684 efx_oword_t oword; \
685 \
686 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
687 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
688 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
689 (_ip) ? 1 : 0); \
690 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
691 (_tcp) ? 0 : 1); \
692 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
693 (_insert) ? 1 : 0); \
694 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
695 \
696 _NOTE(CONSTANTCONDITION) \
697 } while (B_FALSE)
698
699 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
700 do { \
701 efx_oword_t oword; \
702 \
703 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
704 EFX_SET_OWORD_FIELD(oword, \
705 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
706 EFX_SET_OWORD_FIELD(oword, \
707 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
708 EFX_SET_OWORD_FIELD(oword, \
709 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
710 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
711 \
712 (_rc) = 0; \
713 \
714 _NOTE(CONSTANTCONDITION) \
715 } while (B_FALSE)
716
717
718 #if EFSYS_OPT_RX_SCALE
719
720 static __checkReturn efx_rc_t
siena_rx_scale_mode_set(__in efx_nic_t * enp,__in efx_rx_hash_alg_t alg,__in efx_rx_hash_type_t type,__in boolean_t insert)721 siena_rx_scale_mode_set(
722 __in efx_nic_t *enp,
723 __in efx_rx_hash_alg_t alg,
724 __in efx_rx_hash_type_t type,
725 __in boolean_t insert)
726 {
727 efx_rc_t rc;
728
729 switch (alg) {
730 case EFX_RX_HASHALG_LFSR:
731 EFX_RX_LFSR_HASH(enp, insert);
732 break;
733
734 case EFX_RX_HASHALG_TOEPLITZ:
735 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
736 type & EFX_RX_HASH_IPV4,
737 type & EFX_RX_HASH_TCPIPV4);
738
739 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
740 type & EFX_RX_HASH_IPV6,
741 type & EFX_RX_HASH_TCPIPV6,
742 rc);
743 if (rc != 0)
744 goto fail1;
745
746 break;
747
748 default:
749 rc = EINVAL;
750 goto fail2;
751 }
752
753 return (0);
754
755 fail2:
756 EFSYS_PROBE(fail2);
757 fail1:
758 EFSYS_PROBE1(fail1, efx_rc_t, rc);
759
760 EFX_RX_LFSR_HASH(enp, B_FALSE);
761
762 return (rc);
763 }
764 #endif
765
766 #if EFSYS_OPT_RX_SCALE
767 static __checkReturn efx_rc_t
siena_rx_scale_key_set(__in efx_nic_t * enp,__in_ecount (n)uint8_t * key,__in size_t n)768 siena_rx_scale_key_set(
769 __in efx_nic_t *enp,
770 __in_ecount(n) uint8_t *key,
771 __in size_t n)
772 {
773 efx_oword_t oword;
774 unsigned int byte;
775 unsigned int offset;
776 efx_rc_t rc;
777
778 byte = 0;
779
780 /* Write Toeplitz IPv4 hash key */
781 EFX_ZERO_OWORD(oword);
782 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
783 offset > 0 && byte < n;
784 --offset)
785 oword.eo_u8[offset - 1] = key[byte++];
786
787 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
788
789 byte = 0;
790
791 /* Verify Toeplitz IPv4 hash key */
792 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
793 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
794 offset > 0 && byte < n;
795 --offset) {
796 if (oword.eo_u8[offset - 1] != key[byte++]) {
797 rc = EFAULT;
798 goto fail1;
799 }
800 }
801
802 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
803 goto done;
804
805 byte = 0;
806
807 /* Write Toeplitz IPv6 hash key 3 */
808 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
809 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
810 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
811 offset > 0 && byte < n;
812 --offset)
813 oword.eo_u8[offset - 1] = key[byte++];
814
815 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
816
817 /* Write Toeplitz IPv6 hash key 2 */
818 EFX_ZERO_OWORD(oword);
819 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
820 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
821 offset > 0 && byte < n;
822 --offset)
823 oword.eo_u8[offset - 1] = key[byte++];
824
825 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
826
827 /* Write Toeplitz IPv6 hash key 1 */
828 EFX_ZERO_OWORD(oword);
829 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
830 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
831 offset > 0 && byte < n;
832 --offset)
833 oword.eo_u8[offset - 1] = key[byte++];
834
835 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
836
837 byte = 0;
838
839 /* Verify Toeplitz IPv6 hash key 3 */
840 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
841 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
842 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
843 offset > 0 && byte < n;
844 --offset) {
845 if (oword.eo_u8[offset - 1] != key[byte++]) {
846 rc = EFAULT;
847 goto fail2;
848 }
849 }
850
851 /* Verify Toeplitz IPv6 hash key 2 */
852 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
853 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
854 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
855 offset > 0 && byte < n;
856 --offset) {
857 if (oword.eo_u8[offset - 1] != key[byte++]) {
858 rc = EFAULT;
859 goto fail3;
860 }
861 }
862
863 /* Verify Toeplitz IPv6 hash key 1 */
864 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
865 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
866 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
867 offset > 0 && byte < n;
868 --offset) {
869 if (oword.eo_u8[offset - 1] != key[byte++]) {
870 rc = EFAULT;
871 goto fail4;
872 }
873 }
874
875 done:
876 return (0);
877
878 fail4:
879 EFSYS_PROBE(fail4);
880 fail3:
881 EFSYS_PROBE(fail3);
882 fail2:
883 EFSYS_PROBE(fail2);
884 fail1:
885 EFSYS_PROBE1(fail1, efx_rc_t, rc);
886
887 return (rc);
888 }
889 #endif
890
891 #if EFSYS_OPT_RX_SCALE
892 static __checkReturn efx_rc_t
siena_rx_scale_tbl_set(__in efx_nic_t * enp,__in_ecount (n)unsigned int * table,__in size_t n)893 siena_rx_scale_tbl_set(
894 __in efx_nic_t *enp,
895 __in_ecount(n) unsigned int *table,
896 __in size_t n)
897 {
898 efx_oword_t oword;
899 int index;
900 efx_rc_t rc;
901
902 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
903 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
904
905 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
906 rc = EINVAL;
907 goto fail1;
908 }
909
910 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
911 uint32_t byte;
912
913 /* Calculate the entry to place in the table */
914 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
915
916 EFSYS_PROBE2(table, int, index, uint32_t, byte);
917
918 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
919
920 /* Write the table */
921 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
922 index, &oword, B_TRUE);
923 }
924
925 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
926 uint32_t byte;
927
928 /* Determine if we're starting a new batch */
929 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
930
931 /* Read the table */
932 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
933 index, &oword, B_TRUE);
934
935 /* Verify the entry */
936 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
937 rc = EFAULT;
938 goto fail2;
939 }
940 }
941
942 return (0);
943
944 fail2:
945 EFSYS_PROBE(fail2);
946 fail1:
947 EFSYS_PROBE1(fail1, efx_rc_t, rc);
948
949 return (rc);
950 }
951 #endif
952
953 /*
954 * Falcon/Siena pseudo-header
955 * --------------------------
956 *
957 * Receive packets are prefixed by an optional 16 byte pseudo-header.
958 * The pseudo-header is a byte array of one of the forms:
959 *
960 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
961 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
962 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
963 *
964 * where:
965 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
966 * LL.LL LFSR hash (16-bit big-endian)
967 */
968
969 #if EFSYS_OPT_RX_SCALE
970 static __checkReturn uint32_t
siena_rx_prefix_hash(__in efx_nic_t * enp,__in efx_rx_hash_alg_t func,__in uint8_t * buffer)971 siena_rx_prefix_hash(
972 __in efx_nic_t *enp,
973 __in efx_rx_hash_alg_t func,
974 __in uint8_t *buffer)
975 {
976 _NOTE(ARGUNUSED(enp))
977
978 switch (func) {
979 case EFX_RX_HASHALG_TOEPLITZ:
980 return ((buffer[12] << 24) |
981 (buffer[13] << 16) |
982 (buffer[14] << 8) |
983 buffer[15]);
984
985 case EFX_RX_HASHALG_LFSR:
986 return ((buffer[14] << 8) | buffer[15]);
987
988 default:
989 EFSYS_ASSERT(0);
990 return (0);
991 }
992 }
993 #endif /* EFSYS_OPT_RX_SCALE */
994
995 static __checkReturn efx_rc_t
siena_rx_prefix_pktlen(__in efx_nic_t * enp,__in uint8_t * buffer,__out uint16_t * lengthp)996 siena_rx_prefix_pktlen(
997 __in efx_nic_t *enp,
998 __in uint8_t *buffer,
999 __out uint16_t *lengthp)
1000 {
1001 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1002
1003 /* Not supported by Falcon/Siena hardware */
1004 EFSYS_ASSERT(0);
1005 return (ENOTSUP);
1006 }
1007
1008
1009 static void
siena_rx_qpost(__in efx_rxq_t * erp,__in_ecount (n)efsys_dma_addr_t * addrp,__in size_t size,__in unsigned int n,__in unsigned int completed,__in unsigned int added)1010 siena_rx_qpost(
1011 __in efx_rxq_t *erp,
1012 __in_ecount(n) efsys_dma_addr_t *addrp,
1013 __in size_t size,
1014 __in unsigned int n,
1015 __in unsigned int completed,
1016 __in unsigned int added)
1017 {
1018 efx_qword_t qword;
1019 unsigned int i;
1020 unsigned int offset;
1021 unsigned int id;
1022
1023 /* The client driver must not overfill the queue */
1024 EFSYS_ASSERT3U(added - completed + n, <=,
1025 EFX_RXQ_LIMIT(erp->er_mask + 1));
1026
1027 id = added & (erp->er_mask);
1028 for (i = 0; i < n; i++) {
1029 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1030 unsigned int, id, efsys_dma_addr_t, addrp[i],
1031 size_t, size);
1032
1033 EFX_POPULATE_QWORD_3(qword,
1034 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1035 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1036 (uint32_t)(addrp[i] & 0xffffffff),
1037 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1038 (uint32_t)(addrp[i] >> 32));
1039
1040 offset = id * sizeof (efx_qword_t);
1041 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1042
1043 id = (id + 1) & (erp->er_mask);
1044 }
1045 }
1046
1047 static void
siena_rx_qpush(__in efx_rxq_t * erp,__in unsigned int added,__inout unsigned int * pushedp)1048 siena_rx_qpush(
1049 __in efx_rxq_t *erp,
1050 __in unsigned int added,
1051 __inout unsigned int *pushedp)
1052 {
1053 efx_nic_t *enp = erp->er_enp;
1054 unsigned int pushed = *pushedp;
1055 uint32_t wptr;
1056 efx_oword_t oword;
1057 efx_dword_t dword;
1058
1059 /* All descriptors are pushed */
1060 *pushedp = added;
1061
1062 /* Push the populated descriptors out */
1063 wptr = added & erp->er_mask;
1064
1065 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1066
1067 /* Only write the third DWORD */
1068 EFX_POPULATE_DWORD_1(dword,
1069 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1070
1071 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1072 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1073 wptr, pushed & erp->er_mask);
1074 EFSYS_PIO_WRITE_BARRIER();
1075 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1076 erp->er_index, &dword, B_FALSE);
1077 }
1078
1079 static __checkReturn efx_rc_t
siena_rx_qflush(__in efx_rxq_t * erp)1080 siena_rx_qflush(
1081 __in efx_rxq_t *erp)
1082 {
1083 efx_nic_t *enp = erp->er_enp;
1084 efx_oword_t oword;
1085 uint32_t label;
1086
1087 label = erp->er_index;
1088
1089 /* Flush the queue */
1090 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1091 FRF_AZ_RX_FLUSH_DESCQ, label);
1092 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1093
1094 return (0);
1095 }
1096
1097 static void
siena_rx_qenable(__in efx_rxq_t * erp)1098 siena_rx_qenable(
1099 __in efx_rxq_t *erp)
1100 {
1101 efx_nic_t *enp = erp->er_enp;
1102 efx_oword_t oword;
1103
1104 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1105
1106 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1107 erp->er_index, &oword, B_TRUE);
1108
1109 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1110 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1111 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1112
1113 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1114 erp->er_index, &oword, B_TRUE);
1115 }
1116
1117 static __checkReturn efx_rc_t
siena_rx_qcreate(__in efx_nic_t * enp,__in unsigned int index,__in unsigned int label,__in efx_rxq_type_t type,__in efsys_mem_t * esmp,__in size_t n,__in uint32_t id,__in efx_evq_t * eep,__in efx_rxq_t * erp)1118 siena_rx_qcreate(
1119 __in efx_nic_t *enp,
1120 __in unsigned int index,
1121 __in unsigned int label,
1122 __in efx_rxq_type_t type,
1123 __in efsys_mem_t *esmp,
1124 __in size_t n,
1125 __in uint32_t id,
1126 __in efx_evq_t *eep,
1127 __in efx_rxq_t *erp)
1128 {
1129 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1130 efx_oword_t oword;
1131 uint32_t size;
1132 boolean_t jumbo;
1133 efx_rc_t rc;
1134
1135 _NOTE(ARGUNUSED(esmp))
1136
1137 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1138 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1139 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1140 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1141
1142 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1143 EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1144
1145 if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
1146 rc = EINVAL;
1147 goto fail1;
1148 }
1149 if (index >= encp->enc_rxq_limit) {
1150 rc = EINVAL;
1151 goto fail2;
1152 }
1153 for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1154 size++)
1155 if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
1156 break;
1157 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1158 rc = EINVAL;
1159 goto fail3;
1160 }
1161
1162 switch (type) {
1163 case EFX_RXQ_TYPE_DEFAULT:
1164 jumbo = B_FALSE;
1165 break;
1166
1167 #if EFSYS_OPT_RX_SCATTER
1168 case EFX_RXQ_TYPE_SCATTER:
1169 jumbo = B_TRUE;
1170 break;
1171 #endif /* EFSYS_OPT_RX_SCATTER */
1172
1173 default:
1174 rc = EINVAL;
1175 goto fail4;
1176 }
1177
1178 /* Set up the new descriptor queue */
1179 EFX_POPULATE_OWORD_7(oword,
1180 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1181 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1182 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1183 FRF_AZ_RX_DESCQ_LABEL, label,
1184 FRF_AZ_RX_DESCQ_SIZE, size,
1185 FRF_AZ_RX_DESCQ_TYPE, 0,
1186 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1187
1188 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1189 erp->er_index, &oword, B_TRUE);
1190
1191 return (0);
1192
1193 fail4:
1194 EFSYS_PROBE(fail4);
1195 fail3:
1196 EFSYS_PROBE(fail3);
1197 fail2:
1198 EFSYS_PROBE(fail2);
1199 fail1:
1200 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1201
1202 return (rc);
1203 }
1204
1205 static void
siena_rx_qdestroy(__in efx_rxq_t * erp)1206 siena_rx_qdestroy(
1207 __in efx_rxq_t *erp)
1208 {
1209 efx_nic_t *enp = erp->er_enp;
1210 efx_oword_t oword;
1211
1212 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1213 --enp->en_rx_qcount;
1214
1215 /* Purge descriptor queue */
1216 EFX_ZERO_OWORD(oword);
1217
1218 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1219 erp->er_index, &oword, B_TRUE);
1220
1221 /* Free the RXQ object */
1222 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1223 }
1224
1225 static void
siena_rx_fini(__in efx_nic_t * enp)1226 siena_rx_fini(
1227 __in efx_nic_t *enp)
1228 {
1229 _NOTE(ARGUNUSED(enp))
1230 }
1231
1232 #endif /* EFSYS_OPT_SIENA */
1233