1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011-2013 Qlogic Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*
31 * File: qla_isr.c
32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD: stable/12/sys/dev/qlxgb/qla_isr.c 326255 2017-11-27 14:52:40Z pfg $");
37
38 #include "qla_os.h"
39 #include "qla_reg.h"
40 #include "qla_hw.h"
41 #include "qla_def.h"
42 #include "qla_inline.h"
43 #include "qla_ver.h"
44 #include "qla_glbl.h"
45 #include "qla_dbg.h"
46
47 static void qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp);
48 static void qla_replenish_jumbo_rx(qla_host_t *ha, qla_sds_t *sdsp);
49
50 /*
51 * Name: qla_rx_intr
52 * Function: Handles normal ethernet frames received
53 */
54 static void
qla_rx_intr(qla_host_t * ha,uint64_t data,uint32_t sds_idx,struct lro_ctrl * lro)55 qla_rx_intr(qla_host_t *ha, uint64_t data, uint32_t sds_idx,
56 struct lro_ctrl *lro)
57 {
58 uint32_t idx, length, status, ring;
59 qla_rx_buf_t *rxb;
60 struct mbuf *mp;
61 struct ifnet *ifp = ha->ifp;
62 qla_sds_t *sdsp;
63 struct ether_vlan_header *eh;
64
65 sdsp = &ha->hw.sds[sds_idx];
66
67 ring = (uint32_t)Q8_STAT_DESC_TYPE(data);
68 idx = (uint32_t)Q8_STAT_DESC_HANDLE(data);
69 length = (uint32_t)Q8_STAT_DESC_TOTAL_LENGTH(data);
70 status = (uint32_t)Q8_STAT_DESC_STATUS(data);
71
72 if (ring == 0) {
73 if ((idx >= NUM_RX_DESCRIPTORS) || (length > MCLBYTES)) {
74 device_printf(ha->pci_dev, "%s: ring[%d] index[0x%08x]"
75 " len[0x%08x] invalid\n",
76 __func__, ring, idx, length);
77 return;
78 }
79 } else {
80 if ((idx >= NUM_RX_JUMBO_DESCRIPTORS)||(length > MJUM9BYTES)) {
81 device_printf(ha->pci_dev, "%s: ring[%d] index[0x%08x]"
82 " len[0x%08x] invalid\n",
83 __func__, ring, idx, length);
84 return;
85 }
86 }
87
88 if (ring == 0)
89 rxb = &ha->rx_buf[idx];
90 else
91 rxb = &ha->rx_jbuf[idx];
92
93 QL_ASSERT((rxb != NULL),\
94 ("%s: [r, i, sds_idx]=[%d, 0x%x, %d] rxb != NULL\n",\
95 __func__, ring, idx, sds_idx));
96
97 mp = rxb->m_head;
98
99 QL_ASSERT((mp != NULL),\
100 ("%s: [r,i,rxb, sds_idx]=[%d, 0x%x, %p, %d] mp != NULL\n",\
101 __func__, ring, idx, rxb, sds_idx));
102
103 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
104
105 if (ring == 0) {
106 rxb->m_head = NULL;
107 rxb->next = sdsp->rxb_free;
108 sdsp->rxb_free = rxb;
109 sdsp->rx_free++;
110 } else {
111 rxb->m_head = NULL;
112 rxb->next = sdsp->rxjb_free;
113 sdsp->rxjb_free = rxb;
114 sdsp->rxj_free++;
115 }
116
117 mp->m_len = length;
118 mp->m_pkthdr.len = length;
119 mp->m_pkthdr.rcvif = ifp;
120
121 eh = mtod(mp, struct ether_vlan_header *);
122
123 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
124 uint32_t *data = (uint32_t *)eh;
125
126 mp->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
127 mp->m_flags |= M_VLANTAG;
128
129 *(data + 3) = *(data + 2);
130 *(data + 2) = *(data + 1);
131 *(data + 1) = *data;
132
133 m_adj(mp, ETHER_VLAN_ENCAP_LEN);
134 }
135
136 if (status == Q8_STAT_DESC_STATUS_CHKSUM_OK) {
137 mp->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID);
138 } else {
139 mp->m_pkthdr.csum_flags = 0;
140 }
141
142 if (lro->lro_cnt && (tcp_lro_rx(lro, mp, 0) == 0)) {
143 /* LRO packet has been successfully queued */
144 } else {
145 (*ifp->if_input)(ifp, mp);
146 }
147
148 if (sdsp->rx_free > std_replenish)
149 qla_replenish_normal_rx(ha, sdsp);
150
151 if (sdsp->rxj_free > jumbo_replenish)
152 qla_replenish_jumbo_rx(ha, sdsp);
153
154 return;
155 }
156
157 static void
qla_replenish_jumbo_rx(qla_host_t * ha,qla_sds_t * sdsp)158 qla_replenish_jumbo_rx(qla_host_t *ha, qla_sds_t *sdsp)
159 {
160 qla_rx_buf_t *rxb;
161 int count = jumbo_replenish;
162 uint32_t rxj_next;
163
164 if (!mtx_trylock(&ha->rxj_lock))
165 return;
166
167 rxj_next = ha->hw.rxj_next;
168
169 while (count--) {
170 rxb = sdsp->rxjb_free;
171
172 if (rxb == NULL)
173 break;
174
175 sdsp->rxjb_free = rxb->next;
176 sdsp->rxj_free--;
177
178
179 if (qla_get_mbuf(ha, rxb, NULL, RDS_RING_INDEX_JUMBO) == 0) {
180 qla_set_hw_rcv_desc(ha, RDS_RING_INDEX_JUMBO,
181 ha->hw.rxj_in, rxb->handle, rxb->paddr,
182 (rxb->m_head)->m_pkthdr.len);
183 ha->hw.rxj_in++;
184 if (ha->hw.rxj_in == NUM_RX_JUMBO_DESCRIPTORS)
185 ha->hw.rxj_in = 0;
186 ha->hw.rxj_next++;
187 if (ha->hw.rxj_next == NUM_RX_JUMBO_DESCRIPTORS)
188 ha->hw.rxj_next = 0;
189 } else {
190 device_printf(ha->pci_dev,
191 "%s: qla_get_mbuf [1,(%d),(%d)] failed\n",
192 __func__, ha->hw.rxj_in, rxb->handle);
193
194 rxb->m_head = NULL;
195 rxb->next = sdsp->rxjb_free;
196 sdsp->rxjb_free = rxb;
197 sdsp->rxj_free++;
198
199 break;
200 }
201 }
202
203 if (rxj_next != ha->hw.rxj_next) {
204 QL_UPDATE_RDS_PRODUCER_INDEX(ha, 1, ha->hw.rxj_next);
205 }
206 mtx_unlock(&ha->rxj_lock);
207 }
208
209 static void
qla_replenish_normal_rx(qla_host_t * ha,qla_sds_t * sdsp)210 qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp)
211 {
212 qla_rx_buf_t *rxb;
213 int count = std_replenish;
214 uint32_t rx_next;
215
216 if (!mtx_trylock(&ha->rx_lock))
217 return;
218
219 rx_next = ha->hw.rx_next;
220
221 while (count--) {
222 rxb = sdsp->rxb_free;
223
224 if (rxb == NULL)
225 break;
226
227 sdsp->rxb_free = rxb->next;
228 sdsp->rx_free--;
229
230 if (qla_get_mbuf(ha, rxb, NULL, RDS_RING_INDEX_NORMAL) == 0) {
231 qla_set_hw_rcv_desc(ha, RDS_RING_INDEX_NORMAL,
232 ha->hw.rx_in, rxb->handle, rxb->paddr,
233 (rxb->m_head)->m_pkthdr.len);
234 ha->hw.rx_in++;
235 if (ha->hw.rx_in == NUM_RX_DESCRIPTORS)
236 ha->hw.rx_in = 0;
237 ha->hw.rx_next++;
238 if (ha->hw.rx_next == NUM_RX_DESCRIPTORS)
239 ha->hw.rx_next = 0;
240 } else {
241 device_printf(ha->pci_dev,
242 "%s: qla_get_mbuf [0,(%d),(%d)] failed\n",
243 __func__, ha->hw.rx_in, rxb->handle);
244
245 rxb->m_head = NULL;
246 rxb->next = sdsp->rxb_free;
247 sdsp->rxb_free = rxb;
248 sdsp->rx_free++;
249
250 break;
251 }
252 }
253
254 if (rx_next != ha->hw.rx_next) {
255 QL_UPDATE_RDS_PRODUCER_INDEX(ha, 0, ha->hw.rx_next);
256 }
257 mtx_unlock(&ha->rx_lock);
258 }
259
260 /*
261 * Name: qla_isr
262 * Function: Main Interrupt Service Routine
263 */
264 static uint32_t
qla_rcv_isr(qla_host_t * ha,uint32_t sds_idx,uint32_t count)265 qla_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count)
266 {
267 device_t dev;
268 qla_hw_t *hw;
269 uint32_t comp_idx, desc_count;
270 q80_stat_desc_t *sdesc;
271 struct lro_ctrl *lro;
272 uint32_t ret = 0;
273
274 dev = ha->pci_dev;
275 hw = &ha->hw;
276
277 hw->sds[sds_idx].rcv_active = 1;
278 if (ha->flags.stop_rcv) {
279 hw->sds[sds_idx].rcv_active = 0;
280 return 0;
281 }
282
283 QL_DPRINT2((dev, "%s: [%d]enter\n", __func__, sds_idx));
284
285 /*
286 * receive interrupts
287 */
288 comp_idx = hw->sds[sds_idx].sdsr_next;
289 lro = &hw->sds[sds_idx].lro;
290
291 while (count--) {
292
293 sdesc = (q80_stat_desc_t *)
294 &hw->sds[sds_idx].sds_ring_base[comp_idx];
295
296 if (Q8_STAT_DESC_OWNER((sdesc->data[0])) !=
297 Q8_STAT_DESC_OWNER_HOST) {
298 QL_DPRINT2((dev, "%s: data %p sdsr_next 0x%08x\n",
299 __func__, (void *)sdesc->data[0], comp_idx));
300 break;
301 }
302
303 desc_count = Q8_STAT_DESC_COUNT((sdesc->data[0]));
304
305 switch (Q8_STAT_DESC_OPCODE((sdesc->data[0]))) {
306
307 case Q8_STAT_DESC_OPCODE_RCV_PKT:
308 case Q8_STAT_DESC_OPCODE_SYN_OFFLOAD:
309 qla_rx_intr(ha, (sdesc->data[0]), sds_idx, lro);
310
311 break;
312
313 default:
314 device_printf(dev, "%s: default 0x%llx!\n", __func__,
315 (long long unsigned int)sdesc->data[0]);
316 break;
317 }
318
319 while (desc_count--) {
320 sdesc->data[0] =
321 Q8_STAT_DESC_SET_OWNER(Q8_STAT_DESC_OWNER_FW);
322 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
323 sdesc = (q80_stat_desc_t *)
324 &hw->sds[sds_idx].sds_ring_base[comp_idx];
325 }
326 }
327
328 tcp_lro_flush_all(lro);
329
330 if (hw->sds[sds_idx].sdsr_next != comp_idx) {
331 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx);
332 }
333 hw->sds[sds_idx].sdsr_next = comp_idx;
334
335 sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx];
336 if ((sds_idx == 0) && (Q8_STAT_DESC_OWNER((sdesc->data[0])) ==
337 Q8_STAT_DESC_OWNER_HOST)) {
338 ret = -1;
339 }
340
341 hw->sds[sds_idx].rcv_active = 0;
342 return (ret);
343 }
344
345 void
qla_isr(void * arg)346 qla_isr(void *arg)
347 {
348 qla_ivec_t *ivec = arg;
349 qla_host_t *ha;
350 uint32_t sds_idx;
351 uint32_t ret;
352
353 ha = ivec->ha;
354 sds_idx = ivec->irq_rid - 1;
355
356 if (sds_idx >= ha->hw.num_sds_rings) {
357 device_printf(ha->pci_dev, "%s: bogus sds_idx 0x%x\n", __func__,
358 sds_idx);
359
360 return;
361 }
362
363 if (sds_idx == 0)
364 taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
365
366 ret = qla_rcv_isr(ha, sds_idx, rcv_pkt_thres);
367
368 if (sds_idx == 0)
369 taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
370
371 if (ret) {
372 taskqueue_enqueue(ha->irq_vec[sds_idx].rcv_tq,
373 &ha->irq_vec[sds_idx].rcv_task);
374 } else {
375 QL_ENABLE_INTERRUPTS(ha, sds_idx);
376 }
377 }
378
379 void
qla_rcv(void * context,int pending)380 qla_rcv(void *context, int pending)
381 {
382 qla_ivec_t *ivec = context;
383 qla_host_t *ha;
384 device_t dev;
385 qla_hw_t *hw;
386 uint32_t sds_idx;
387 uint32_t ret;
388 struct ifnet *ifp;
389
390 ha = ivec->ha;
391 dev = ha->pci_dev;
392 hw = &ha->hw;
393 sds_idx = ivec->irq_rid - 1;
394 ifp = ha->ifp;
395
396 do {
397 if (sds_idx == 0) {
398 if (qla_le32_to_host(*(hw->tx_cons)) != hw->txr_comp) {
399 taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
400 } else if ((ifp->if_snd.ifq_head != NULL) &&
401 QL_RUNNING(ifp)) {
402 taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
403 }
404 }
405 ret = qla_rcv_isr(ha, sds_idx, rcv_pkt_thres_d);
406 } while (ret);
407
408 if (sds_idx == 0)
409 taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
410
411 QL_ENABLE_INTERRUPTS(ha, sds_idx);
412 }
413
414