1 /* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
2 /* $NetBSD: qat_d15xx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
3
4 /*
5 * Copyright (c) 2019 Internet Initiative Japan, Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*
31 * Copyright(c) 2014 Intel Corporation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 *
36 * * Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * * Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in
40 * the documentation and/or other materials provided with the
41 * distribution.
42 * * Neither the name of Intel Corporation nor the names of its
43 * contributors may be used to endorse or promote products derived
44 * from this software without specific prior written permission.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 #include <sys/cdefs.h>
60 __FBSDID("$FreeBSD: stable/12/sys/dev/qat/qat_d15xx.c 367386 2020-11-05 15:55:23Z markj $");
61 #if 0
62 __KERNEL_RCSID(0, "$NetBSD: qat_d15xx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
63 #endif
64
65 #include <sys/param.h>
66 #include <sys/bus.h>
67 #include <sys/systm.h>
68
69 #include <machine/bus.h>
70
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcivar.h>
73
74 #include "qatreg.h"
75 #include "qat_hw17reg.h"
76 #include "qat_d15xxreg.h"
77 #include "qatvar.h"
78 #include "qat_hw17var.h"
79
80 static uint32_t
qat_d15xx_get_accel_mask(struct qat_softc * sc)81 qat_d15xx_get_accel_mask(struct qat_softc *sc)
82 {
83 uint32_t fusectl, strap;
84
85 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
86 strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_D15XX, 4);
87
88 return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_D15XX) &
89 ACCEL_MASK_D15XX);
90 }
91
92 static uint32_t
qat_d15xx_get_ae_mask(struct qat_softc * sc)93 qat_d15xx_get_ae_mask(struct qat_softc *sc)
94 {
95 uint32_t fusectl, me_strap, me_disable, ssms_disabled;
96
97 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
98 me_strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_D15XX, 4);
99
100 /* If SSMs are disabled, then disable the corresponding MEs */
101 ssms_disabled = (~qat_d15xx_get_accel_mask(sc)) & ACCEL_MASK_D15XX;
102 me_disable = 0x3;
103 while (ssms_disabled) {
104 if (ssms_disabled & 1)
105 me_strap |= me_disable;
106 ssms_disabled >>= 1;
107 me_disable <<= 2;
108 }
109
110 return (~(fusectl | me_strap)) & AE_MASK_D15XX;
111 }
112
113 static enum qat_sku
qat_d15xx_get_sku(struct qat_softc * sc)114 qat_d15xx_get_sku(struct qat_softc *sc)
115 {
116 switch (sc->sc_ae_num) {
117 case 8:
118 return QAT_SKU_2;
119 case MAX_AE_D15XX:
120 return QAT_SKU_4;
121 }
122
123 return QAT_SKU_UNKNOWN;
124 }
125
126 static uint32_t
qat_d15xx_get_accel_cap(struct qat_softc * sc)127 qat_d15xx_get_accel_cap(struct qat_softc *sc)
128 {
129 uint32_t cap, legfuse, strap;
130
131 legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
132 strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_D15XX, 4);
133
134 cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
135 QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
136 QAT_ACCEL_CAP_CIPHER +
137 QAT_ACCEL_CAP_AUTHENTICATION +
138 QAT_ACCEL_CAP_COMPRESSION +
139 QAT_ACCEL_CAP_ZUC +
140 QAT_ACCEL_CAP_SHA3;
141
142 if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
143 cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
144 cap &= ~QAT_ACCEL_CAP_CIPHER;
145 }
146 if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
147 cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
148 if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
149 cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
150 if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
151 cap &= ~QAT_ACCEL_CAP_COMPRESSION;
152 if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
153 cap &= ~QAT_ACCEL_CAP_ZUC;
154
155 if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_PKE_D15XX)
156 cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
157 if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_CY_D15XX)
158 cap &= ~QAT_ACCEL_CAP_COMPRESSION;
159
160 return cap;
161 }
162
163 static const char *
qat_d15xx_get_fw_uof_name(struct qat_softc * sc)164 qat_d15xx_get_fw_uof_name(struct qat_softc *sc)
165 {
166
167 return AE_FW_UOF_NAME_D15XX;
168 }
169
170 static void
qat_d15xx_enable_intr(struct qat_softc * sc)171 qat_d15xx_enable_intr(struct qat_softc *sc)
172 {
173
174 /* Enable bundle and misc interrupts */
175 qat_misc_write_4(sc, SMIAPF0_D15XX, SMIA0_MASK_D15XX);
176 qat_misc_write_4(sc, SMIAPF1_D15XX, SMIA1_MASK_D15XX);
177 }
178
179 /* Worker thread to service arbiter mappings */
180 static uint32_t thrd_to_arb_map[] = {
181 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
182 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
183 };
184
185 static void
qat_d15xx_get_arb_mapping(struct qat_softc * sc,const uint32_t ** arb_map_config)186 qat_d15xx_get_arb_mapping(struct qat_softc *sc, const uint32_t **arb_map_config)
187 {
188 int i;
189
190 for (i = 1; i < MAX_AE_D15XX; i++) {
191 if ((~sc->sc_ae_mask) & (1 << i))
192 thrd_to_arb_map[i] = 0;
193 }
194 *arb_map_config = thrd_to_arb_map;
195 }
196
197 static void
qat_d15xx_enable_error_interrupts(struct qat_softc * sc)198 qat_d15xx_enable_error_interrupts(struct qat_softc *sc)
199 {
200 qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_D15XX); /* ME0-ME3 */
201 qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_D15XX); /* ME4-ME7 */
202 qat_misc_write_4(sc, ERRMSK4, ERRMSK4_CERR_D15XX); /* ME8-ME9 */
203 qat_misc_write_4(sc, ERRMSK5, ERRMSK5_CERR_D15XX); /* SSM2-SSM4 */
204
205 /* Reset everything except VFtoPF1_16. */
206 qat_misc_read_write_and_4(sc, ERRMSK3, VF2PF1_16_D15XX);
207 /* Disable Secure RAM correctable error interrupt */
208 qat_misc_read_write_or_4(sc, ERRMSK3, ERRMSK3_CERR_D15XX);
209
210 /* RI CPP bus interface error detection and reporting. */
211 qat_misc_write_4(sc, RICPPINTCTL_D15XX, RICPP_EN_D15XX);
212
213 /* TI CPP bus interface error detection and reporting. */
214 qat_misc_write_4(sc, TICPPINTCTL_D15XX, TICPP_EN_D15XX);
215
216 /* Enable CFC Error interrupts and logging. */
217 qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_D15XX, CPP_CFC_UE_D15XX);
218
219 /* Enable SecureRAM to fix and log Correctable errors */
220 qat_misc_write_4(sc, SECRAMCERR_D15XX, SECRAM_CERR_D15XX);
221
222 /* Enable SecureRAM Uncorrectable error interrupts and logging */
223 qat_misc_write_4(sc, SECRAMUERR, SECRAM_UERR_D15XX);
224
225 /* Enable Push/Pull Misc Uncorrectable error interrupts and logging */
226 qat_misc_write_4(sc, CPPMEMTGTERR, TGT_UERR_D15XX);
227 }
228
229 static void
qat_d15xx_disable_error_interrupts(struct qat_softc * sc)230 qat_d15xx_disable_error_interrupts(struct qat_softc *sc)
231 {
232 /* ME0-ME3 */
233 qat_misc_write_4(sc, ERRMSK0, ERRMSK0_UERR_D15XX | ERRMSK0_CERR_D15XX);
234 /* ME4-ME7 */
235 qat_misc_write_4(sc, ERRMSK1, ERRMSK1_UERR_D15XX | ERRMSK1_CERR_D15XX);
236 /* Secure RAM, CPP Push Pull, RI, TI, SSM0-SSM1, CFC */
237 qat_misc_write_4(sc, ERRMSK3, ERRMSK3_UERR_D15XX | ERRMSK3_CERR_D15XX);
238 /* ME8-ME9 */
239 qat_misc_write_4(sc, ERRMSK4, ERRMSK4_UERR_D15XX | ERRMSK4_CERR_D15XX);
240 /* SSM2-SSM4 */
241 qat_misc_write_4(sc, ERRMSK5, ERRMSK5_UERR_D15XX | ERRMSK5_CERR_D15XX);
242 }
243
244 static void
qat_d15xx_enable_error_correction(struct qat_softc * sc)245 qat_d15xx_enable_error_correction(struct qat_softc *sc)
246 {
247 u_int i, mask;
248
249 /* Enable Accel Engine error detection & correction */
250 for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
251 if (!(mask & 1))
252 continue;
253 qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_D15XX(i),
254 ENABLE_AE_ECC_ERR_D15XX);
255 qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_D15XX(i),
256 ENABLE_AE_ECC_PARITY_CORR_D15XX);
257 }
258
259 /* Enable shared memory error detection & correction */
260 for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
261 if (!(mask & 1))
262 continue;
263
264 qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_D15XX);
265 qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_D15XX);
266 qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_D15XX);
267 }
268
269 qat_d15xx_enable_error_interrupts(sc);
270 }
271
272 const struct qat_hw qat_hw_d15xx = {
273 .qhw_sram_bar_id = BAR_SRAM_ID_D15XX,
274 .qhw_misc_bar_id = BAR_PMISC_ID_D15XX,
275 .qhw_etr_bar_id = BAR_ETR_ID_D15XX,
276 .qhw_cap_global_offset = CAP_GLOBAL_OFFSET_D15XX,
277 .qhw_ae_offset = AE_OFFSET_D15XX,
278 .qhw_ae_local_offset = AE_LOCAL_OFFSET_D15XX,
279 .qhw_etr_bundle_size = ETR_BUNDLE_SIZE_D15XX,
280 .qhw_num_banks = ETR_MAX_BANKS_D15XX,
281 .qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
282 .qhw_num_accel = MAX_ACCEL_D15XX,
283 .qhw_num_engines = MAX_AE_D15XX,
284 .qhw_tx_rx_gap = ETR_TX_RX_GAP_D15XX,
285 .qhw_tx_rings_mask = ETR_TX_RINGS_MASK_D15XX,
286 .qhw_clock_per_sec = CLOCK_PER_SEC_D15XX,
287 .qhw_fw_auth = true,
288 .qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
289 .qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
290 .qhw_ring_asym_tx = 0,
291 .qhw_ring_asym_rx = 8,
292 .qhw_ring_sym_tx = 2,
293 .qhw_ring_sym_rx = 10,
294 .qhw_mof_fwname = AE_FW_MOF_NAME_D15XX,
295 .qhw_mmp_fwname = AE_FW_MMP_NAME_D15XX,
296 .qhw_prod_type = AE_FW_PROD_TYPE_D15XX,
297 .qhw_get_accel_mask = qat_d15xx_get_accel_mask,
298 .qhw_get_ae_mask = qat_d15xx_get_ae_mask,
299 .qhw_get_sku = qat_d15xx_get_sku,
300 .qhw_get_accel_cap = qat_d15xx_get_accel_cap,
301 .qhw_get_fw_uof_name = qat_d15xx_get_fw_uof_name,
302 .qhw_enable_intr = qat_d15xx_enable_intr,
303 .qhw_init_admin_comms = qat_adm_mailbox_init,
304 .qhw_send_admin_init = qat_adm_mailbox_send_init,
305 .qhw_init_arb = qat_arb_init,
306 .qhw_get_arb_mapping = qat_d15xx_get_arb_mapping,
307 .qhw_enable_error_correction = qat_d15xx_enable_error_correction,
308 .qhw_disable_error_interrupts = qat_d15xx_disable_error_interrupts,
309 .qhw_set_ssm_wdtimer = qat_set_ssm_wdtimer,
310 .qhw_check_slice_hang = qat_check_slice_hang,
311 .qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
312 .qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
313 .qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
314 };
315