1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $FreeBSD: stable/12/sys/dev/pci/pci_dw.h 367206 2020-10-31 14:59:39Z mmel $
29 *
30 */
31
32 #ifndef _PCI_DW_H_
33 #define _PCI_DW_H_
34
35 #include "pci_dw_if.h"
36
37
38 /* DesignWare CIe configuration registers */
39 #define DW_PORT_LINK_CTRL 0x710
40 #define PORT_LINK_CAPABLE(n) (((n) & 0x3F) << 16)
41 #define PORT_LINK_CAPABLE_1 0x01
42 #define PORT_LINK_CAPABLE_2 0x03
43 #define PORT_LINK_CAPABLE_4 0x07
44 #define PORT_LINK_CAPABLE_8 0x0F
45 #define PORT_LINK_CAPABLE_16 0x1F
46 #define PORT_LINK_CAPABLE_32 0x3F
47
48
49 #define DW_GEN2_CTRL 0x80C
50 #define DIRECT_SPEED_CHANGE (1 << 17)
51 #define GEN2_CTRL_NUM_OF_LANES(n) (((n) & 0x3F) << 8)
52 #define GEN2_CTRL_NUM_OF_LANES_1 0x01
53 #define GEN2_CTRL_NUM_OF_LANES_2 0x03
54 #define GEN2_CTRL_NUM_OF_LANES_4 0x07
55 #define GEN2_CTRL_NUM_OF_LANES_8 0x0F
56 #define GEN2_CTRL_NUM_OF_LANES_16 0x1F
57 #define GEN2_CTRL_NUM_OF_LANES_32 0x3F
58
59 #define DW_MSI_ADDR_LO 0x820
60 #define DW_MSI_ADDR_HI 0x824
61 #define DW_MSI_INTR0_ENABLE 0x828
62 #define DW_MSI_INTR0_MASK 0x82C
63 #define DW_MSI_INTR0_STATUS 0x830
64
65
66 #define DW_MISC_CONTROL_1 0x8BC
67 #define DBI_RO_WR_EN (1 << 0)
68
69 #define DW_IATU_VIEWPORT 0x900
70 #define IATU_REGION_INBOUND (1U << 31)
71 #define IATU_REGION_INDEX(x) ((x) & 0x7)
72 #define DW_IATU_CTRL1 0x904
73 #define IATU_CTRL1_TYPE(x) ((x) & 0x1F)
74 #define IATU_CTRL1_TYPE_MEM 0x0
75 #define IATU_CTRL1_TYPE_IO 0x2
76 #define IATU_CTRL1_TYPE_CFG0 0x4
77 #define IATU_CTRL1_TYPE_CFG1 0x5
78 #define DW_IATU_CTRL2 0x908
79 #define IATU_CTRL2_REGION_EN (1U << 31)
80 #define DW_IATU_LWR_BASE_ADDR 0x90C
81 #define DW_IATU_UPPER_BASE_ADDR 0x910
82 #define DW_IATU_LIMIT_ADDR 0x914
83 #define DW_IATU_LWR_TARGET_ADDR 0x918
84 #define DW_IATU_UPPER_TARGET_ADDR 0x91C
85
86
87 struct pci_dw_softc {
88 struct ofw_pci_softc ofw_pci; /* Must be first */
89
90 /* Filled by attachement stub */
91 struct resource *dbi_res;
92
93 /* pci_dw variables */
94 device_t dev;
95 phandle_t node;
96 struct mtx mtx;
97 struct resource *cfg_res;
98
99 struct ofw_pci_range mem_range;
100 struct ofw_pci_range pref_mem_range;
101 struct ofw_pci_range io_range;
102
103 bool coherent;
104 bus_dma_tag_t dmat;
105
106 int num_lanes;
107 int num_viewport;
108 bus_addr_t cfg_pa; /* PA of config memoty */
109 bus_size_t cfg_size; /* size of config region */
110
111 u_int bus_start;
112 u_int bus_end;
113 u_int root_bus;
114 u_int sub_bus;
115 };
116
117 DECLARE_CLASS(pci_dw_driver);
118
119
120 static inline void
pci_dw_dbi_wr4(device_t dev,u_int reg,uint32_t val)121 pci_dw_dbi_wr4(device_t dev, u_int reg, uint32_t val)
122 {
123 PCI_DW_DBI_WRITE(dev, reg, val, 4);
124 }
125
126 static inline void
pci_dw_dbi_wr2(device_t dev,u_int reg,uint16_t val)127 pci_dw_dbi_wr2(device_t dev, u_int reg, uint16_t val)
128 {
129 PCI_DW_DBI_WRITE(dev, reg, val, 2);
130 }
131
132 static inline void
pci_dw_dbi_wr1(device_t dev,u_int reg,uint8_t val)133 pci_dw_dbi_wr1(device_t dev, u_int reg, uint8_t val)
134 {
135 PCI_DW_DBI_WRITE(dev, reg, val, 1);
136 }
137
138 static inline uint32_t
pci_dw_dbi_rd4(device_t dev,u_int reg)139 pci_dw_dbi_rd4(device_t dev, u_int reg)
140 {
141 return (PCI_DW_DBI_READ(dev, reg, 4));
142 }
143
144 static inline uint16_t
pci_dw_dbi_rd2(device_t dev,u_int reg)145 pci_dw_dbi_rd2(device_t dev, u_int reg)
146 {
147 return ((uint16_t)PCI_DW_DBI_READ(dev, reg, 2));
148 }
149
150 static inline uint8_t
pci_dw_dbi_rd1(device_t dev,u_int reg)151 pci_dw_dbi_rd1(device_t dev, u_int reg)
152 {
153 return ((uint8_t)PCI_DW_DBI_READ(dev, reg, 1));
154 }
155
156 int pci_dw_init(device_t);
157
158 #endif /* __PCI_HOST_GENERIC_H_ */
159