1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: stable/12/sys/dev/mvs/mvs_pci.c 338949 2018-09-26 17:12:30Z imp $");
31
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <vm/uma.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <sys/rman.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include "mvs.h"
49
50 /* local prototypes */
51 static int mvs_setup_interrupt(device_t dev);
52 static void mvs_intr(void *data);
53 static int mvs_suspend(device_t dev);
54 static int mvs_resume(device_t dev);
55 static int mvs_ctlr_setup(device_t dev);
56
57 static struct {
58 uint32_t id;
59 uint8_t rev;
60 const char *name;
61 int ports;
62 int quirks;
63 } mvs_ids[] = {
64 {0x504011ab, 0x00, "Marvell 88SX5040", 4, MVS_Q_GENI},
65 {0x504111ab, 0x00, "Marvell 88SX5041", 4, MVS_Q_GENI},
66 {0x508011ab, 0x00, "Marvell 88SX5080", 8, MVS_Q_GENI},
67 {0x508111ab, 0x00, "Marvell 88SX5081", 8, MVS_Q_GENI},
68 {0x604011ab, 0x00, "Marvell 88SX6040", 4, MVS_Q_GENII},
69 {0x604111ab, 0x00, "Marvell 88SX6041", 4, MVS_Q_GENII},
70 {0x604211ab, 0x00, "Marvell 88SX6042", 4, MVS_Q_GENIIE},
71 {0x608011ab, 0x00, "Marvell 88SX6080", 8, MVS_Q_GENII},
72 {0x608111ab, 0x00, "Marvell 88SX6081", 8, MVS_Q_GENII},
73 {0x704211ab, 0x00, "Marvell 88SX7042", 4, MVS_Q_GENIIE|MVS_Q_CT},
74 {0x02419005, 0x00, "Adaptec 1420SA", 4, MVS_Q_GENII},
75 {0x02439005, 0x00, "Adaptec 1430SA", 4, MVS_Q_GENIIE|MVS_Q_CT},
76 {0x00000000, 0x00, NULL, 0, 0}
77 };
78
79 static int
mvs_probe(device_t dev)80 mvs_probe(device_t dev)
81 {
82 char buf[64];
83 int i;
84 uint32_t devid = pci_get_devid(dev);
85 uint8_t revid = pci_get_revid(dev);
86
87 for (i = 0; mvs_ids[i].id != 0; i++) {
88 if (mvs_ids[i].id == devid &&
89 mvs_ids[i].rev <= revid) {
90 snprintf(buf, sizeof(buf), "%s SATA controller",
91 mvs_ids[i].name);
92 device_set_desc_copy(dev, buf);
93 return (BUS_PROBE_DEFAULT);
94 }
95 }
96 return (ENXIO);
97 }
98
99 static int
mvs_attach(device_t dev)100 mvs_attach(device_t dev)
101 {
102 struct mvs_controller *ctlr = device_get_softc(dev);
103 device_t child;
104 int error, unit, i;
105 uint32_t devid = pci_get_devid(dev);
106 uint8_t revid = pci_get_revid(dev);
107
108 ctlr->dev = dev;
109 i = 0;
110 while (mvs_ids[i].id != 0 &&
111 (mvs_ids[i].id != devid ||
112 mvs_ids[i].rev > revid))
113 i++;
114 ctlr->channels = mvs_ids[i].ports;
115 ctlr->quirks = mvs_ids[i].quirks;
116 ctlr->ccc = 0;
117 resource_int_value(device_get_name(dev),
118 device_get_unit(dev), "ccc", &ctlr->ccc);
119 ctlr->cccc = 8;
120 resource_int_value(device_get_name(dev),
121 device_get_unit(dev), "cccc", &ctlr->cccc);
122 if (ctlr->ccc == 0 || ctlr->cccc == 0) {
123 ctlr->ccc = 0;
124 ctlr->cccc = 0;
125 }
126 if (ctlr->ccc > 100000)
127 ctlr->ccc = 100000;
128 device_printf(dev,
129 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n",
130 ((ctlr->quirks & MVS_Q_GENI) ? "I" :
131 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")),
132 ctlr->channels,
133 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"),
134 ((ctlr->quirks & MVS_Q_GENI) ?
135 "not supported" : "supported"),
136 ((ctlr->quirks & MVS_Q_GENIIE) ?
137 " with FBS" : ""));
138 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF);
139 /* We should have a memory BAR(0). */
140 ctlr->r_rid = PCIR_BAR(0);
141 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
142 &ctlr->r_rid, RF_ACTIVE)))
143 return ENXIO;
144 /* Setup our own memory management for channels. */
145 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
146 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
147 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
148 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
149 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
150 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
151 return (error);
152 }
153 if ((error = rman_manage_region(&ctlr->sc_iomem,
154 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
155 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
156 rman_fini(&ctlr->sc_iomem);
157 return (error);
158 }
159 pci_enable_busmaster(dev);
160 mvs_ctlr_setup(dev);
161 /* Setup interrupts. */
162 if (mvs_setup_interrupt(dev)) {
163 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
164 rman_fini(&ctlr->sc_iomem);
165 return ENXIO;
166 }
167 /* Attach all channels on this controller */
168 for (unit = 0; unit < ctlr->channels; unit++) {
169 child = device_add_child(dev, "mvsch", -1);
170 if (child == NULL)
171 device_printf(dev, "failed to add channel device\n");
172 else
173 device_set_ivars(child, (void *)(intptr_t)unit);
174 }
175 bus_generic_attach(dev);
176 return 0;
177 }
178
179 static int
mvs_detach(device_t dev)180 mvs_detach(device_t dev)
181 {
182 struct mvs_controller *ctlr = device_get_softc(dev);
183
184 /* Detach & delete all children */
185 device_delete_children(dev);
186
187 /* Free interrupt. */
188 if (ctlr->irq.r_irq) {
189 bus_teardown_intr(dev, ctlr->irq.r_irq,
190 ctlr->irq.handle);
191 bus_release_resource(dev, SYS_RES_IRQ,
192 ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
193 }
194 pci_release_msi(dev);
195 /* Free memory. */
196 rman_fini(&ctlr->sc_iomem);
197 if (ctlr->r_mem)
198 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
199 mtx_destroy(&ctlr->mtx);
200 return (0);
201 }
202
203 static int
mvs_ctlr_setup(device_t dev)204 mvs_ctlr_setup(device_t dev)
205 {
206 struct mvs_controller *ctlr = device_get_softc(dev);
207 int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
208
209 /* Mask chip interrupts */
210 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
211 /* Mask PCI interrupts */
212 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
213 /* Clear PCI interrupts */
214 ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000);
215 if (ccc && bootverbose) {
216 device_printf(dev,
217 "CCC with %dus/%dcmd enabled\n",
218 ctlr->ccc, ctlr->cccc);
219 }
220 ccc *= 150;
221 /* Configure chip-global CCC */
222 if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) {
223 ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc);
224 ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc);
225 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
226 if (ccc)
227 ccim |= IC_ALL_PORTS_COAL_DONE;
228 ccc = 0;
229 cccc = 0;
230 }
231 for (i = 0; i < ctlr->channels / 4; i++) {
232 /* Configure per-HC CCC */
233 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc);
234 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc);
235 if (ccc)
236 ccim |= (IC_HC0_COAL_DONE << (i * IC_HC_SHIFT));
237 /* Clear HC interrupts */
238 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000);
239 }
240 /* Enable chip interrupts */
241 ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) |
242 IC_ERR_HC0 | IC_ERR_HC1;
243 ctlr->mim = ctlr->gmim | ctlr->pmim;
244 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
245 /* Enable PCI interrupts */
246 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff);
247 return (0);
248 }
249
250 static void
mvs_edma(device_t dev,device_t child,int mode)251 mvs_edma(device_t dev, device_t child, int mode)
252 {
253 struct mvs_controller *ctlr = device_get_softc(dev);
254 int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
255 int bit = IC_DONE_IRQ << (unit * 2 + unit / 4) ;
256
257 if (ctlr->ccc == 0)
258 return;
259 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */
260 mtx_lock(&ctlr->mtx);
261 if (mode == MVS_EDMA_OFF)
262 ctlr->pmim |= bit;
263 else
264 ctlr->pmim &= ~bit;
265 ctlr->mim = ctlr->gmim | ctlr->pmim;
266 if (!ctlr->msia)
267 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
268 mtx_unlock(&ctlr->mtx);
269 }
270
271 static int
mvs_suspend(device_t dev)272 mvs_suspend(device_t dev)
273 {
274 struct mvs_controller *ctlr = device_get_softc(dev);
275
276 bus_generic_suspend(dev);
277 /* Mask chip interrupts */
278 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
279 /* Mask PCI interrupts */
280 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
281 return 0;
282 }
283
284 static int
mvs_resume(device_t dev)285 mvs_resume(device_t dev)
286 {
287
288 mvs_ctlr_setup(dev);
289 return (bus_generic_resume(dev));
290 }
291
292 static int
mvs_setup_interrupt(device_t dev)293 mvs_setup_interrupt(device_t dev)
294 {
295 struct mvs_controller *ctlr = device_get_softc(dev);
296 int msi = 0;
297
298 /* Process hints. */
299 resource_int_value(device_get_name(dev),
300 device_get_unit(dev), "msi", &msi);
301 if (msi < 0)
302 msi = 0;
303 else if (msi > 0)
304 msi = min(1, pci_msi_count(dev));
305 /* Allocate MSI if needed/present. */
306 if (msi && pci_alloc_msi(dev, &msi) != 0)
307 msi = 0;
308 ctlr->msi = msi;
309 /* Allocate all IRQs. */
310 ctlr->irq.r_irq_rid = msi ? 1 : 0;
311 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
312 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
313 device_printf(dev, "unable to map interrupt\n");
314 return (ENXIO);
315 }
316 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL,
317 mvs_intr, ctlr, &ctlr->irq.handle))) {
318 device_printf(dev, "unable to setup interrupt\n");
319 bus_release_resource(dev, SYS_RES_IRQ,
320 ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
321 ctlr->irq.r_irq = NULL;
322 return (ENXIO);
323 }
324 return (0);
325 }
326
327 /*
328 * Common case interrupt handler.
329 */
330 static void
mvs_intr(void * data)331 mvs_intr(void *data)
332 {
333 struct mvs_controller *ctlr = data;
334 struct mvs_intr_arg arg;
335 void (*function)(void *);
336 int p;
337 u_int32_t ic, aic;
338
339 ic = ATA_INL(ctlr->r_mem, CHIP_MIC);
340 if (ctlr->msi) {
341 /* We have to mask MSI during processing. */
342 mtx_lock(&ctlr->mtx);
343 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0);
344 ctlr->msia = 1; /* Deny MIM update during processing. */
345 mtx_unlock(&ctlr->mtx);
346 } else if (ic == 0)
347 return;
348 /* Acknowledge all-ports CCC interrupt. */
349 if (ic & IC_ALL_PORTS_COAL_DONE)
350 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
351 for (p = 0; p < ctlr->channels; p++) {
352 if ((p & 3) == 0) {
353 if (p != 0)
354 ic >>= 1;
355 if ((ic & IC_HC0) == 0) {
356 p += 3;
357 ic >>= 8;
358 continue;
359 }
360 /* Acknowledge interrupts of this HC. */
361 aic = 0;
362 if (ic & (IC_DONE_IRQ << 0))
363 aic |= HC_IC_DONE(0) | HC_IC_DEV(0);
364 if (ic & (IC_DONE_IRQ << 2))
365 aic |= HC_IC_DONE(1) | HC_IC_DEV(1);
366 if (ic & (IC_DONE_IRQ << 4))
367 aic |= HC_IC_DONE(2) | HC_IC_DEV(2);
368 if (ic & (IC_DONE_IRQ << 6))
369 aic |= HC_IC_DONE(3) | HC_IC_DEV(3);
370 if (ic & IC_HC0_COAL_DONE)
371 aic |= HC_IC_COAL;
372 ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic);
373 }
374 /* Call per-port interrupt handler. */
375 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ);
376 if ((arg.cause != 0) &&
377 (function = ctlr->interrupt[p].function)) {
378 arg.arg = ctlr->interrupt[p].argument;
379 function(&arg);
380 }
381 ic >>= 2;
382 }
383 if (ctlr->msi) {
384 /* Unmasking MSI triggers next interrupt, if needed. */
385 mtx_lock(&ctlr->mtx);
386 ctlr->msia = 0; /* Allow MIM update. */
387 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
388 mtx_unlock(&ctlr->mtx);
389 }
390 }
391
392 static struct resource *
mvs_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)393 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid,
394 rman_res_t start, rman_res_t end, rman_res_t count,
395 u_int flags)
396 {
397 struct mvs_controller *ctlr = device_get_softc(dev);
398 int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
399 struct resource *res = NULL;
400 int offset = HC_BASE(unit >> 2) + PORT_BASE(unit & 0x03);
401 rman_res_t st;
402
403 switch (type) {
404 case SYS_RES_MEMORY:
405 st = rman_get_start(ctlr->r_mem);
406 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
407 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child);
408 if (res) {
409 bus_space_handle_t bsh;
410 bus_space_tag_t bst;
411 bsh = rman_get_bushandle(ctlr->r_mem);
412 bst = rman_get_bustag(ctlr->r_mem);
413 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh);
414 rman_set_bushandle(res, bsh);
415 rman_set_bustag(res, bst);
416 }
417 break;
418 case SYS_RES_IRQ:
419 if (*rid == ATA_IRQ_RID)
420 res = ctlr->irq.r_irq;
421 break;
422 }
423 return (res);
424 }
425
426 static int
mvs_release_resource(device_t dev,device_t child,int type,int rid,struct resource * r)427 mvs_release_resource(device_t dev, device_t child, int type, int rid,
428 struct resource *r)
429 {
430
431 switch (type) {
432 case SYS_RES_MEMORY:
433 rman_release_resource(r);
434 return (0);
435 case SYS_RES_IRQ:
436 if (rid != ATA_IRQ_RID)
437 return ENOENT;
438 return (0);
439 }
440 return (EINVAL);
441 }
442
443 static int
mvs_setup_intr(device_t dev,device_t child,struct resource * irq,int flags,driver_filter_t * filter,driver_intr_t * function,void * argument,void ** cookiep)444 mvs_setup_intr(device_t dev, device_t child, struct resource *irq,
445 int flags, driver_filter_t *filter, driver_intr_t *function,
446 void *argument, void **cookiep)
447 {
448 struct mvs_controller *ctlr = device_get_softc(dev);
449 int unit = (intptr_t)device_get_ivars(child);
450
451 if (filter != NULL) {
452 printf("mvs.c: we cannot use a filter here\n");
453 return (EINVAL);
454 }
455 ctlr->interrupt[unit].function = function;
456 ctlr->interrupt[unit].argument = argument;
457 return (0);
458 }
459
460 static int
mvs_teardown_intr(device_t dev,device_t child,struct resource * irq,void * cookie)461 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq,
462 void *cookie)
463 {
464 struct mvs_controller *ctlr = device_get_softc(dev);
465 int unit = (intptr_t)device_get_ivars(child);
466
467 ctlr->interrupt[unit].function = NULL;
468 ctlr->interrupt[unit].argument = NULL;
469 return (0);
470 }
471
472 static int
mvs_print_child(device_t dev,device_t child)473 mvs_print_child(device_t dev, device_t child)
474 {
475 int retval;
476
477 retval = bus_print_child_header(dev, child);
478 retval += printf(" at channel %d",
479 (int)(intptr_t)device_get_ivars(child));
480 retval += bus_print_child_footer(dev, child);
481
482 return (retval);
483 }
484
485 static int
mvs_child_location_str(device_t dev,device_t child,char * buf,size_t buflen)486 mvs_child_location_str(device_t dev, device_t child, char *buf,
487 size_t buflen)
488 {
489
490 snprintf(buf, buflen, "channel=%d",
491 (int)(intptr_t)device_get_ivars(child));
492 return (0);
493 }
494
495 static bus_dma_tag_t
mvs_get_dma_tag(device_t bus,device_t child)496 mvs_get_dma_tag(device_t bus, device_t child)
497 {
498
499 return (bus_get_dma_tag(bus));
500 }
501
502 static device_method_t mvs_methods[] = {
503 DEVMETHOD(device_probe, mvs_probe),
504 DEVMETHOD(device_attach, mvs_attach),
505 DEVMETHOD(device_detach, mvs_detach),
506 DEVMETHOD(device_suspend, mvs_suspend),
507 DEVMETHOD(device_resume, mvs_resume),
508 DEVMETHOD(bus_print_child, mvs_print_child),
509 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource),
510 DEVMETHOD(bus_release_resource, mvs_release_resource),
511 DEVMETHOD(bus_setup_intr, mvs_setup_intr),
512 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr),
513 DEVMETHOD(bus_child_location_str, mvs_child_location_str),
514 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag),
515 DEVMETHOD(mvs_edma, mvs_edma),
516 { 0, 0 }
517 };
518 static driver_t mvs_driver = {
519 "mvs",
520 mvs_methods,
521 sizeof(struct mvs_controller)
522 };
523 DRIVER_MODULE(mvs, pci, mvs_driver, mvs_devclass, 0, 0);
524 MODULE_PNP_INFO("W32:vendor/device", pci, mvs, mvs_ids,
525 nitems(mvs_ids) - 1);
526 MODULE_VERSION(mvs, 1);
527 MODULE_DEPEND(mvs, cam, 1, 1, 1);
528
529