1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: stable/12/sys/dev/hwpmc/hwpmc_octeon.c 326255 2017-11-27 14:52:40Z pfg $");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/pmc.h>
36 #include <sys/pmckern.h>
37
38 #include <machine/cpu.h>
39 #include <machine/cpufunc.h>
40 #include <machine/pmc_mdep.h>
41
42 #include <contrib/octeon-sdk/cvmx.h>
43 #include <contrib/octeon-sdk/cvmx-core.h>
44
45 #define OCTEON_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
46 PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
47 PMC_CAP_THRESHOLD | PMC_CAP_READ | \
48 PMC_CAP_WRITE | PMC_CAP_INVERT | \
49 PMC_CAP_QUALIFIER)
50
51 const struct mips_event_code_map mips_event_codes[] =
52 {
53 { PMC_EV_OCTEON_CLK, MIPS_CTR_ALL, CVMX_CORE_PERF_CLK },
54 { PMC_EV_OCTEON_ISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_ISSUE },
55 { PMC_EV_OCTEON_RET, MIPS_CTR_ALL, CVMX_CORE_PERF_RET },
56 { PMC_EV_OCTEON_NISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_NISSUE },
57 { PMC_EV_OCTEON_SISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_SISSUE },
58 { PMC_EV_OCTEON_DISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_DISSUE },
59 { PMC_EV_OCTEON_IFI, MIPS_CTR_ALL, CVMX_CORE_PERF_IFI },
60 { PMC_EV_OCTEON_BR, MIPS_CTR_ALL, CVMX_CORE_PERF_BR },
61 { PMC_EV_OCTEON_BRMIS, MIPS_CTR_ALL, CVMX_CORE_PERF_BRMIS },
62 { PMC_EV_OCTEON_J, MIPS_CTR_ALL, CVMX_CORE_PERF_J },
63 { PMC_EV_OCTEON_JMIS, MIPS_CTR_ALL, CVMX_CORE_PERF_JMIS },
64 { PMC_EV_OCTEON_REPLAY, MIPS_CTR_ALL, CVMX_CORE_PERF_REPLAY },
65 { PMC_EV_OCTEON_IUNA, MIPS_CTR_ALL, CVMX_CORE_PERF_IUNA },
66 { PMC_EV_OCTEON_TRAP, MIPS_CTR_ALL, CVMX_CORE_PERF_TRAP },
67 { PMC_EV_OCTEON_UULOAD, MIPS_CTR_ALL, CVMX_CORE_PERF_UULOAD },
68 { PMC_EV_OCTEON_UUSTORE, MIPS_CTR_ALL, CVMX_CORE_PERF_UUSTORE },
69 { PMC_EV_OCTEON_ULOAD, MIPS_CTR_ALL, CVMX_CORE_PERF_ULOAD },
70 { PMC_EV_OCTEON_USTORE, MIPS_CTR_ALL, CVMX_CORE_PERF_USTORE },
71 { PMC_EV_OCTEON_EC, MIPS_CTR_ALL, CVMX_CORE_PERF_EC },
72 { PMC_EV_OCTEON_MC, MIPS_CTR_ALL, CVMX_CORE_PERF_MC },
73 { PMC_EV_OCTEON_CC, MIPS_CTR_ALL, CVMX_CORE_PERF_CC },
74 { PMC_EV_OCTEON_CSRC, MIPS_CTR_ALL, CVMX_CORE_PERF_CSRC },
75 { PMC_EV_OCTEON_CFETCH, MIPS_CTR_ALL, CVMX_CORE_PERF_CFETCH },
76 { PMC_EV_OCTEON_CPREF, MIPS_CTR_ALL, CVMX_CORE_PERF_CPREF },
77 { PMC_EV_OCTEON_ICA, MIPS_CTR_ALL, CVMX_CORE_PERF_ICA },
78 { PMC_EV_OCTEON_II, MIPS_CTR_ALL, CVMX_CORE_PERF_II },
79 { PMC_EV_OCTEON_IP, MIPS_CTR_ALL, CVMX_CORE_PERF_IP },
80 { PMC_EV_OCTEON_CIMISS, MIPS_CTR_ALL, CVMX_CORE_PERF_CIMISS },
81 { PMC_EV_OCTEON_WBUF, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUF },
82 { PMC_EV_OCTEON_WDAT, MIPS_CTR_ALL, CVMX_CORE_PERF_WDAT },
83 { PMC_EV_OCTEON_WBUFLD, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFLD },
84 { PMC_EV_OCTEON_WBUFFL, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFFL },
85 { PMC_EV_OCTEON_WBUFTR, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFTR },
86 { PMC_EV_OCTEON_BADD, MIPS_CTR_ALL, CVMX_CORE_PERF_BADD },
87 { PMC_EV_OCTEON_BADDL2, MIPS_CTR_ALL, CVMX_CORE_PERF_BADDL2 },
88 { PMC_EV_OCTEON_BFILL, MIPS_CTR_ALL, CVMX_CORE_PERF_BFILL },
89 { PMC_EV_OCTEON_DDIDS, MIPS_CTR_ALL, CVMX_CORE_PERF_DDIDS },
90 { PMC_EV_OCTEON_IDIDS, MIPS_CTR_ALL, CVMX_CORE_PERF_IDIDS },
91 { PMC_EV_OCTEON_DIDNA, MIPS_CTR_ALL, CVMX_CORE_PERF_DIDNA },
92 { PMC_EV_OCTEON_LDS, MIPS_CTR_ALL, CVMX_CORE_PERF_LDS },
93 { PMC_EV_OCTEON_LMLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_LMLDS },
94 { PMC_EV_OCTEON_IOLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_IOLDS },
95 { PMC_EV_OCTEON_DMLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_DMLDS },
96 { PMC_EV_OCTEON_STS, MIPS_CTR_ALL, CVMX_CORE_PERF_STS },
97 { PMC_EV_OCTEON_LMSTS, MIPS_CTR_ALL, CVMX_CORE_PERF_LMSTS },
98 { PMC_EV_OCTEON_IOSTS, MIPS_CTR_ALL, CVMX_CORE_PERF_IOSTS },
99 { PMC_EV_OCTEON_IOBDMA, MIPS_CTR_ALL, CVMX_CORE_PERF_IOBDMA },
100 { PMC_EV_OCTEON_DTLB, MIPS_CTR_ALL, CVMX_CORE_PERF_DTLB },
101 { PMC_EV_OCTEON_DTLBAD, MIPS_CTR_ALL, CVMX_CORE_PERF_DTLBAD },
102 { PMC_EV_OCTEON_ITLB, MIPS_CTR_ALL, CVMX_CORE_PERF_ITLB },
103 { PMC_EV_OCTEON_SYNC, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNC },
104 { PMC_EV_OCTEON_SYNCIOB, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNCIOB },
105 { PMC_EV_OCTEON_SYNCW, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNCW },
106 };
107
108 const int mips_event_codes_size = nitems(mips_event_codes);
109
110 struct mips_pmc_spec mips_pmc_spec = {
111 .ps_cpuclass = PMC_CLASS_OCTEON,
112 .ps_cputype = PMC_CPU_MIPS_OCTEON,
113 .ps_capabilities = OCTEON_PMC_CAPS,
114 .ps_counter_width = 64
115 };
116
117 /*
118 * Performance Count Register N
119 */
120 uint64_t
mips_pmcn_read(unsigned int pmc)121 mips_pmcn_read(unsigned int pmc)
122 {
123 uint64_t reg = 0;
124
125 KASSERT(pmc < mips_npmcs, ("[mips,%d] illegal PMC number %d",
126 __LINE__, pmc));
127
128 /* The counter value is the next value after the control register. */
129 switch (pmc) {
130 case 0:
131 CVMX_MF_COP0(reg, COP0_PERFVALUE0);
132 break;
133 case 1:
134 CVMX_MF_COP0(reg, COP0_PERFVALUE1);
135 break;
136 default:
137 return 0;
138 }
139 return (reg);
140 }
141
142 uint64_t
mips_pmcn_write(unsigned int pmc,uint64_t reg)143 mips_pmcn_write(unsigned int pmc, uint64_t reg)
144 {
145
146 KASSERT(pmc < mips_npmcs, ("[mips,%d] illegal PMC number %d",
147 __LINE__, pmc));
148
149 switch (pmc) {
150 case 0:
151 CVMX_MT_COP0(reg, COP0_PERFVALUE0);
152 break;
153 case 1:
154 CVMX_MT_COP0(reg, COP0_PERFVALUE1);
155 break;
156 default:
157 return 0;
158 }
159 return (reg);
160 }
161
162 uint32_t
mips_get_perfctl(int cpu,int ri,uint32_t event,uint32_t caps)163 mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps)
164 {
165 cvmx_core_perf_control_t control;
166
167 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
168 ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
169 KASSERT(ri >= 0 && ri < mips_npmcs,
170 ("[mips,%d] illegal row index %d", __LINE__, ri));
171
172 control.s.event = event;
173
174 if (caps & PMC_CAP_SYSTEM) {
175 control.s.k = 1;
176 control.s.s = 1;
177 control.s.ex = 1;
178 }
179
180 if (caps & PMC_CAP_USER)
181 control.s.u = 1;
182
183 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) {
184 control.s.k = 1;
185 control.s.s = 1;
186 control.s.u = 1;
187 control.s.ex = 1;
188 }
189
190 if (caps & PMC_CAP_INTERRUPT)
191 control.s.ie = 1;
192
193 PMCDBG2(MDP,ALL,2,"mips-allocate ri=%d -> config=0x%x", ri,
194 control.u32);
195
196 return (control.u32);
197 }
198