1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2008 Joseph Koshy
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 /*
30  * Common code for handling Intel CPUs.
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: stable/12/sys/dev/hwpmc/hwpmc_intel.c 371448 2021-12-26 00:51:16Z mav $");
35 
36 #include <sys/param.h>
37 #include <sys/pmc.h>
38 #include <sys/pmckern.h>
39 #include <sys/systm.h>
40 
41 #include <machine/cpu.h>
42 #include <machine/cputypes.h>
43 #include <machine/md_var.h>
44 #include <machine/specialreg.h>
45 
46 static int
intel_switch_in(struct pmc_cpu * pc,struct pmc_process * pp)47 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
48 {
49 	(void) pc;
50 
51 	PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
52 	    pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
53 
54 	/* allow the RDPMC instruction if needed */
55 	if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
56 		load_cr4(rcr4() | CR4_PCE);
57 
58 	PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
59 
60 	return 0;
61 }
62 
63 static int
intel_switch_out(struct pmc_cpu * pc,struct pmc_process * pp)64 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
65 {
66 	(void) pc;
67 	(void) pp;		/* can be NULL */
68 
69 	PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
70 	    (uintmax_t) rcr4());
71 
72 	/* always turn off the RDPMC instruction */
73 	load_cr4(rcr4() & ~CR4_PCE);
74 
75 	return 0;
76 }
77 
78 struct pmc_mdep *
pmc_intel_initialize(void)79 pmc_intel_initialize(void)
80 {
81 	struct pmc_mdep *pmc_mdep;
82 	enum pmc_cputype cputype;
83 	int error, family, model, nclasses, ncpus, stepping, verov;
84 
85 	KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
86 	    ("[intel,%d] Initializing non-intel processor", __LINE__));
87 
88 	PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
89 
90 	cputype = -1;
91 	nclasses = 2;
92 	error = 0;
93 	verov = 0;
94 	family = CPUID_TO_FAMILY(cpu_id);
95 	model = CPUID_TO_MODEL(cpu_id);
96 	stepping = CPUID_TO_STEPPING(cpu_id);
97 
98 	snprintf(pmc_cpuid, sizeof(pmc_cpuid), "GenuineIntel-%d-%02X-%X",
99 	    family, model, stepping);
100 
101 	switch (cpu_id & 0xF00) {
102 	case 0x600:		/* Pentium Pro, Celeron, Pentium II & III */
103 		switch (model) {
104 		case 0xE:
105 			cputype = PMC_CPU_INTEL_CORE;
106 			break;
107 		case 0xF:
108 			/* Per Intel document 315338-020. */
109 			if (stepping == 0x7) {
110 				cputype = PMC_CPU_INTEL_CORE;
111 				verov = 1;
112 			} else {
113 				cputype = PMC_CPU_INTEL_CORE2;
114 				nclasses = 3;
115 			}
116 			break;
117 		case 0x17:
118 			cputype = PMC_CPU_INTEL_CORE2EXTREME;
119 			nclasses = 3;
120 			break;
121 		case 0x1C:	/* Per Intel document 320047-002. */
122 			cputype = PMC_CPU_INTEL_ATOM;
123 			nclasses = 3;
124 			break;
125 		case 0x1A:
126 		case 0x1E:	/*
127 				 * Per Intel document 253669-032 9/2009,
128 				 * pages A-2 and A-57
129 				 */
130 		case 0x1F:	/*
131 				 * Per Intel document 253669-032 9/2009,
132 				 * pages A-2 and A-57
133 				 */
134 			cputype = PMC_CPU_INTEL_COREI7;
135 			nclasses = 5;
136 			break;
137 		case 0x2E:
138 			cputype = PMC_CPU_INTEL_NEHALEM_EX;
139 			nclasses = 3;
140 			break;
141 		case 0x25:	/* Per Intel document 253669-033US 12/2009. */
142 		case 0x2C:	/* Per Intel document 253669-033US 12/2009. */
143 			cputype = PMC_CPU_INTEL_WESTMERE;
144 			nclasses = 5;
145 			break;
146 		case 0x2F:	/* Westmere-EX, seen in wild */
147 			cputype = PMC_CPU_INTEL_WESTMERE_EX;
148 			nclasses = 3;
149 			break;
150 		case 0x2A:	/* Per Intel document 253669-039US 05/2011. */
151 			cputype = PMC_CPU_INTEL_SANDYBRIDGE;
152 			nclasses = 3;
153 			break;
154 		case 0x2D:	/* Per Intel document 253669-044US 08/2012. */
155 			cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
156 			nclasses = 3;
157 			break;
158 		case 0x3A:	/* Per Intel document 253669-043US 05/2012. */
159 			cputype = PMC_CPU_INTEL_IVYBRIDGE;
160 			nclasses = 3;
161 			break;
162 		case 0x3E:	/* Per Intel document 325462-045US 01/2013. */
163 			cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
164 			nclasses = 3;
165 			break;
166 			/* Skylake */
167 		case 0x4e:
168 		case 0x5e:
169 			/* Kabylake */
170 		case 0x8E:	/* Per Intel document 325462-063US July 2017. */
171 		case 0x9E:	/* Per Intel document 325462-063US July 2017. */
172 			/* Cometlake */
173 		case 0xA5:
174 		case 0xA6:
175 			cputype = PMC_CPU_INTEL_SKYLAKE;
176 			nclasses = 3;
177 			break;
178 		case 0x55:	/* SDM rev 63 */
179 			cputype = PMC_CPU_INTEL_SKYLAKE_XEON;
180 			nclasses = 3;
181 			break;
182 			/* Icelake */
183 		case 0x7D:
184 		case 0x7E:
185 			/* Tigerlake */
186 		case 0x8C:
187 		case 0x8D:
188 			/* Rocketlake */
189 		case 0xA7:
190 			cputype = PMC_CPU_INTEL_ICELAKE;
191 			nclasses = 3;
192 			break;
193 		case 0x6A:
194 		case 0x6C:
195 			cputype = PMC_CPU_INTEL_ICELAKE_XEON;
196 			nclasses = 3;
197 			break;
198 		case 0x3D:
199 		case 0x47:
200 			cputype = PMC_CPU_INTEL_BROADWELL;
201 			nclasses = 3;
202 			break;
203 		case 0x4f:
204 		case 0x56:
205 			cputype = PMC_CPU_INTEL_BROADWELL_XEON;
206 			nclasses = 3;
207 			break;
208 		case 0x3F:	/* Per Intel document 325462-045US 09/2014. */
209 		case 0x46:	/* Per Intel document 325462-045US 09/2014. */
210 			        /* Should 46 be XEON. probably its own? */
211 			cputype = PMC_CPU_INTEL_HASWELL_XEON;
212 			nclasses = 3;
213 			break;
214 		case 0x3C:	/* Per Intel document 325462-045US 01/2013. */
215 		case 0x45:	/* Per Intel document 325462-045US 09/2014. */
216 			cputype = PMC_CPU_INTEL_HASWELL;
217 			nclasses = 3;
218 			break;
219 		case 0x37:
220 		case 0x4A:
221 		case 0x4D:      /* Per Intel document 330061-001 01/2014. */
222 		case 0x5A:
223 		case 0x5D:
224 			cputype = PMC_CPU_INTEL_ATOM_SILVERMONT;
225 			nclasses = 3;
226 			break;
227 		case 0x5C:	/* Per Intel document 325462-071US 10/2019. */
228 		case 0x5F:
229 			cputype = PMC_CPU_INTEL_ATOM_GOLDMONT;
230 			nclasses = 3;
231 			break;
232 		}
233 		break;
234 	}
235 
236 
237 	if ((int) cputype == -1) {
238 		printf("pmc: Unknown Intel CPU.\n");
239 		return (NULL);
240 	}
241 
242 	/* Allocate base class and initialize machine dependent struct */
243 	pmc_mdep = pmc_mdep_alloc(nclasses);
244 
245 	pmc_mdep->pmd_cputype	 = cputype;
246 	pmc_mdep->pmd_switch_in	 = intel_switch_in;
247 	pmc_mdep->pmd_switch_out = intel_switch_out;
248 
249 	ncpus = pmc_cpu_max();
250 	error = pmc_tsc_initialize(pmc_mdep, ncpus);
251 	if (error)
252 		goto error;
253 	switch (cputype) {
254 		/*
255 		 * Intel Core, Core 2 and Atom processors.
256 		 */
257 	case PMC_CPU_INTEL_ATOM:
258 	case PMC_CPU_INTEL_ATOM_SILVERMONT:
259 	case PMC_CPU_INTEL_ATOM_GOLDMONT:
260 	case PMC_CPU_INTEL_BROADWELL:
261 	case PMC_CPU_INTEL_BROADWELL_XEON:
262 	case PMC_CPU_INTEL_SKYLAKE_XEON:
263 	case PMC_CPU_INTEL_SKYLAKE:
264 	case PMC_CPU_INTEL_ICELAKE:
265 	case PMC_CPU_INTEL_ICELAKE_XEON:
266 	case PMC_CPU_INTEL_CORE:
267 	case PMC_CPU_INTEL_CORE2:
268 	case PMC_CPU_INTEL_CORE2EXTREME:
269 	case PMC_CPU_INTEL_COREI7:
270 	case PMC_CPU_INTEL_NEHALEM_EX:
271 	case PMC_CPU_INTEL_IVYBRIDGE:
272 	case PMC_CPU_INTEL_SANDYBRIDGE:
273 	case PMC_CPU_INTEL_WESTMERE:
274 	case PMC_CPU_INTEL_WESTMERE_EX:
275 	case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
276 	case PMC_CPU_INTEL_IVYBRIDGE_XEON:
277 	case PMC_CPU_INTEL_HASWELL:
278 	case PMC_CPU_INTEL_HASWELL_XEON:
279 		error = pmc_core_initialize(pmc_mdep, ncpus, verov);
280 		break;
281 
282 	default:
283 		KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
284 	}
285 
286 	if (error) {
287 		pmc_tsc_finalize(pmc_mdep);
288 		goto error;
289 	}
290 
291 	/*
292 	 * Init the uncore class.
293 	 */
294 	switch (cputype) {
295 		/*
296 		 * Intel Corei7 and Westmere processors.
297 		 */
298 	case PMC_CPU_INTEL_COREI7:
299 	case PMC_CPU_INTEL_WESTMERE:
300 #ifdef notyet
301 	/*
302 	 * TODO: re-enable uncore class on these processors.
303 	 *
304 	 * The uncore unit was reworked beginning with Sandy Bridge, including
305 	 * the MSRs required to program it. In particular, we need to:
306 	 *  - Parse the MSR_UNC_CBO_CONFIG MSR for number of C-box units in the
307 	 *    system
308 	 *  - Support reading and writing to ARB and C-box units, depending on
309 	 *    the requested event
310 	 *  - Create some kind of mapping between C-box <--> CPU
311 	 *
312 	 * Also TODO: support other later changes to these interfaces, to
313 	 * enable the uncore class on generations newer than Broadwell.
314 	 * Skylake+ appears to use newer addresses for the uncore MSRs.
315 	 */
316 	case PMC_CPU_INTEL_HASWELL:
317 	case PMC_CPU_INTEL_BROADWELL:
318 	case PMC_CPU_INTEL_SANDYBRIDGE:
319 #endif
320 		error = pmc_uncore_initialize(pmc_mdep, ncpus);
321 		break;
322 	default:
323 		break;
324 	}
325   error:
326 	if (error) {
327 		pmc_mdep_free(pmc_mdep);
328 		pmc_mdep = NULL;
329 	}
330 
331 	return (pmc_mdep);
332 }
333 
334 void
pmc_intel_finalize(struct pmc_mdep * md)335 pmc_intel_finalize(struct pmc_mdep *md)
336 {
337 	pmc_tsc_finalize(md);
338 
339 	switch (md->pmd_cputype) {
340 	case PMC_CPU_INTEL_ATOM:
341 	case PMC_CPU_INTEL_ATOM_SILVERMONT:
342 	case PMC_CPU_INTEL_ATOM_GOLDMONT:
343 	case PMC_CPU_INTEL_BROADWELL:
344 	case PMC_CPU_INTEL_BROADWELL_XEON:
345 	case PMC_CPU_INTEL_SKYLAKE_XEON:
346 	case PMC_CPU_INTEL_SKYLAKE:
347 	case PMC_CPU_INTEL_ICELAKE:
348 	case PMC_CPU_INTEL_ICELAKE_XEON:
349 	case PMC_CPU_INTEL_CORE:
350 	case PMC_CPU_INTEL_CORE2:
351 	case PMC_CPU_INTEL_CORE2EXTREME:
352 	case PMC_CPU_INTEL_COREI7:
353 	case PMC_CPU_INTEL_NEHALEM_EX:
354 	case PMC_CPU_INTEL_HASWELL:
355 	case PMC_CPU_INTEL_HASWELL_XEON:
356 	case PMC_CPU_INTEL_IVYBRIDGE:
357 	case PMC_CPU_INTEL_SANDYBRIDGE:
358 	case PMC_CPU_INTEL_WESTMERE:
359 	case PMC_CPU_INTEL_WESTMERE_EX:
360 	case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
361 	case PMC_CPU_INTEL_IVYBRIDGE_XEON:
362 		pmc_core_finalize(md);
363 		break;
364 	default:
365 		KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
366 	}
367 
368 	/*
369 	 * Uncore.
370 	 */
371 	switch (md->pmd_cputype) {
372 	case PMC_CPU_INTEL_COREI7:
373 	case PMC_CPU_INTEL_WESTMERE:
374 #ifdef notyet
375 	case PMC_CPU_INTEL_HASWELL:
376 	case PMC_CPU_INTEL_BROADWELL:
377 	case PMC_CPU_INTEL_SANDYBRIDGE:
378 #endif
379 		pmc_uncore_finalize(md);
380 		break;
381 	default:
382 		break;
383 	}
384 }
385