1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 1997 by Simon Shapiro
5 * All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD: stable/12/sys/dev/dpt/dpt_scsi.c 326255 2017-11-27 14:52:40Z pfg $");
34
35 /*
36 * dpt_scsi.c: SCSI dependent code for the DPT driver
37 *
38 * credits: Assisted by Mike Neuffer in the early low level DPT code
39 * Thanx to Mark Salyzyn of DPT for his assistance.
40 * Special thanx to Justin Gibbs for invaluable help in
41 * making this driver look and work like a FreeBSD component.
42 * Last but not least, many thanx to UCB and the FreeBSD
43 * team for creating and maintaining such a wonderful O/S.
44 *
45 * TODO: * Add ISA probe code.
46 * * Add driver-level RAID-0. This will allow interoperability with
47 * NiceTry, M$-Doze, Win-Dog, Slowlaris, etc., in recognizing RAID
48 * arrays that span controllers (Wow!).
49 */
50
51 #define _DPT_C_
52
53 #include "opt_dpt.h"
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/conf.h>
58 #include <sys/eventhandler.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61
62 #include <sys/bus.h>
63
64 #include <machine/bus.h>
65
66 #include <machine/resource.h>
67 #include <sys/rman.h>
68
69
70 #include <cam/cam.h>
71 #include <cam/cam_ccb.h>
72 #include <cam/cam_sim.h>
73 #include <cam/cam_xpt_sim.h>
74 #include <cam/cam_debug.h>
75 #include <cam/scsi/scsi_all.h>
76 #include <cam/scsi/scsi_message.h>
77
78 #include <vm/vm.h>
79 #include <vm/pmap.h>
80
81 #include <dev/dpt/dpt.h>
82
83 /* dpt_isa.c, and dpt_pci.c need this in a central place */
84 devclass_t dpt_devclass;
85
86 #define microtime_now dpt_time_now()
87
88 #define dpt_inl(dpt, port) \
89 bus_read_4((dpt)->io_res, (dpt)->io_offset + port)
90 #define dpt_inb(dpt, port) \
91 bus_read_1((dpt)->io_res, (dpt)->io_offset + port)
92 #define dpt_outl(dpt, port, value) \
93 bus_write_4((dpt)->io_res, (dpt)->io_offset + port, value)
94 #define dpt_outb(dpt, port, value) \
95 bus_write_1((dpt)->io_res, (dpt)->io_offset + port, value)
96
97 /*
98 * These will have to be setup by parameters passed at boot/load time. For
99 * performance reasons, we make them constants for the time being.
100 */
101 #define dpt_min_segs DPT_MAX_SEGS
102 #define dpt_max_segs DPT_MAX_SEGS
103
104 /* Definitions for our use of the SIM private CCB area */
105 #define ccb_dccb_ptr spriv_ptr0
106 #define ccb_dpt_ptr spriv_ptr1
107
108 /* ================= Private Inline Function declarations ===================*/
109 static __inline int dpt_just_reset(dpt_softc_t * dpt);
110 static __inline int dpt_raid_busy(dpt_softc_t * dpt);
111 static __inline int dpt_wait(dpt_softc_t *dpt, u_int bits,
112 u_int state);
113 static __inline struct dpt_ccb* dptgetccb(struct dpt_softc *dpt);
114 static __inline void dptfreeccb(struct dpt_softc *dpt,
115 struct dpt_ccb *dccb);
116 static __inline bus_addr_t dptccbvtop(struct dpt_softc *dpt,
117 struct dpt_ccb *dccb);
118
119 static __inline int dpt_send_immediate(dpt_softc_t *dpt,
120 eata_ccb_t *cmd_block,
121 u_int32_t cmd_busaddr,
122 u_int retries,
123 u_int ifc, u_int code,
124 u_int code2);
125
126 /* ==================== Private Function declarations =======================*/
127 static void dptmapmem(void *arg, bus_dma_segment_t *segs,
128 int nseg, int error);
129
130 static struct sg_map_node*
131 dptallocsgmap(struct dpt_softc *dpt);
132
133 static int dptallocccbs(dpt_softc_t *dpt);
134
135 static int dpt_get_conf(dpt_softc_t *dpt, dpt_ccb_t *dccb,
136 u_int32_t dccb_busaddr, u_int size,
137 u_int page, u_int target, int extent);
138 static void dpt_detect_cache(dpt_softc_t *dpt, dpt_ccb_t *dccb,
139 u_int32_t dccb_busaddr,
140 u_int8_t *buff);
141
142 static void dpt_poll(struct cam_sim *sim);
143 static void dpt_intr_locked(dpt_softc_t *dpt);
144
145 static void dptexecuteccb(void *arg, bus_dma_segment_t *dm_segs,
146 int nseg, int error);
147
148 static void dpt_action(struct cam_sim *sim, union ccb *ccb);
149
150 static int dpt_send_eata_command(dpt_softc_t *dpt, eata_ccb_t *cmd,
151 u_int32_t cmd_busaddr,
152 u_int command, u_int retries,
153 u_int ifc, u_int code,
154 u_int code2);
155 static void dptprocesserror(dpt_softc_t *dpt, dpt_ccb_t *dccb,
156 union ccb *ccb, u_int hba_stat,
157 u_int scsi_stat, u_int32_t resid);
158
159 static void dpttimeout(void *arg);
160 static void dptshutdown(void *arg, int howto);
161
162 /* ================= Private Inline Function definitions ====================*/
163 static __inline int
dpt_just_reset(dpt_softc_t * dpt)164 dpt_just_reset(dpt_softc_t * dpt)
165 {
166 if ((dpt_inb(dpt, 2) == 'D')
167 && (dpt_inb(dpt, 3) == 'P')
168 && (dpt_inb(dpt, 4) == 'T')
169 && (dpt_inb(dpt, 5) == 'H'))
170 return (1);
171 else
172 return (0);
173 }
174
175 static __inline int
dpt_raid_busy(dpt_softc_t * dpt)176 dpt_raid_busy(dpt_softc_t * dpt)
177 {
178 if ((dpt_inb(dpt, 0) == 'D')
179 && (dpt_inb(dpt, 1) == 'P')
180 && (dpt_inb(dpt, 2) == 'T'))
181 return (1);
182 else
183 return (0);
184 }
185
186 static __inline int
dpt_wait(dpt_softc_t * dpt,u_int bits,u_int state)187 dpt_wait(dpt_softc_t *dpt, u_int bits, u_int state)
188 {
189 int i;
190 u_int c;
191
192 for (i = 0; i < 20000; i++) { /* wait 20ms for not busy */
193 c = dpt_inb(dpt, HA_RSTATUS) & bits;
194 if (c == state)
195 return (0);
196 else
197 DELAY(50);
198 }
199 return (-1);
200 }
201
202 static __inline struct dpt_ccb*
dptgetccb(struct dpt_softc * dpt)203 dptgetccb(struct dpt_softc *dpt)
204 {
205 struct dpt_ccb* dccb;
206
207 if (!dumping)
208 mtx_assert(&dpt->lock, MA_OWNED);
209 if ((dccb = SLIST_FIRST(&dpt->free_dccb_list)) != NULL) {
210 SLIST_REMOVE_HEAD(&dpt->free_dccb_list, links);
211 dpt->free_dccbs--;
212 } else if (dpt->total_dccbs < dpt->max_dccbs) {
213 dptallocccbs(dpt);
214 dccb = SLIST_FIRST(&dpt->free_dccb_list);
215 if (dccb == NULL)
216 device_printf(dpt->dev, "Can't malloc DCCB\n");
217 else {
218 SLIST_REMOVE_HEAD(&dpt->free_dccb_list, links);
219 dpt->free_dccbs--;
220 }
221 }
222
223 return (dccb);
224 }
225
226 static __inline void
dptfreeccb(struct dpt_softc * dpt,struct dpt_ccb * dccb)227 dptfreeccb(struct dpt_softc *dpt, struct dpt_ccb *dccb)
228 {
229
230 if (!dumping)
231 mtx_assert(&dpt->lock, MA_OWNED);
232 if ((dccb->state & DCCB_ACTIVE) != 0)
233 LIST_REMOVE(&dccb->ccb->ccb_h, sim_links.le);
234 if ((dccb->state & DCCB_RELEASE_SIMQ) != 0)
235 dccb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
236 else if (dpt->resource_shortage != 0
237 && (dccb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) {
238 dccb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
239 dpt->resource_shortage = FALSE;
240 }
241 dccb->state = DCCB_FREE;
242 SLIST_INSERT_HEAD(&dpt->free_dccb_list, dccb, links);
243 ++dpt->free_dccbs;
244 }
245
246 static __inline bus_addr_t
dptccbvtop(struct dpt_softc * dpt,struct dpt_ccb * dccb)247 dptccbvtop(struct dpt_softc *dpt, struct dpt_ccb *dccb)
248 {
249 return (dpt->dpt_ccb_busbase
250 + (u_int32_t)((caddr_t)dccb - (caddr_t)dpt->dpt_dccbs));
251 }
252
253 static __inline struct dpt_ccb *
dptccbptov(struct dpt_softc * dpt,bus_addr_t busaddr)254 dptccbptov(struct dpt_softc *dpt, bus_addr_t busaddr)
255 {
256 return (dpt->dpt_dccbs
257 + ((struct dpt_ccb *)busaddr
258 - (struct dpt_ccb *)dpt->dpt_ccb_busbase));
259 }
260
261 /*
262 * Send a command for immediate execution by the DPT
263 * See above function for IMPORTANT notes.
264 */
265 static __inline int
dpt_send_immediate(dpt_softc_t * dpt,eata_ccb_t * cmd_block,u_int32_t cmd_busaddr,u_int retries,u_int ifc,u_int code,u_int code2)266 dpt_send_immediate(dpt_softc_t *dpt, eata_ccb_t *cmd_block,
267 u_int32_t cmd_busaddr, u_int retries,
268 u_int ifc, u_int code, u_int code2)
269 {
270 return (dpt_send_eata_command(dpt, cmd_block, cmd_busaddr,
271 EATA_CMD_IMMEDIATE, retries, ifc,
272 code, code2));
273 }
274
275
276 /* ===================== Private Function definitions =======================*/
277 static void
dptmapmem(void * arg,bus_dma_segment_t * segs,int nseg,int error)278 dptmapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
279 {
280 bus_addr_t *busaddrp;
281
282 busaddrp = (bus_addr_t *)arg;
283 *busaddrp = segs->ds_addr;
284 }
285
286 static struct sg_map_node *
dptallocsgmap(struct dpt_softc * dpt)287 dptallocsgmap(struct dpt_softc *dpt)
288 {
289 struct sg_map_node *sg_map;
290
291 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
292
293 if (sg_map == NULL)
294 return (NULL);
295
296 /* Allocate S/G space for the next batch of CCBS */
297 if (bus_dmamem_alloc(dpt->sg_dmat, (void **)&sg_map->sg_vaddr,
298 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
299 free(sg_map, M_DEVBUF);
300 return (NULL);
301 }
302
303 (void)bus_dmamap_load(dpt->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr,
304 PAGE_SIZE, dptmapmem, &sg_map->sg_physaddr,
305 /*flags*/0);
306
307 SLIST_INSERT_HEAD(&dpt->sg_maps, sg_map, links);
308
309 return (sg_map);
310 }
311
312 /*
313 * Allocate another chunk of CCB's. Return count of entries added.
314 */
315 static int
dptallocccbs(dpt_softc_t * dpt)316 dptallocccbs(dpt_softc_t *dpt)
317 {
318 struct dpt_ccb *next_ccb;
319 struct sg_map_node *sg_map;
320 bus_addr_t physaddr;
321 dpt_sg_t *segs;
322 int newcount;
323 int i;
324
325 if (!dumping)
326 mtx_assert(&dpt->lock, MA_OWNED);
327 next_ccb = &dpt->dpt_dccbs[dpt->total_dccbs];
328
329 if (next_ccb == dpt->dpt_dccbs) {
330 /*
331 * First time through. Re-use the S/G
332 * space we allocated for initialization
333 * CCBS.
334 */
335 sg_map = SLIST_FIRST(&dpt->sg_maps);
336 } else {
337 sg_map = dptallocsgmap(dpt);
338 }
339
340 if (sg_map == NULL)
341 return (0);
342
343 segs = sg_map->sg_vaddr;
344 physaddr = sg_map->sg_physaddr;
345
346 newcount = (PAGE_SIZE / (dpt->sgsize * sizeof(dpt_sg_t)));
347 for (i = 0; dpt->total_dccbs < dpt->max_dccbs && i < newcount; i++) {
348 int error;
349
350 error = bus_dmamap_create(dpt->buffer_dmat, /*flags*/0,
351 &next_ccb->dmamap);
352 if (error != 0)
353 break;
354 callout_init_mtx(&next_ccb->timer, &dpt->lock, 0);
355 next_ccb->sg_list = segs;
356 next_ccb->sg_busaddr = htonl(physaddr);
357 next_ccb->eata_ccb.cp_dataDMA = htonl(physaddr);
358 next_ccb->eata_ccb.cp_statDMA = htonl(dpt->sp_physaddr);
359 next_ccb->eata_ccb.cp_reqDMA =
360 htonl(dptccbvtop(dpt, next_ccb)
361 + offsetof(struct dpt_ccb, sense_data));
362 next_ccb->eata_ccb.cp_busaddr = dpt->dpt_ccb_busend;
363 next_ccb->state = DCCB_FREE;
364 next_ccb->tag = dpt->total_dccbs;
365 SLIST_INSERT_HEAD(&dpt->free_dccb_list, next_ccb, links);
366 segs += dpt->sgsize;
367 physaddr += (dpt->sgsize * sizeof(dpt_sg_t));
368 dpt->dpt_ccb_busend += sizeof(*next_ccb);
369 next_ccb++;
370 dpt->total_dccbs++;
371 }
372 return (i);
373 }
374
375 /*
376 * Read a configuration page into the supplied dpt_cont_t buffer.
377 */
378 static int
dpt_get_conf(dpt_softc_t * dpt,dpt_ccb_t * dccb,u_int32_t dccb_busaddr,u_int size,u_int page,u_int target,int extent)379 dpt_get_conf(dpt_softc_t *dpt, dpt_ccb_t *dccb, u_int32_t dccb_busaddr,
380 u_int size, u_int page, u_int target, int extent)
381 {
382 eata_ccb_t *cp;
383
384 u_int8_t status;
385
386 int ndx;
387 int result;
388
389 mtx_assert(&dpt->lock, MA_OWNED);
390 cp = &dccb->eata_ccb;
391 bzero((void *)(uintptr_t)(volatile void *)dpt->sp, sizeof(*dpt->sp));
392
393 cp->Interpret = 1;
394 cp->DataIn = 1;
395 cp->Auto_Req_Sen = 1;
396 cp->reqlen = sizeof(struct scsi_sense_data);
397
398 cp->cp_id = target;
399 cp->cp_LUN = 0; /* In the EATA packet */
400 cp->cp_lun = 0; /* In the SCSI command */
401
402 cp->cp_scsi_cmd = INQUIRY;
403 cp->cp_len = size;
404
405 cp->cp_extent = extent;
406
407 cp->cp_page = page;
408 cp->cp_channel = 0; /* DNC, Interpret mode is set */
409 cp->cp_identify = 1;
410 cp->cp_datalen = htonl(size);
411
412 /*
413 * This could be a simple for loop, but we suspected the compiler To
414 * have optimized it a bit too much. Wait for the controller to
415 * become ready
416 */
417 while (((status = dpt_inb(dpt, HA_RSTATUS)) != (HA_SREADY | HA_SSC)
418 && (status != (HA_SREADY | HA_SSC | HA_SERROR))
419 && (status != (HA_SDRDY | HA_SERROR | HA_SDRQ)))
420 || (dpt_wait(dpt, HA_SBUSY, 0))) {
421
422 /*
423 * RAID Drives still Spinning up? (This should only occur if
424 * the DPT controller is in a NON PC (PCI?) platform).
425 */
426 if (dpt_raid_busy(dpt)) {
427 device_printf(dpt->dev,
428 "WARNING: Get_conf() RSUS failed.\n");
429 return (0);
430 }
431 }
432
433 DptStat_Reset_BUSY(dpt->sp);
434
435 /*
436 * XXXX We might want to do something more clever than aborting at
437 * this point, like resetting (rebooting) the controller and trying
438 * again.
439 */
440 if ((result = dpt_send_eata_command(dpt, cp, dccb_busaddr,
441 EATA_CMD_DMA_SEND_CP,
442 10000, 0, 0, 0)) != 0) {
443 device_printf(dpt->dev,
444 "WARNING: Get_conf() failed (%d) to send "
445 "EATA_CMD_DMA_READ_CONFIG\n",
446 result);
447 return (0);
448 }
449 /* Wait for two seconds for a response. This can be slow */
450 for (ndx = 0;
451 (ndx < 20000)
452 && !((status = dpt_inb(dpt, HA_RAUXSTAT)) & HA_AIRQ);
453 ndx++) {
454 DELAY(50);
455 }
456
457 /* Grab the status and clear interrupts */
458 status = dpt_inb(dpt, HA_RSTATUS);
459
460 /*
461 * Check the status carefully. Return only if the
462 * command was successful.
463 */
464 if (((status & HA_SERROR) == 0)
465 && (dpt->sp->hba_stat == 0)
466 && (dpt->sp->scsi_stat == 0)
467 && (dpt->sp->residue_len == 0))
468 return (0);
469
470 if (dpt->sp->scsi_stat == SCSI_STATUS_CHECK_COND)
471 return (0);
472
473 return (1);
474 }
475
476 /* Detect Cache parameters and size */
477 static void
dpt_detect_cache(dpt_softc_t * dpt,dpt_ccb_t * dccb,u_int32_t dccb_busaddr,u_int8_t * buff)478 dpt_detect_cache(dpt_softc_t *dpt, dpt_ccb_t *dccb, u_int32_t dccb_busaddr,
479 u_int8_t *buff)
480 {
481 eata_ccb_t *cp;
482 u_int8_t *param;
483 int bytes;
484 int result;
485 int ndx;
486 u_int8_t status;
487
488 mtx_assert(&dpt->lock, MA_OWNED);
489
490 /*
491 * Default setting, for best performance..
492 * This is what virtually all cards default to..
493 */
494 dpt->cache_type = DPT_CACHE_WRITEBACK;
495 dpt->cache_size = 0;
496
497 cp = &dccb->eata_ccb;
498 bzero((void *)(uintptr_t)(volatile void *)dpt->sp, sizeof(dpt->sp));
499 bzero(buff, 512);
500
501 /* Setup the command structure */
502 cp->Interpret = 1;
503 cp->DataIn = 1;
504 cp->Auto_Req_Sen = 1;
505 cp->reqlen = sizeof(struct scsi_sense_data);
506
507 cp->cp_id = 0; /* who cares? The HBA will interpret.. */
508 cp->cp_LUN = 0; /* In the EATA packet */
509 cp->cp_lun = 0; /* In the SCSI command */
510 cp->cp_channel = 0;
511
512 cp->cp_scsi_cmd = EATA_CMD_DMA_SEND_CP;
513 cp->cp_len = 56;
514
515 cp->cp_extent = 0;
516 cp->cp_page = 0;
517 cp->cp_identify = 1;
518 cp->cp_dispri = 1;
519
520 /*
521 * Build the EATA Command Packet structure
522 * for a Log Sense Command.
523 */
524 cp->cp_cdb[0] = 0x4d;
525 cp->cp_cdb[1] = 0x0;
526 cp->cp_cdb[2] = 0x40 | 0x33;
527 cp->cp_cdb[7] = 1;
528
529 cp->cp_datalen = htonl(512);
530
531 result = dpt_send_eata_command(dpt, cp, dccb_busaddr,
532 EATA_CMD_DMA_SEND_CP,
533 10000, 0, 0, 0);
534 if (result != 0) {
535 device_printf(dpt->dev,
536 "WARNING: detect_cache() failed (%d) to send "
537 "EATA_CMD_DMA_SEND_CP\n", result);
538 return;
539 }
540 /* Wait for two seconds for a response. This can be slow... */
541 for (ndx = 0;
542 (ndx < 20000) &&
543 !((status = dpt_inb(dpt, HA_RAUXSTAT)) & HA_AIRQ);
544 ndx++) {
545 DELAY(50);
546 }
547
548 /* Grab the status and clear interrupts */
549 status = dpt_inb(dpt, HA_RSTATUS);
550
551 /*
552 * Sanity check
553 */
554 if (buff[0] != 0x33) {
555 return;
556 }
557 bytes = DPT_HCP_LENGTH(buff);
558 param = DPT_HCP_FIRST(buff);
559
560 if (DPT_HCP_CODE(param) != 1) {
561 /*
562 * DPT Log Page layout error
563 */
564 device_printf(dpt->dev, "NOTICE: Log Page (1) layout error\n");
565 return;
566 }
567 if (!(param[4] & 0x4)) {
568 dpt->cache_type = DPT_NO_CACHE;
569 return;
570 }
571 while (DPT_HCP_CODE(param) != 6) {
572 param = DPT_HCP_NEXT(param);
573 if ((param < buff)
574 || (param >= &buff[bytes])) {
575 return;
576 }
577 }
578
579 if (param[4] & 0x2) {
580 /*
581 * Cache disabled
582 */
583 dpt->cache_type = DPT_NO_CACHE;
584 return;
585 }
586
587 if (param[4] & 0x4) {
588 dpt->cache_type = DPT_CACHE_WRITETHROUGH;
589 }
590
591 /* XXX This isn't correct. This log parameter only has two bytes.... */
592 #if 0
593 dpt->cache_size = param[5]
594 | (param[6] << 8)
595 | (param[7] << 16)
596 | (param[8] << 24);
597 #endif
598 }
599
600 static void
dpt_poll(struct cam_sim * sim)601 dpt_poll(struct cam_sim *sim)
602 {
603 dpt_intr_locked(cam_sim_softc(sim));
604 }
605
606 static void
dptexecuteccb(void * arg,bus_dma_segment_t * dm_segs,int nseg,int error)607 dptexecuteccb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
608 {
609 struct dpt_ccb *dccb;
610 union ccb *ccb;
611 struct dpt_softc *dpt;
612
613 dccb = (struct dpt_ccb *)arg;
614 ccb = dccb->ccb;
615 dpt = (struct dpt_softc *)ccb->ccb_h.ccb_dpt_ptr;
616 if (!dumping)
617 mtx_assert(&dpt->lock, MA_OWNED);
618
619 if (error != 0) {
620 if (error != EFBIG)
621 device_printf(dpt->dev,
622 "Unexepected error 0x%x returned from "
623 "bus_dmamap_load\n", error);
624 if (ccb->ccb_h.status == CAM_REQ_INPROG) {
625 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
626 ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN;
627 }
628 dptfreeccb(dpt, dccb);
629 xpt_done(ccb);
630 return;
631 }
632
633 if (nseg != 0) {
634 dpt_sg_t *sg;
635 bus_dma_segment_t *end_seg;
636 bus_dmasync_op_t op;
637
638 end_seg = dm_segs + nseg;
639
640 /* Copy the segments into our SG list */
641 sg = dccb->sg_list;
642 while (dm_segs < end_seg) {
643 sg->seg_len = htonl(dm_segs->ds_len);
644 sg->seg_addr = htonl(dm_segs->ds_addr);
645 sg++;
646 dm_segs++;
647 }
648
649 if (nseg > 1) {
650 dccb->eata_ccb.scatter = 1;
651 dccb->eata_ccb.cp_dataDMA = dccb->sg_busaddr;
652 dccb->eata_ccb.cp_datalen =
653 htonl(nseg * sizeof(dpt_sg_t));
654 } else {
655 dccb->eata_ccb.cp_dataDMA = dccb->sg_list[0].seg_addr;
656 dccb->eata_ccb.cp_datalen = dccb->sg_list[0].seg_len;
657 }
658
659 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
660 op = BUS_DMASYNC_PREREAD;
661 else
662 op = BUS_DMASYNC_PREWRITE;
663
664 bus_dmamap_sync(dpt->buffer_dmat, dccb->dmamap, op);
665
666 } else {
667 dccb->eata_ccb.cp_dataDMA = 0;
668 dccb->eata_ccb.cp_datalen = 0;
669 }
670
671 /*
672 * Last time we need to check if this CCB needs to
673 * be aborted.
674 */
675 if (ccb->ccb_h.status != CAM_REQ_INPROG) {
676 if (nseg != 0)
677 bus_dmamap_unload(dpt->buffer_dmat, dccb->dmamap);
678 dptfreeccb(dpt, dccb);
679 xpt_done(ccb);
680 return;
681 }
682
683 dccb->state |= DCCB_ACTIVE;
684 ccb->ccb_h.status |= CAM_SIM_QUEUED;
685 LIST_INSERT_HEAD(&dpt->pending_ccb_list, &ccb->ccb_h, sim_links.le);
686 callout_reset_sbt(&dccb->timer, SBT_1MS * ccb->ccb_h.timeout, 0,
687 dpttimeout, dccb, 0);
688 if (dpt_send_eata_command(dpt, &dccb->eata_ccb,
689 dccb->eata_ccb.cp_busaddr,
690 EATA_CMD_DMA_SEND_CP, 0, 0, 0, 0) != 0) {
691 ccb->ccb_h.status = CAM_NO_HBA; /* HBA dead or just busy?? */
692 if (nseg != 0)
693 bus_dmamap_unload(dpt->buffer_dmat, dccb->dmamap);
694 dptfreeccb(dpt, dccb);
695 xpt_done(ccb);
696 }
697 }
698
699 static void
dpt_action(struct cam_sim * sim,union ccb * ccb)700 dpt_action(struct cam_sim *sim, union ccb *ccb)
701 {
702 struct dpt_softc *dpt;
703
704 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("dpt_action\n"));
705
706 dpt = (struct dpt_softc *)cam_sim_softc(sim);
707 mtx_assert(&dpt->lock, MA_OWNED);
708
709 if ((dpt->state & DPT_HA_SHUTDOWN_ACTIVE) != 0) {
710 xpt_print_path(ccb->ccb_h.path);
711 printf("controller is shutdown. Aborting CCB.\n");
712 ccb->ccb_h.status = CAM_NO_HBA;
713 xpt_done(ccb);
714 return;
715 }
716
717 switch (ccb->ccb_h.func_code) {
718 /* Common cases first */
719 case XPT_SCSI_IO: /* Execute the requested I/O operation */
720 {
721 struct ccb_scsiio *csio;
722 struct ccb_hdr *ccbh;
723 struct dpt_ccb *dccb;
724 struct eata_ccb *eccb;
725
726 csio = &ccb->csio;
727 ccbh = &ccb->ccb_h;
728 /* Max CDB length is 12 bytes */
729 if (csio->cdb_len > 12) {
730 ccb->ccb_h.status = CAM_REQ_INVALID;
731 xpt_done(ccb);
732 return;
733 }
734 if ((dccb = dptgetccb(dpt)) == NULL) {
735 dpt->resource_shortage = 1;
736 xpt_freeze_simq(sim, /*count*/1);
737 ccb->ccb_h.status = CAM_REQUEUE_REQ;
738 xpt_done(ccb);
739 return;
740 }
741 eccb = &dccb->eata_ccb;
742
743 /* Link dccb and ccb so we can find one from the other */
744 dccb->ccb = ccb;
745 ccb->ccb_h.ccb_dccb_ptr = dccb;
746 ccb->ccb_h.ccb_dpt_ptr = dpt;
747
748 /*
749 * Explicitly set all flags so that the compiler can
750 * be smart about setting them.
751 */
752 eccb->SCSI_Reset = 0;
753 eccb->HBA_Init = 0;
754 eccb->Auto_Req_Sen = (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE)
755 ? 0 : 1;
756 eccb->scatter = 0;
757 eccb->Quick = 0;
758 eccb->Interpret =
759 ccb->ccb_h.target_id == dpt->hostid[cam_sim_bus(sim)]
760 ? 1 : 0;
761 eccb->DataOut = (ccb->ccb_h.flags & CAM_DIR_OUT) ? 1 : 0;
762 eccb->DataIn = (ccb->ccb_h.flags & CAM_DIR_IN) ? 1 : 0;
763 eccb->reqlen = csio->sense_len;
764 eccb->cp_id = ccb->ccb_h.target_id;
765 eccb->cp_channel = cam_sim_bus(sim);
766 eccb->cp_LUN = ccb->ccb_h.target_lun;
767 eccb->cp_luntar = 0;
768 eccb->cp_dispri = (ccb->ccb_h.flags & CAM_DIS_DISCONNECT)
769 ? 0 : 1;
770 eccb->cp_identify = 1;
771
772 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0
773 && csio->tag_action != CAM_TAG_ACTION_NONE) {
774 eccb->cp_msg[0] = csio->tag_action;
775 eccb->cp_msg[1] = dccb->tag;
776 } else {
777 eccb->cp_msg[0] = 0;
778 eccb->cp_msg[1] = 0;
779 }
780 eccb->cp_msg[2] = 0;
781
782 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
783 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
784 bcopy(csio->cdb_io.cdb_ptr,
785 eccb->cp_cdb, csio->cdb_len);
786 } else {
787 /* I guess I could map it in... */
788 ccb->ccb_h.status = CAM_REQ_INVALID;
789 dptfreeccb(dpt, dccb);
790 xpt_done(ccb);
791 return;
792 }
793 } else {
794 bcopy(csio->cdb_io.cdb_bytes,
795 eccb->cp_cdb, csio->cdb_len);
796 }
797 /*
798 * If we have any data to send with this command,
799 * map it into bus space.
800 */
801 /* Only use S/G if there is a transfer */
802 if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
803 int error;
804
805 error = bus_dmamap_load_ccb(dpt->buffer_dmat,
806 dccb->dmamap,
807 ccb,
808 dptexecuteccb,
809 dccb, /*flags*/0);
810 if (error == EINPROGRESS) {
811 /*
812 * So as to maintain ordering,
813 * freeze the controller queue
814 * until our mapping is
815 * returned.
816 */
817 xpt_freeze_simq(sim, 1);
818 dccb->state |= CAM_RELEASE_SIMQ;
819 }
820 } else {
821 /*
822 * XXX JGibbs.
823 * Does it want them both on or both off?
824 * CAM_DIR_NONE is both on, so this code can
825 * be removed if this is also what the DPT
826 * exptects.
827 */
828 eccb->DataOut = 0;
829 eccb->DataIn = 0;
830 dptexecuteccb(dccb, NULL, 0, 0);
831 }
832 break;
833 }
834 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
835 case XPT_ABORT: /* Abort the specified CCB */
836 /* XXX Implement */
837 ccb->ccb_h.status = CAM_REQ_INVALID;
838 xpt_done(ccb);
839 break;
840 case XPT_SET_TRAN_SETTINGS:
841 {
842 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
843 xpt_done(ccb);
844 break;
845 }
846 case XPT_GET_TRAN_SETTINGS:
847 /* Get default/user set transfer settings for the target */
848 {
849 struct ccb_trans_settings *cts = &ccb->cts;
850 struct ccb_trans_settings_scsi *scsi =
851 &cts->proto_specific.scsi;
852 struct ccb_trans_settings_spi *spi =
853 &cts->xport_specific.spi;
854
855 cts->protocol = PROTO_SCSI;
856 cts->protocol_version = SCSI_REV_2;
857 cts->transport = XPORT_SPI;
858 cts->transport_version = 2;
859
860 if (cts->type == CTS_TYPE_USER_SETTINGS) {
861 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
862 spi->bus_width = (dpt->max_id > 7)
863 ? MSG_EXT_WDTR_BUS_8_BIT
864 : MSG_EXT_WDTR_BUS_16_BIT;
865 spi->sync_period = 25; /* 10MHz */
866 if (spi->sync_period != 0)
867 spi->sync_offset = 15;
868 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
869
870 spi->valid = CTS_SPI_VALID_SYNC_RATE
871 | CTS_SPI_VALID_SYNC_OFFSET
872 | CTS_SPI_VALID_BUS_WIDTH
873 | CTS_SPI_VALID_DISC;
874 scsi->valid = CTS_SCSI_VALID_TQ;
875 ccb->ccb_h.status = CAM_REQ_CMP;
876 } else {
877 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
878 }
879 xpt_done(ccb);
880 break;
881 }
882 case XPT_CALC_GEOMETRY:
883 {
884 /*
885 * XXX Use Adaptec translation until I find out how to
886 * get this information from the card.
887 */
888 cam_calc_geometry(&ccb->ccg, /*extended*/1);
889 xpt_done(ccb);
890 break;
891 }
892 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
893 {
894 /* XXX Implement */
895 ccb->ccb_h.status = CAM_REQ_CMP;
896 xpt_done(ccb);
897 break;
898 }
899 case XPT_TERM_IO: /* Terminate the I/O process */
900 /* XXX Implement */
901 ccb->ccb_h.status = CAM_REQ_INVALID;
902 xpt_done(ccb);
903 break;
904 case XPT_PATH_INQ: /* Path routing inquiry */
905 {
906 struct ccb_pathinq *cpi = &ccb->cpi;
907
908 cpi->version_num = 1;
909 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE;
910 if (dpt->max_id > 7)
911 cpi->hba_inquiry |= PI_WIDE_16;
912 cpi->target_sprt = 0;
913 cpi->hba_misc = 0;
914 cpi->hba_eng_cnt = 0;
915 cpi->max_target = dpt->max_id;
916 cpi->max_lun = dpt->max_lun;
917 cpi->initiator_id = dpt->hostid[cam_sim_bus(sim)];
918 cpi->bus_id = cam_sim_bus(sim);
919 cpi->base_transfer_speed = 3300;
920 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
921 strlcpy(cpi->hba_vid, "DPT", HBA_IDLEN);
922 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
923 cpi->unit_number = cam_sim_unit(sim);
924 cpi->transport = XPORT_SPI;
925 cpi->transport_version = 2;
926 cpi->protocol = PROTO_SCSI;
927 cpi->protocol_version = SCSI_REV_2;
928 cpi->ccb_h.status = CAM_REQ_CMP;
929 xpt_done(ccb);
930 break;
931 }
932 default:
933 ccb->ccb_h.status = CAM_REQ_INVALID;
934 xpt_done(ccb);
935 break;
936 }
937 }
938
939 /*
940 * This routine will try to send an EATA command to the DPT HBA.
941 * It will, by default, try 20,000 times, waiting 50us between tries.
942 * It returns 0 on success and 1 on failure.
943 */
944 static int
dpt_send_eata_command(dpt_softc_t * dpt,eata_ccb_t * cmd_block,u_int32_t cmd_busaddr,u_int command,u_int retries,u_int ifc,u_int code,u_int code2)945 dpt_send_eata_command(dpt_softc_t *dpt, eata_ccb_t *cmd_block,
946 u_int32_t cmd_busaddr, u_int command, u_int retries,
947 u_int ifc, u_int code, u_int code2)
948 {
949 u_int loop;
950
951 if (!retries)
952 retries = 20000;
953
954 /*
955 * I hate this polling nonsense. Wish there was a way to tell the DPT
956 * to go get commands at its own pace, or to interrupt when ready.
957 * In the mean time we will measure how many itterations it really
958 * takes.
959 */
960 for (loop = 0; loop < retries; loop++) {
961 if ((dpt_inb(dpt, HA_RAUXSTAT) & HA_ABUSY) == 0)
962 break;
963 else
964 DELAY(50);
965 }
966
967 if (loop < retries) {
968 #ifdef DPT_MEASURE_PERFORMANCE
969 if (loop > dpt->performance.max_eata_tries)
970 dpt->performance.max_eata_tries = loop;
971
972 if (loop < dpt->performance.min_eata_tries)
973 dpt->performance.min_eata_tries = loop;
974 #endif
975 } else {
976 #ifdef DPT_MEASURE_PERFORMANCE
977 ++dpt->performance.command_too_busy;
978 #endif
979 return (1);
980 }
981
982 /* The controller is alive, advance the wedge timer */
983 #ifdef DPT_RESET_HBA
984 dpt->last_contact = microtime_now;
985 #endif
986
987 if (cmd_block == NULL)
988 cmd_busaddr = 0;
989 #if (BYTE_ORDER == BIG_ENDIAN)
990 else {
991 cmd_busaddr = ((cmd_busaddr >> 24) & 0xFF)
992 | ((cmd_busaddr >> 16) & 0xFF)
993 | ((cmd_busaddr >> 8) & 0xFF)
994 | (cmd_busaddr & 0xFF);
995 }
996 #endif
997 /* And now the address */
998 dpt_outl(dpt, HA_WDMAADDR, cmd_busaddr);
999
1000 if (command == EATA_CMD_IMMEDIATE) {
1001 if (cmd_block == NULL) {
1002 dpt_outb(dpt, HA_WCODE2, code2);
1003 dpt_outb(dpt, HA_WCODE, code);
1004 }
1005 dpt_outb(dpt, HA_WIFC, ifc);
1006 }
1007 dpt_outb(dpt, HA_WCOMMAND, command);
1008
1009 return (0);
1010 }
1011
1012
1013 /* ==================== Exported Function definitions =======================*/
1014 void
dpt_alloc(device_t dev)1015 dpt_alloc(device_t dev)
1016 {
1017 dpt_softc_t *dpt = device_get_softc(dev);
1018 int i;
1019
1020 mtx_init(&dpt->lock, "dpt", NULL, MTX_DEF);
1021 SLIST_INIT(&dpt->free_dccb_list);
1022 LIST_INIT(&dpt->pending_ccb_list);
1023 for (i = 0; i < MAX_CHANNELS; i++)
1024 dpt->resetlevel[i] = DPT_HA_OK;
1025
1026 #ifdef DPT_MEASURE_PERFORMANCE
1027 dpt_reset_performance(dpt);
1028 #endif /* DPT_MEASURE_PERFORMANCE */
1029 return;
1030 }
1031
1032 void
dpt_free(struct dpt_softc * dpt)1033 dpt_free(struct dpt_softc *dpt)
1034 {
1035 switch (dpt->init_level) {
1036 default:
1037 case 5:
1038 bus_dmamap_unload(dpt->dccb_dmat, dpt->dccb_dmamap);
1039 case 4:
1040 bus_dmamem_free(dpt->dccb_dmat, dpt->dpt_dccbs,
1041 dpt->dccb_dmamap);
1042 case 3:
1043 bus_dma_tag_destroy(dpt->dccb_dmat);
1044 case 2:
1045 bus_dma_tag_destroy(dpt->buffer_dmat);
1046 case 1:
1047 {
1048 struct sg_map_node *sg_map;
1049
1050 while ((sg_map = SLIST_FIRST(&dpt->sg_maps)) != NULL) {
1051 SLIST_REMOVE_HEAD(&dpt->sg_maps, links);
1052 bus_dmamap_unload(dpt->sg_dmat,
1053 sg_map->sg_dmamap);
1054 bus_dmamem_free(dpt->sg_dmat, sg_map->sg_vaddr,
1055 sg_map->sg_dmamap);
1056 free(sg_map, M_DEVBUF);
1057 }
1058 bus_dma_tag_destroy(dpt->sg_dmat);
1059 }
1060 case 0:
1061 break;
1062 }
1063 mtx_destroy(&dpt->lock);
1064 }
1065
1066 int
dpt_alloc_resources(device_t dev)1067 dpt_alloc_resources (device_t dev)
1068 {
1069 dpt_softc_t * dpt;
1070 int error;
1071
1072 dpt = device_get_softc(dev);
1073
1074 dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type, &dpt->io_rid,
1075 RF_ACTIVE);
1076 if (dpt->io_res == NULL) {
1077 device_printf(dev, "No I/O space?!\n");
1078 error = ENOMEM;
1079 goto bad;
1080 }
1081
1082 dpt->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &dpt->irq_rid,
1083 RF_ACTIVE);
1084 if (dpt->irq_res == NULL) {
1085 device_printf(dev, "No IRQ!\n");
1086 error = ENOMEM;
1087 goto bad;
1088 }
1089
1090 return (0);
1091 bad:
1092 return(error);
1093 }
1094
1095
1096 void
dpt_release_resources(device_t dev)1097 dpt_release_resources (device_t dev)
1098 {
1099 struct dpt_softc * dpt;
1100
1101 dpt = device_get_softc(dev);
1102
1103 if (dpt->ih)
1104 bus_teardown_intr(dev, dpt->irq_res, dpt->ih);
1105 if (dpt->io_res)
1106 bus_release_resource(dev, dpt->io_type, dpt->io_rid, dpt->io_res);
1107 if (dpt->irq_res)
1108 bus_release_resource(dev, SYS_RES_IRQ, dpt->irq_rid, dpt->irq_res);
1109 if (dpt->drq_res)
1110 bus_release_resource(dev, SYS_RES_DRQ, dpt->drq_rid, dpt->drq_res);
1111
1112 return;
1113 }
1114
1115 static u_int8_t string_sizes[] =
1116 {
1117 sizeof(((dpt_inq_t*)NULL)->vendor),
1118 sizeof(((dpt_inq_t*)NULL)->modelNum),
1119 sizeof(((dpt_inq_t*)NULL)->firmware),
1120 sizeof(((dpt_inq_t*)NULL)->protocol),
1121 };
1122
1123 int
dpt_init(struct dpt_softc * dpt)1124 dpt_init(struct dpt_softc *dpt)
1125 {
1126 dpt_conf_t conf;
1127 struct sg_map_node *sg_map;
1128 dpt_ccb_t *dccb;
1129 u_int8_t *strp;
1130 int index;
1131 int i;
1132 int retval;
1133
1134 dpt->init_level = 0;
1135 SLIST_INIT(&dpt->sg_maps);
1136 mtx_lock(&dpt->lock);
1137
1138 #ifdef DPT_RESET_BOARD
1139 device_printf(dpt->dev, "resetting HBA\n");
1140 dpt_outb(dpt, HA_WCOMMAND, EATA_CMD_RESET);
1141 DELAY(750000);
1142 /* XXX Shouldn't we poll a status register or something??? */
1143 #endif
1144 /* DMA tag for our S/G structures. We allocate in page sized chunks */
1145 if (bus_dma_tag_create( /* parent */ dpt->parent_dmat,
1146 /* alignment */ 1,
1147 /* boundary */ 0,
1148 /* lowaddr */ BUS_SPACE_MAXADDR,
1149 /* highaddr */ BUS_SPACE_MAXADDR,
1150 /* filter */ NULL,
1151 /* filterarg */ NULL,
1152 /* maxsize */ PAGE_SIZE,
1153 /* nsegments */ 1,
1154 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
1155 /* flags */ 0,
1156 /* lockfunc */ NULL,
1157 /* lockarg */ NULL,
1158 &dpt->sg_dmat) != 0) {
1159 goto error_exit;
1160 }
1161
1162 dpt->init_level++;
1163
1164 /*
1165 * We allocate our DPT ccbs as a contiguous array of bus dma'able
1166 * memory. To get the allocation size, we need to know how many
1167 * ccbs the card supports. This requires a ccb. We solve this
1168 * chicken and egg problem by allocating some re-usable S/G space
1169 * up front, and treating it as our status packet, CCB, and target
1170 * memory space for these commands.
1171 */
1172 sg_map = dptallocsgmap(dpt);
1173 if (sg_map == NULL)
1174 goto error_exit;
1175
1176 dpt->sp = (volatile dpt_sp_t *)sg_map->sg_vaddr;
1177 dccb = (struct dpt_ccb *)(uintptr_t)(volatile void *)&dpt->sp[1];
1178 bzero(dccb, sizeof(*dccb));
1179 dpt->sp_physaddr = sg_map->sg_physaddr;
1180 dccb->eata_ccb.cp_dataDMA =
1181 htonl(sg_map->sg_physaddr + sizeof(dpt_sp_t) + sizeof(*dccb));
1182 dccb->eata_ccb.cp_busaddr = ~0;
1183 dccb->eata_ccb.cp_statDMA = htonl(dpt->sp_physaddr);
1184 dccb->eata_ccb.cp_reqDMA = htonl(dpt->sp_physaddr + sizeof(*dccb)
1185 + offsetof(struct dpt_ccb, sense_data));
1186
1187 /* Okay. Fetch our config */
1188 bzero(&dccb[1], sizeof(conf)); /* data area */
1189 retval = dpt_get_conf(dpt, dccb, sg_map->sg_physaddr + sizeof(dpt_sp_t),
1190 sizeof(conf), 0xc1, 7, 1);
1191
1192 if (retval != 0) {
1193 device_printf(dpt->dev, "Failed to get board configuration\n");
1194 goto error_exit;
1195 }
1196 bcopy(&dccb[1], &conf, sizeof(conf));
1197
1198 bzero(&dccb[1], sizeof(dpt->board_data));
1199 retval = dpt_get_conf(dpt, dccb, sg_map->sg_physaddr + sizeof(dpt_sp_t),
1200 sizeof(dpt->board_data), 0, conf.scsi_id0, 0);
1201 if (retval != 0) {
1202 device_printf(dpt->dev, "Failed to get inquiry information\n");
1203 goto error_exit;
1204 }
1205 bcopy(&dccb[1], &dpt->board_data, sizeof(dpt->board_data));
1206
1207 dpt_detect_cache(dpt, dccb, sg_map->sg_physaddr + sizeof(dpt_sp_t),
1208 (u_int8_t *)&dccb[1]);
1209
1210 switch (ntohl(conf.splen)) {
1211 case DPT_EATA_REVA:
1212 dpt->EATA_revision = 'a';
1213 break;
1214 case DPT_EATA_REVB:
1215 dpt->EATA_revision = 'b';
1216 break;
1217 case DPT_EATA_REVC:
1218 dpt->EATA_revision = 'c';
1219 break;
1220 case DPT_EATA_REVZ:
1221 dpt->EATA_revision = 'z';
1222 break;
1223 default:
1224 dpt->EATA_revision = '?';
1225 }
1226
1227 dpt->max_id = conf.MAX_ID;
1228 dpt->max_lun = conf.MAX_LUN;
1229 dpt->irq = conf.IRQ;
1230 dpt->dma_channel = (8 - conf.DMA_channel) & 7;
1231 dpt->channels = conf.MAX_CHAN + 1;
1232 dpt->state |= DPT_HA_OK;
1233 if (conf.SECOND)
1234 dpt->primary = FALSE;
1235 else
1236 dpt->primary = TRUE;
1237
1238 dpt->more_support = conf.MORE_support;
1239
1240 if (strncmp(dpt->board_data.firmware, "07G0", 4) >= 0)
1241 dpt->immediate_support = 1;
1242 else
1243 dpt->immediate_support = 0;
1244
1245 dpt->cplen = ntohl(conf.cplen);
1246 dpt->cppadlen = ntohs(conf.cppadlen);
1247 dpt->max_dccbs = ntohs(conf.queuesiz);
1248
1249 if (dpt->max_dccbs > 256) {
1250 device_printf(dpt->dev, "Max CCBs reduced from %d to "
1251 "256 due to tag algorithm\n", dpt->max_dccbs);
1252 dpt->max_dccbs = 256;
1253 }
1254
1255 dpt->hostid[0] = conf.scsi_id0;
1256 dpt->hostid[1] = conf.scsi_id1;
1257 dpt->hostid[2] = conf.scsi_id2;
1258
1259 if (conf.SG_64K)
1260 dpt->sgsize = 8192;
1261 else
1262 dpt->sgsize = ntohs(conf.SGsiz);
1263
1264 /* We can only get 64k buffers, so don't bother to waste space. */
1265 if (dpt->sgsize < 17 || dpt->sgsize > 32)
1266 dpt->sgsize = 32;
1267
1268 if (dpt->sgsize > dpt_max_segs)
1269 dpt->sgsize = dpt_max_segs;
1270
1271 /* DMA tag for mapping buffers into device visible space. */
1272 if (bus_dma_tag_create( /* parent */ dpt->parent_dmat,
1273 /* alignment */ 1,
1274 /* boundary */ 0,
1275 /* lowaddr */ BUS_SPACE_MAXADDR,
1276 /* highaddr */ BUS_SPACE_MAXADDR,
1277 /* filter */ NULL,
1278 /* filterarg */ NULL,
1279 /* maxsize */ DFLTPHYS,
1280 /* nsegments */ dpt->sgsize,
1281 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
1282 /* flags */ BUS_DMA_ALLOCNOW,
1283 /* lockfunc */ busdma_lock_mutex,
1284 /* lockarg */ &dpt->lock,
1285 &dpt->buffer_dmat) != 0) {
1286 device_printf(dpt->dev,
1287 "bus_dma_tag_create(...,dpt->buffer_dmat) failed\n");
1288 goto error_exit;
1289 }
1290
1291 dpt->init_level++;
1292
1293 /* DMA tag for our ccb structures and interrupt status packet */
1294 if (bus_dma_tag_create( /* parent */ dpt->parent_dmat,
1295 /* alignment */ 1,
1296 /* boundary */ 0,
1297 /* lowaddr */ BUS_SPACE_MAXADDR,
1298 /* highaddr */ BUS_SPACE_MAXADDR,
1299 /* filter */ NULL,
1300 /* filterarg */ NULL,
1301 /* maxsize */ (dpt->max_dccbs *
1302 sizeof(struct dpt_ccb)) +
1303 sizeof(dpt_sp_t),
1304 /* nsegments */ 1,
1305 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
1306 /* flags */ 0,
1307 /* lockfunc */ NULL,
1308 /* lockarg */ NULL,
1309 &dpt->dccb_dmat) != 0) {
1310 device_printf(dpt->dev,
1311 "bus_dma_tag_create(...,dpt->dccb_dmat) failed\n");
1312 goto error_exit;
1313 }
1314
1315 dpt->init_level++;
1316
1317 /* Allocation for our ccbs and interrupt status packet */
1318 if (bus_dmamem_alloc(dpt->dccb_dmat, (void **)&dpt->dpt_dccbs,
1319 BUS_DMA_NOWAIT, &dpt->dccb_dmamap) != 0) {
1320 device_printf(dpt->dev,
1321 "bus_dmamem_alloc(dpt->dccb_dmat,...) failed\n");
1322 goto error_exit;
1323 }
1324
1325 dpt->init_level++;
1326
1327 /* And permanently map them */
1328 bus_dmamap_load(dpt->dccb_dmat, dpt->dccb_dmamap,
1329 dpt->dpt_dccbs,
1330 (dpt->max_dccbs * sizeof(struct dpt_ccb))
1331 + sizeof(dpt_sp_t),
1332 dptmapmem, &dpt->dpt_ccb_busbase, /*flags*/0);
1333
1334 /* Clear them out. */
1335 bzero(dpt->dpt_dccbs,
1336 (dpt->max_dccbs * sizeof(struct dpt_ccb)) + sizeof(dpt_sp_t));
1337
1338 dpt->dpt_ccb_busend = dpt->dpt_ccb_busbase;
1339
1340 dpt->sp = (dpt_sp_t*)&dpt->dpt_dccbs[dpt->max_dccbs];
1341 dpt->sp_physaddr = dpt->dpt_ccb_busbase
1342 + (dpt->max_dccbs * sizeof(dpt_ccb_t));
1343 dpt->init_level++;
1344
1345 /* Allocate our first batch of ccbs */
1346 if (dptallocccbs(dpt) == 0) {
1347 device_printf(dpt->dev, "dptallocccbs(dpt) == 0\n");
1348 mtx_unlock(&dpt->lock);
1349 return (2);
1350 }
1351
1352 /* Prepare for Target Mode */
1353 dpt->target_mode_enabled = 1;
1354
1355 /* Nuke excess spaces from inquiry information */
1356 strp = dpt->board_data.vendor;
1357 for (i = 0; i < sizeof(string_sizes); i++) {
1358 index = string_sizes[i] - 1;
1359 while (index && (strp[index] == ' '))
1360 strp[index--] = '\0';
1361 strp += string_sizes[i];
1362 }
1363
1364 device_printf(dpt->dev, "%.8s %.16s FW Rev. %.4s, ",
1365 dpt->board_data.vendor,
1366 dpt->board_data.modelNum, dpt->board_data.firmware);
1367
1368 printf("%d channel%s, ", dpt->channels, dpt->channels > 1 ? "s" : "");
1369
1370 if (dpt->cache_type != DPT_NO_CACHE
1371 && dpt->cache_size != 0) {
1372 printf("%s Cache, ",
1373 dpt->cache_type == DPT_CACHE_WRITETHROUGH
1374 ? "Write-Through" : "Write-Back");
1375 }
1376
1377 printf("%d CCBs\n", dpt->max_dccbs);
1378 mtx_unlock(&dpt->lock);
1379 return (0);
1380
1381 error_exit:
1382 mtx_unlock(&dpt->lock);
1383 return (1);
1384 }
1385
1386 int
dpt_attach(dpt_softc_t * dpt)1387 dpt_attach(dpt_softc_t *dpt)
1388 {
1389 struct cam_devq *devq;
1390 int i;
1391
1392 /*
1393 * Create the device queue for our SIM.
1394 */
1395 devq = cam_simq_alloc(dpt->max_dccbs);
1396 if (devq == NULL)
1397 return (0);
1398
1399 mtx_lock(&dpt->lock);
1400 for (i = 0; i < dpt->channels; i++) {
1401 /*
1402 * Construct our SIM entry
1403 */
1404 dpt->sims[i] = cam_sim_alloc(dpt_action, dpt_poll, "dpt",
1405 dpt, device_get_unit(dpt->dev), &dpt->lock,
1406 /*untagged*/2,
1407 /*tagged*/dpt->max_dccbs, devq);
1408 if (dpt->sims[i] == NULL) {
1409 if (i == 0)
1410 cam_simq_free(devq);
1411 else
1412 printf( "%s(): Unable to attach bus %d "
1413 "due to resource shortage\n",
1414 __func__, i);
1415 break;
1416 }
1417
1418 if (xpt_bus_register(dpt->sims[i], dpt->dev, i) != CAM_SUCCESS){
1419 cam_sim_free(dpt->sims[i], /*free_devq*/i == 0);
1420 dpt->sims[i] = NULL;
1421 break;
1422 }
1423
1424 if (xpt_create_path(&dpt->paths[i], /*periph*/NULL,
1425 cam_sim_path(dpt->sims[i]),
1426 CAM_TARGET_WILDCARD,
1427 CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1428 xpt_bus_deregister(cam_sim_path(dpt->sims[i]));
1429 cam_sim_free(dpt->sims[i], /*free_devq*/i == 0);
1430 dpt->sims[i] = NULL;
1431 break;
1432 }
1433
1434 }
1435 mtx_unlock(&dpt->lock);
1436 if (i > 0)
1437 EVENTHANDLER_REGISTER(shutdown_final, dptshutdown,
1438 dpt, SHUTDOWN_PRI_DEFAULT);
1439 return (i);
1440 }
1441
1442 int
dpt_detach(device_t dev)1443 dpt_detach (device_t dev)
1444 {
1445 struct dpt_softc * dpt;
1446 int i;
1447
1448 dpt = device_get_softc(dev);
1449
1450 mtx_lock(&dpt->lock);
1451 for (i = 0; i < dpt->channels; i++) {
1452 #if 0
1453 xpt_async(AC_LOST_DEVICE, dpt->paths[i], NULL);
1454 #endif
1455 xpt_free_path(dpt->paths[i]);
1456 xpt_bus_deregister(cam_sim_path(dpt->sims[i]));
1457 cam_sim_free(dpt->sims[i], /*free_devq*/TRUE);
1458 }
1459 mtx_unlock(&dpt->lock);
1460
1461 dptshutdown((void *)dpt, SHUTDOWN_PRI_DEFAULT);
1462
1463 dpt_release_resources(dev);
1464
1465 dpt_free(dpt);
1466
1467 return (0);
1468 }
1469
1470 /*
1471 * This is the interrupt handler for the DPT driver.
1472 */
1473 void
dpt_intr(void * arg)1474 dpt_intr(void *arg)
1475 {
1476 dpt_softc_t *dpt;
1477
1478 dpt = arg;
1479 mtx_lock(&dpt->lock);
1480 dpt_intr_locked(dpt);
1481 mtx_unlock(&dpt->lock);
1482 }
1483
1484 void
dpt_intr_locked(dpt_softc_t * dpt)1485 dpt_intr_locked(dpt_softc_t *dpt)
1486 {
1487 dpt_ccb_t *dccb;
1488 union ccb *ccb;
1489 u_int status;
1490 u_int aux_status;
1491 u_int hba_stat;
1492 u_int scsi_stat;
1493 u_int32_t residue_len; /* Number of bytes not transferred */
1494
1495 /* First order of business is to check if this interrupt is for us */
1496 while (((aux_status = dpt_inb(dpt, HA_RAUXSTAT)) & HA_AIRQ) != 0) {
1497
1498 /*
1499 * What we want to do now, is to capture the status, all of it,
1500 * move it where it belongs, wake up whoever sleeps waiting to
1501 * process this result, and get out of here.
1502 */
1503 if (dpt->sp->ccb_busaddr < dpt->dpt_ccb_busbase
1504 || dpt->sp->ccb_busaddr >= dpt->dpt_ccb_busend) {
1505 device_printf(dpt->dev,
1506 "Encountered bogus status packet\n");
1507 status = dpt_inb(dpt, HA_RSTATUS);
1508 return;
1509 }
1510
1511 dccb = dptccbptov(dpt, dpt->sp->ccb_busaddr);
1512
1513 dpt->sp->ccb_busaddr = ~0;
1514
1515 /* Ignore status packets with EOC not set */
1516 if (dpt->sp->EOC == 0) {
1517 device_printf(dpt->dev,
1518 "ERROR: Request %d received with "
1519 "clear EOC.\n Marking as LOST.\n",
1520 dccb->transaction_id);
1521
1522 /* This CLEARS the interrupt! */
1523 status = dpt_inb(dpt, HA_RSTATUS);
1524 continue;
1525 }
1526 dpt->sp->EOC = 0;
1527
1528 /*
1529 * Double buffer the status information so the hardware can
1530 * work on updating the status packet while we decifer the
1531 * one we were just interrupted for.
1532 * According to Mark Salyzyn, we only need few pieces of it.
1533 */
1534 hba_stat = dpt->sp->hba_stat;
1535 scsi_stat = dpt->sp->scsi_stat;
1536 residue_len = dpt->sp->residue_len;
1537
1538 /* Clear interrupts, check for error */
1539 if ((status = dpt_inb(dpt, HA_RSTATUS)) & HA_SERROR) {
1540 /*
1541 * Error Condition. Check for magic cookie. Exit
1542 * this test on earliest sign of non-reset condition
1543 */
1544
1545 /* Check that this is not a board reset interrupt */
1546 if (dpt_just_reset(dpt)) {
1547 device_printf(dpt->dev, "HBA rebooted.\n"
1548 " All transactions should be "
1549 "resubmitted\n");
1550
1551 device_printf(dpt->dev,
1552 ">>---->> This is incomplete, "
1553 "fix me.... <<----<<");
1554 panic("DPT Rebooted");
1555
1556 }
1557 }
1558 /* Process CCB */
1559 ccb = dccb->ccb;
1560 callout_stop(&dccb->timer);
1561 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1562 bus_dmasync_op_t op;
1563
1564 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1565 op = BUS_DMASYNC_POSTREAD;
1566 else
1567 op = BUS_DMASYNC_POSTWRITE;
1568 bus_dmamap_sync(dpt->buffer_dmat, dccb->dmamap, op);
1569 bus_dmamap_unload(dpt->buffer_dmat, dccb->dmamap);
1570 }
1571
1572 /* Common Case inline... */
1573 if (hba_stat == HA_NO_ERROR) {
1574 ccb->csio.scsi_status = scsi_stat;
1575 ccb->ccb_h.status = 0;
1576 switch (scsi_stat) {
1577 case SCSI_STATUS_OK:
1578 ccb->ccb_h.status |= CAM_REQ_CMP;
1579 break;
1580 case SCSI_STATUS_CHECK_COND:
1581 case SCSI_STATUS_CMD_TERMINATED:
1582 bcopy(&dccb->sense_data, &ccb->csio.sense_data,
1583 ccb->csio.sense_len);
1584 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1585 /* FALLTHROUGH */
1586 default:
1587 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1588 /* XXX Freeze DevQ */
1589 break;
1590 }
1591 ccb->csio.resid = residue_len;
1592 dptfreeccb(dpt, dccb);
1593 xpt_done(ccb);
1594 } else {
1595 dptprocesserror(dpt, dccb, ccb, hba_stat, scsi_stat,
1596 residue_len);
1597 }
1598 }
1599 }
1600
1601 static void
dptprocesserror(dpt_softc_t * dpt,dpt_ccb_t * dccb,union ccb * ccb,u_int hba_stat,u_int scsi_stat,u_int32_t resid)1602 dptprocesserror(dpt_softc_t *dpt, dpt_ccb_t *dccb, union ccb *ccb,
1603 u_int hba_stat, u_int scsi_stat, u_int32_t resid)
1604 {
1605 ccb->csio.resid = resid;
1606 switch (hba_stat) {
1607 case HA_ERR_SEL_TO:
1608 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1609 break;
1610 case HA_ERR_CMD_TO:
1611 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
1612 break;
1613 case HA_SCSIBUS_RESET:
1614 case HA_HBA_POWER_UP: /* Similar effect to a bus reset??? */
1615 ccb->ccb_h.status = CAM_SCSI_BUS_RESET;
1616 break;
1617 case HA_CP_ABORTED:
1618 case HA_CP_RESET: /* XXX ??? */
1619 case HA_CP_ABORT_NA: /* XXX ??? */
1620 case HA_CP_RESET_NA: /* XXX ??? */
1621 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG)
1622 ccb->ccb_h.status = CAM_REQ_ABORTED;
1623 break;
1624 case HA_PCI_PARITY:
1625 case HA_PCI_MABORT:
1626 case HA_PCI_TABORT:
1627 case HA_PCI_STABORT:
1628 case HA_BUS_PARITY:
1629 case HA_PARITY_ERR:
1630 case HA_ECC_ERR:
1631 ccb->ccb_h.status = CAM_UNCOR_PARITY;
1632 break;
1633 case HA_UNX_MSGRJCT:
1634 ccb->ccb_h.status = CAM_MSG_REJECT_REC;
1635 break;
1636 case HA_UNX_BUSPHASE:
1637 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1638 break;
1639 case HA_UNX_BUS_FREE:
1640 ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1641 break;
1642 case HA_SCSI_HUNG:
1643 case HA_RESET_STUCK:
1644 /*
1645 * Dead??? Can the controller get unstuck
1646 * from these conditions
1647 */
1648 ccb->ccb_h.status = CAM_NO_HBA;
1649 break;
1650 case HA_RSENSE_FAIL:
1651 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1652 break;
1653 default:
1654 device_printf(dpt->dev, "Undocumented Error %x\n", hba_stat);
1655 printf("Please mail this message to shimon@simon-shapiro.org\n");
1656 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
1657 break;
1658 }
1659 dptfreeccb(dpt, dccb);
1660 xpt_done(ccb);
1661 }
1662
1663 static void
dpttimeout(void * arg)1664 dpttimeout(void *arg)
1665 {
1666 struct dpt_ccb *dccb;
1667 union ccb *ccb;
1668 struct dpt_softc *dpt;
1669
1670 dccb = (struct dpt_ccb *)arg;
1671 ccb = dccb->ccb;
1672 dpt = (struct dpt_softc *)ccb->ccb_h.ccb_dpt_ptr;
1673 mtx_assert(&dpt->lock, MA_OWNED);
1674 xpt_print_path(ccb->ccb_h.path);
1675 printf("CCB %p - timed out\n", (void *)dccb);
1676
1677 /*
1678 * Try to clear any pending jobs. FreeBSD will lose interrupts,
1679 * leaving the controller suspended, and commands timed-out.
1680 * By calling the interrupt handler, any command thus stuck will be
1681 * completed.
1682 */
1683 dpt_intr_locked(dpt);
1684
1685 if ((dccb->state & DCCB_ACTIVE) == 0) {
1686 xpt_print_path(ccb->ccb_h.path);
1687 printf("CCB %p - timed out CCB already completed\n",
1688 (void *)dccb);
1689 return;
1690 }
1691
1692 /* Abort this particular command. Leave all others running */
1693 dpt_send_immediate(dpt, &dccb->eata_ccb, dccb->eata_ccb.cp_busaddr,
1694 /*retries*/20000, EATA_SPECIFIC_ABORT, 0, 0);
1695 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
1696 }
1697
1698 /*
1699 * Shutdown the controller and ensure that the cache is completely flushed.
1700 * Called from the shutdown_final event after all disk access has completed.
1701 */
1702 static void
dptshutdown(void * arg,int howto)1703 dptshutdown(void *arg, int howto)
1704 {
1705 dpt_softc_t *dpt;
1706
1707 dpt = (dpt_softc_t *)arg;
1708
1709 device_printf(dpt->dev,
1710 "Shutting down (mode %x) HBA. Please wait...\n", howto);
1711
1712 /*
1713 * What we do for a shutdown, is give the DPT early power loss warning
1714 */
1715 mtx_lock(&dpt->lock);
1716 dpt_send_immediate(dpt, NULL, 0, EATA_POWER_OFF_WARN, 0, 0, 0);
1717 mtx_unlock(&dpt->lock);
1718 DELAY(1000 * 1000 * 5);
1719 device_printf(dpt->dev, "Controller was warned of shutdown and is now "
1720 "disabled\n");
1721 }
1722
1723 /*============================================================================*/
1724
1725 #if 0
1726 #ifdef DPT_RESET_HBA
1727
1728 /*
1729 ** Function name : dpt_reset_hba
1730 **
1731 ** Description : Reset the HBA and properly discard all pending work
1732 ** Input : Softc
1733 ** Output : Nothing
1734 */
1735 static void
1736 dpt_reset_hba(dpt_softc_t *dpt)
1737 {
1738 eata_ccb_t *ccb;
1739 dpt_ccb_t dccb, *dccbp;
1740 int result;
1741 struct scsi_xfer *xs;
1742
1743 mtx_assert(&dpt->lock, MA_OWNED);
1744
1745 /* Prepare a control block. The SCSI command part is immaterial */
1746 dccb.xs = NULL;
1747 dccb.flags = 0;
1748 dccb.state = DPT_CCB_STATE_NEW;
1749 dccb.std_callback = NULL;
1750 dccb.wrbuff_callback = NULL;
1751
1752 ccb = &dccb.eata_ccb;
1753 ccb->CP_OpCode = EATA_CMD_RESET;
1754 ccb->SCSI_Reset = 0;
1755 ccb->HBA_Init = 1;
1756 ccb->Auto_Req_Sen = 1;
1757 ccb->cp_id = 0; /* Should be ignored */
1758 ccb->DataIn = 1;
1759 ccb->DataOut = 0;
1760 ccb->Interpret = 1;
1761 ccb->reqlen = htonl(sizeof(struct scsi_sense_data));
1762 ccb->cp_statDMA = htonl(vtophys(&ccb->cp_statDMA));
1763 ccb->cp_reqDMA = htonl(vtophys(&ccb->cp_reqDMA));
1764 ccb->cp_viraddr = (u_int32_t) & ccb;
1765
1766 ccb->cp_msg[0] = HA_IDENTIFY_MSG | HA_DISCO_RECO;
1767 ccb->cp_scsi_cmd = 0; /* Should be ignored */
1768
1769 /* Lock up the submitted queue. We are very persistent here */
1770 while (dpt->queue_status & DPT_SUBMITTED_QUEUE_ACTIVE) {
1771 DELAY(100);
1772 }
1773
1774 dpt->queue_status |= DPT_SUBMITTED_QUEUE_ACTIVE;
1775
1776 /* Send the RESET message */
1777 if ((result = dpt_send_eata_command(dpt, &dccb.eata_ccb,
1778 EATA_CMD_RESET, 0, 0, 0, 0)) != 0) {
1779 device_printf(dpt->dev, "Failed to send the RESET message.\n"
1780 " Trying cold boot (ouch!)\n");
1781
1782
1783 if ((result = dpt_send_eata_command(dpt, &dccb.eata_ccb,
1784 EATA_COLD_BOOT, 0, 0,
1785 0, 0)) != 0) {
1786 panic("%s: Faild to cold boot the HBA\n",
1787 device_get_nameunit(dpt->dev));
1788 }
1789 #ifdef DPT_MEASURE_PERFORMANCE
1790 dpt->performance.cold_boots++;
1791 #endif /* DPT_MEASURE_PERFORMANCE */
1792 }
1793
1794 #ifdef DPT_MEASURE_PERFORMANCE
1795 dpt->performance.warm_starts++;
1796 #endif /* DPT_MEASURE_PERFORMANCE */
1797
1798 device_printf(dpt->dev,
1799 "Aborting pending requests. O/S should re-submit\n");
1800
1801 while ((dccbp = TAILQ_FIRST(&dpt->completed_ccbs)) != NULL) {
1802 struct scsi_xfer *xs = dccbp->xs;
1803
1804 /* Not all transactions have xs structs */
1805 if (xs != NULL) {
1806 /* Tell the kernel proper this did not complete well */
1807 xs->error |= XS_SELTIMEOUT;
1808 xs->flags |= SCSI_ITSDONE;
1809 scsi_done(xs);
1810 }
1811
1812 dpt_Qremove_submitted(dpt, dccbp);
1813
1814 /* Remember, Callbacks are NOT in the standard queue */
1815 if (dccbp->std_callback != NULL) {
1816 (dccbp->std_callback)(dpt, dccbp->eata_ccb.cp_channel,
1817 dccbp);
1818 } else {
1819 dpt_Qpush_free(dpt, dccbp);
1820 }
1821 }
1822
1823 device_printf(dpt->dev, "reset done aborting all pending commands\n");
1824 dpt->queue_status &= ~DPT_SUBMITTED_QUEUE_ACTIVE;
1825 }
1826
1827 #endif /* DPT_RESET_HBA */
1828
1829 /*
1830 * Build a Command Block for target mode READ/WRITE BUFFER,
1831 * with the ``sync'' bit ON.
1832 *
1833 * Although the length and offset are 24 bit fields in the command, they cannot
1834 * exceed 8192 bytes, so we take them as short integers andcheck their range.
1835 * If they are sensless, we round them to zero offset, maximum length and
1836 * complain.
1837 */
1838
1839 static void
1840 dpt_target_ccb(dpt_softc_t * dpt, int bus, u_int8_t target, u_int8_t lun,
1841 dpt_ccb_t * ccb, int mode, u_int8_t command,
1842 u_int16_t length, u_int16_t offset)
1843 {
1844 eata_ccb_t *cp;
1845
1846 mtx_assert(&dpt->lock, MA_OWNED);
1847 if ((length + offset) > DPT_MAX_TARGET_MODE_BUFFER_SIZE) {
1848 device_printf(dpt->dev,
1849 "Length of %d, and offset of %d are wrong\n",
1850 length, offset);
1851 length = DPT_MAX_TARGET_MODE_BUFFER_SIZE;
1852 offset = 0;
1853 }
1854 ccb->xs = NULL;
1855 ccb->flags = 0;
1856 ccb->state = DPT_CCB_STATE_NEW;
1857 ccb->std_callback = (ccb_callback) dpt_target_done;
1858 ccb->wrbuff_callback = NULL;
1859
1860 cp = &ccb->eata_ccb;
1861 cp->CP_OpCode = EATA_CMD_DMA_SEND_CP;
1862 cp->SCSI_Reset = 0;
1863 cp->HBA_Init = 0;
1864 cp->Auto_Req_Sen = 1;
1865 cp->cp_id = target;
1866 cp->DataIn = 1;
1867 cp->DataOut = 0;
1868 cp->Interpret = 0;
1869 cp->reqlen = htonl(sizeof(struct scsi_sense_data));
1870 cp->cp_statDMA = htonl(vtophys(&cp->cp_statDMA));
1871 cp->cp_reqDMA = htonl(vtophys(&cp->cp_reqDMA));
1872 cp->cp_viraddr = (u_int32_t) & ccb;
1873
1874 cp->cp_msg[0] = HA_IDENTIFY_MSG | HA_DISCO_RECO;
1875
1876 cp->cp_scsi_cmd = command;
1877 cp->cp_cdb[1] = (u_int8_t) (mode & SCSI_TM_MODE_MASK);
1878 cp->cp_lun = lun; /* Order is important here! */
1879 cp->cp_cdb[2] = 0x00; /* Buffer Id, only 1 :-( */
1880 cp->cp_cdb[3] = (length >> 16) & 0xFF; /* Buffer offset MSB */
1881 cp->cp_cdb[4] = (length >> 8) & 0xFF;
1882 cp->cp_cdb[5] = length & 0xFF;
1883 cp->cp_cdb[6] = (length >> 16) & 0xFF; /* Length MSB */
1884 cp->cp_cdb[7] = (length >> 8) & 0xFF;
1885 cp->cp_cdb[8] = length & 0xFF; /* Length LSB */
1886 cp->cp_cdb[9] = 0; /* No sync, no match bits */
1887
1888 /*
1889 * This could be optimized to live in dpt_register_buffer.
1890 * We keep it here, just in case the kernel decides to reallocate pages
1891 */
1892 if (dpt_scatter_gather(dpt, ccb, DPT_RW_BUFFER_SIZE,
1893 dpt->rw_buffer[bus][target][lun])) {
1894 device_printf(dpt->dev, "Failed to setup Scatter/Gather for "
1895 "Target-Mode buffer\n");
1896 }
1897 }
1898
1899 /* Setup a target mode READ command */
1900
1901 static void
1902 dpt_set_target(int redo, dpt_softc_t * dpt,
1903 u_int8_t bus, u_int8_t target, u_int8_t lun, int mode,
1904 u_int16_t length, u_int16_t offset, dpt_ccb_t * ccb)
1905 {
1906
1907 mtx_assert(&dpt->lock, MA_OWNED);
1908 if (dpt->target_mode_enabled) {
1909 if (!redo)
1910 dpt_target_ccb(dpt, bus, target, lun, ccb, mode,
1911 SCSI_TM_READ_BUFFER, length, offset);
1912
1913 ccb->transaction_id = ++dpt->commands_processed;
1914
1915 #ifdef DPT_MEASURE_PERFORMANCE
1916 dpt->performance.command_count[ccb->eata_ccb.cp_scsi_cmd]++;
1917 ccb->command_started = microtime_now;
1918 #endif
1919 dpt_Qadd_waiting(dpt, ccb);
1920 dpt_sched_queue(dpt);
1921 } else {
1922 device_printf(dpt->dev,
1923 "Target Mode Request, but Target Mode is OFF\n");
1924 }
1925 }
1926
1927 /*
1928 * Schedule a buffer to be sent to another target.
1929 * The work will be scheduled and the callback provided will be called when
1930 * the work is actually done.
1931 *
1932 * Please NOTE: ``Anyone'' can send a buffer, but only registered clients
1933 * get notified of receipt of buffers.
1934 */
1935
1936 int
1937 dpt_send_buffer(int unit, u_int8_t channel, u_int8_t target, u_int8_t lun,
1938 u_int8_t mode, u_int16_t length, u_int16_t offset, void *data,
1939 buff_wr_done callback)
1940 {
1941 dpt_softc_t *dpt;
1942 dpt_ccb_t *ccb = NULL;
1943
1944 /* This is an external call. Be a bit paranoid */
1945 dpt = devclass_get_device(dpt_devclass, unit);
1946 if (dpt == NULL)
1947 return (INVALID_UNIT);
1948
1949 mtx_lock(&dpt->lock);
1950 if (dpt->target_mode_enabled) {
1951 if ((channel >= dpt->channels) || (target > dpt->max_id) ||
1952 (lun > dpt->max_lun)) {
1953 mtx_unlock(&dpt->lock);
1954 return (INVALID_SENDER);
1955 }
1956 if ((dpt->rw_buffer[channel][target][lun] == NULL) ||
1957 (dpt->buffer_receiver[channel][target][lun] == NULL)) {
1958 mtx_unlock(&dpt->lock);
1959 return (NOT_REGISTERED);
1960 }
1961
1962 /* Process the free list */
1963 if ((TAILQ_EMPTY(&dpt->free_ccbs)) && dpt_alloc_freelist(dpt)) {
1964 device_printf(dpt->dev,
1965 "ERROR: Cannot allocate any more free CCB's.\n"
1966 " Please try later\n");
1967 mtx_unlock(&dpt->lock);
1968 return (NO_RESOURCES);
1969 }
1970 /* Now grab the newest CCB */
1971 if ((ccb = dpt_Qpop_free(dpt)) == NULL) {
1972 mtx_unlock(&dpt->lock);
1973 panic("%s: Got a NULL CCB from pop_free()\n",
1974 device_get_nameunit(dpt->dev));
1975 }
1976
1977 bcopy(dpt->rw_buffer[channel][target][lun] + offset, data, length);
1978 dpt_target_ccb(dpt, channel, target, lun, ccb, mode,
1979 SCSI_TM_WRITE_BUFFER,
1980 length, offset);
1981 ccb->std_callback = (ccb_callback) callback; /* Potential trouble */
1982
1983 ccb->transaction_id = ++dpt->commands_processed;
1984
1985 #ifdef DPT_MEASURE_PERFORMANCE
1986 dpt->performance.command_count[ccb->eata_ccb.cp_scsi_cmd]++;
1987 ccb->command_started = microtime_now;
1988 #endif
1989 dpt_Qadd_waiting(dpt, ccb);
1990 dpt_sched_queue(dpt);
1991
1992 mtx_unlock(&dpt->lock);
1993 return (0);
1994 }
1995 mtx_unlock(&dpt->lock);
1996 return (DRIVER_DOWN);
1997 }
1998
1999 static void
2000 dpt_target_done(dpt_softc_t * dpt, int bus, dpt_ccb_t * ccb)
2001 {
2002 eata_ccb_t *cp;
2003
2004 cp = &ccb->eata_ccb;
2005
2006 /*
2007 * Remove the CCB from the waiting queue.
2008 * We do NOT put it back on the free, etc., queues as it is a special
2009 * ccb, owned by the dpt_softc of this unit.
2010 */
2011 dpt_Qremove_completed(dpt, ccb);
2012
2013 #define br_channel (ccb->eata_ccb.cp_channel)
2014 #define br_target (ccb->eata_ccb.cp_id)
2015 #define br_lun (ccb->eata_ccb.cp_LUN)
2016 #define br_index [br_channel][br_target][br_lun]
2017 #define read_buffer_callback (dpt->buffer_receiver br_index )
2018 #define read_buffer (dpt->rw_buffer[br_channel][br_target][br_lun])
2019 #define cb(offset) (ccb->eata_ccb.cp_cdb[offset])
2020 #define br_offset ((cb(3) << 16) | (cb(4) << 8) | cb(5))
2021 #define br_length ((cb(6) << 16) | (cb(7) << 8) | cb(8))
2022
2023 /* Different reasons for being here, you know... */
2024 switch (ccb->eata_ccb.cp_scsi_cmd) {
2025 case SCSI_TM_READ_BUFFER:
2026 if (read_buffer_callback != NULL) {
2027 /* This is a buffer generated by a kernel process */
2028 read_buffer_callback(device_get_unit(dpt->dev),
2029 br_channel, br_target, br_lun,
2030 read_buffer,
2031 br_offset, br_length);
2032 } else {
2033 /*
2034 * This is a buffer waited for by a user (sleeping)
2035 * command
2036 */
2037 wakeup(ccb);
2038 }
2039
2040 /* We ALWAYS re-issue the same command; args are don't-care */
2041 dpt_set_target(1, 0, 0, 0, 0, 0, 0, 0, 0);
2042 break;
2043
2044 case SCSI_TM_WRITE_BUFFER:
2045 (ccb->wrbuff_callback) (device_get_unit(dpt->dev), br_channel,
2046 br_target, br_offset, br_length,
2047 br_lun, ccb->status_packet.hba_stat);
2048 break;
2049 default:
2050 device_printf(dpt->dev,
2051 "%s is an unsupported command for target mode\n",
2052 scsi_cmd_name(ccb->eata_ccb.cp_scsi_cmd));
2053 }
2054 dpt->target_ccb[br_channel][br_target][br_lun] = NULL;
2055 dpt_Qpush_free(dpt, ccb);
2056 }
2057
2058
2059 /*
2060 * Use this function to register a client for a buffer read target operation.
2061 * The function you register will be called every time a buffer is received
2062 * by the target mode code.
2063 */
2064 dpt_rb_t
2065 dpt_register_buffer(int unit, u_int8_t channel, u_int8_t target, u_int8_t lun,
2066 u_int8_t mode, u_int16_t length, u_int16_t offset,
2067 dpt_rec_buff callback, dpt_rb_op_t op)
2068 {
2069 dpt_softc_t *dpt;
2070 dpt_ccb_t *ccb = NULL;
2071 int ospl;
2072
2073 dpt = devclass_get_device(dpt_devclass, unit);
2074 if (dpt == NULL)
2075 return (INVALID_UNIT);
2076 mtx_lock(&dpt->lock);
2077
2078 if (dpt->state & DPT_HA_SHUTDOWN_ACTIVE) {
2079 mtx_unlock(&dpt->lock);
2080 return (DRIVER_DOWN);
2081 }
2082
2083 if ((channel > (dpt->channels - 1)) || (target > (dpt->max_id - 1)) ||
2084 (lun > (dpt->max_lun - 1))) {
2085 mtx_unlock(&dpt->lock);
2086 return (INVALID_SENDER);
2087 }
2088
2089 if (dpt->buffer_receiver[channel][target][lun] == NULL) {
2090 if (op == REGISTER_BUFFER) {
2091 /* Assign the requested callback */
2092 dpt->buffer_receiver[channel][target][lun] = callback;
2093 /* Get a CCB */
2094
2095 /* Process the free list */
2096 if ((TAILQ_EMPTY(&dpt->free_ccbs)) && dpt_alloc_freelist(dpt)) {
2097 device_printf(dpt->dev,
2098 "ERROR: Cannot allocate any more free CCB's.\n"
2099 " Please try later\n");
2100 mtx_unlock(&dpt->lock);
2101 return (NO_RESOURCES);
2102 }
2103 /* Now grab the newest CCB */
2104 if ((ccb = dpt_Qpop_free(dpt)) == NULL) {
2105 mtx_unlock(&dpt->lock);
2106 panic("%s: Got a NULL CCB from pop_free()\n",
2107 device_get_nameunit(dpt->dev));
2108 }
2109
2110 /* Clean up the leftover of the previous tenant */
2111 ccb->status = DPT_CCB_STATE_NEW;
2112 dpt->target_ccb[channel][target][lun] = ccb;
2113
2114 dpt->rw_buffer[channel][target][lun] =
2115 malloc(DPT_RW_BUFFER_SIZE, M_DEVBUF, M_NOWAIT);
2116 if (dpt->rw_buffer[channel][target][lun] == NULL) {
2117 device_printf(dpt->dev, "Failed to allocate "
2118 "Target-Mode buffer\n");
2119 dpt_Qpush_free(dpt, ccb);
2120 mtx_unlock(&dpt->lock);
2121 return (NO_RESOURCES);
2122 }
2123 dpt_set_target(0, dpt, channel, target, lun, mode,
2124 length, offset, ccb);
2125 mtx_unlock(&dpt->lock);
2126 return (SUCCESSFULLY_REGISTERED);
2127 } else {
2128 mtx_unlock(&dpt->lock);
2129 return (NOT_REGISTERED);
2130 }
2131 } else {
2132 if (op == REGISTER_BUFFER) {
2133 if (dpt->buffer_receiver[channel][target][lun] == callback) {
2134 mtx_unlock(&dpt->lock);
2135 return (ALREADY_REGISTERED);
2136 } else {
2137 mtx_unlock(&dpt->lock);
2138 return (REGISTERED_TO_ANOTHER);
2139 }
2140 } else {
2141 if (dpt->buffer_receiver[channel][target][lun] == callback) {
2142 dpt->buffer_receiver[channel][target][lun] = NULL;
2143 dpt_Qpush_free(dpt, ccb);
2144 free(dpt->rw_buffer[channel][target][lun], M_DEVBUF);
2145 mtx_unlock(&dpt->lock);
2146 return (SUCCESSFULLY_REGISTERED);
2147 } else {
2148 mtx_unlock(&dpt->lock);
2149 return (INVALID_CALLBACK);
2150 }
2151 }
2152
2153 }
2154 mtx_unlock(&dpt->lock);
2155 }
2156
2157 /* Return the state of the blinking DPT LED's */
2158 u_int8_t
2159 dpt_blinking_led(dpt_softc_t * dpt)
2160 {
2161 int ndx;
2162 u_int32_t state;
2163 u_int32_t previous;
2164 u_int8_t result;
2165
2166 mtx_assert(&dpt->lock, MA_OWNED);
2167 result = 0;
2168
2169 for (ndx = 0, state = 0, previous = 0;
2170 (ndx < 10) && (state != previous);
2171 ndx++) {
2172 previous = state;
2173 state = dpt_inl(dpt, 1);
2174 }
2175
2176 if ((state == previous) && (state == DPT_BLINK_INDICATOR))
2177 result = dpt_inb(dpt, 5);
2178
2179 return (result);
2180 }
2181
2182 /*
2183 * Execute a command which did not come from the kernel's SCSI layer.
2184 * The only way to map user commands to bus and target is to comply with the
2185 * standard DPT wire-down scheme:
2186 */
2187 int
2188 dpt_user_cmd(dpt_softc_t * dpt, eata_pt_t * user_cmd,
2189 caddr_t cmdarg, int minor_no)
2190 {
2191 dpt_ccb_t *ccb;
2192 void *data;
2193 int channel, target, lun;
2194 int huh;
2195 int result;
2196 int submitted;
2197
2198 mtx_assert(&dpt->lock, MA_OWNED);
2199 data = NULL;
2200 channel = minor2hba(minor_no);
2201 target = minor2target(minor_no);
2202 lun = minor2lun(minor_no);
2203
2204 if ((channel > (dpt->channels - 1))
2205 || (target > dpt->max_id)
2206 || (lun > dpt->max_lun))
2207 return (ENXIO);
2208
2209 if (target == dpt->sc_scsi_link[channel].adapter_targ) {
2210 /* This one is for the controller itself */
2211 if ((user_cmd->eataID[0] != 'E')
2212 || (user_cmd->eataID[1] != 'A')
2213 || (user_cmd->eataID[2] != 'T')
2214 || (user_cmd->eataID[3] != 'A')) {
2215 return (ENXIO);
2216 }
2217 }
2218 /* Get a DPT CCB, so we can prepare a command */
2219
2220 /* Process the free list */
2221 if ((TAILQ_EMPTY(&dpt->free_ccbs)) && dpt_alloc_freelist(dpt)) {
2222 device_printf(dpt->dev,
2223 "ERROR: Cannot allocate any more free CCB's.\n"
2224 " Please try later\n");
2225 return (EFAULT);
2226 }
2227 /* Now grab the newest CCB */
2228 if ((ccb = dpt_Qpop_free(dpt)) == NULL) {
2229 panic("%s: Got a NULL CCB from pop_free()\n",
2230 device_get_nameunit(dpt->dev));
2231 } else {
2232 /* Clean up the leftover of the previous tenant */
2233 ccb->status = DPT_CCB_STATE_NEW;
2234 }
2235
2236 bcopy((caddr_t) & user_cmd->command_packet, (caddr_t) & ccb->eata_ccb,
2237 sizeof(eata_ccb_t));
2238
2239 /* We do not want to do user specified scatter/gather. Why?? */
2240 if (ccb->eata_ccb.scatter == 1)
2241 return (EINVAL);
2242
2243 ccb->eata_ccb.Auto_Req_Sen = 1;
2244 ccb->eata_ccb.reqlen = htonl(sizeof(struct scsi_sense_data));
2245 ccb->eata_ccb.cp_datalen = htonl(sizeof(ccb->eata_ccb.cp_datalen));
2246 ccb->eata_ccb.cp_dataDMA = htonl(vtophys(ccb->eata_ccb.cp_dataDMA));
2247 ccb->eata_ccb.cp_statDMA = htonl(vtophys(&ccb->eata_ccb.cp_statDMA));
2248 ccb->eata_ccb.cp_reqDMA = htonl(vtophys(&ccb->eata_ccb.cp_reqDMA));
2249 ccb->eata_ccb.cp_viraddr = (u_int32_t) & ccb;
2250
2251 if (ccb->eata_ccb.DataIn || ccb->eata_ccb.DataOut) {
2252 /* Data I/O is involved in this command. Alocate buffer */
2253 if (ccb->eata_ccb.cp_datalen > PAGE_SIZE) {
2254 data = contigmalloc(ccb->eata_ccb.cp_datalen,
2255 M_TEMP, M_WAITOK, 0, ~0,
2256 ccb->eata_ccb.cp_datalen,
2257 0x10000);
2258 } else {
2259 data = malloc(ccb->eata_ccb.cp_datalen, M_TEMP,
2260 M_WAITOK);
2261 }
2262
2263 if (data == NULL) {
2264 device_printf(dpt->dev, "Cannot allocate %d bytes "
2265 "for EATA command\n",
2266 ccb->eata_ccb.cp_datalen);
2267 return (EFAULT);
2268 }
2269 #define usr_cmd_DMA (caddr_t)user_cmd->command_packet.cp_dataDMA
2270 if (ccb->eata_ccb.DataIn == 1) {
2271 if (copyin(usr_cmd_DMA,
2272 data, ccb->eata_ccb.cp_datalen) == -1)
2273 return (EFAULT);
2274 }
2275 } else {
2276 /* No data I/O involved here. Make sure the DPT knows that */
2277 ccb->eata_ccb.cp_datalen = 0;
2278 data = NULL;
2279 }
2280
2281 if (ccb->eata_ccb.FWNEST == 1)
2282 ccb->eata_ccb.FWNEST = 0;
2283
2284 if (ccb->eata_ccb.cp_datalen != 0) {
2285 if (dpt_scatter_gather(dpt, ccb, ccb->eata_ccb.cp_datalen,
2286 data) != 0) {
2287 if (data != NULL)
2288 free(data, M_TEMP);
2289 return (EFAULT);
2290 }
2291 }
2292 /**
2293 * We are required to quiet a SCSI bus.
2294 * since we do not queue comands on a bus basis,
2295 * we wait for ALL commands on a controller to complete.
2296 * In the mean time, sched_queue() will not schedule new commands.
2297 */
2298 if ((ccb->eata_ccb.cp_cdb[0] == MULTIFUNCTION_CMD)
2299 && (ccb->eata_ccb.cp_cdb[2] == BUS_QUIET)) {
2300 /* We wait for ALL traffic for this HBa to subside */
2301 dpt->state |= DPT_HA_QUIET;
2302
2303 while ((submitted = dpt->submitted_ccbs_count) != 0) {
2304 huh = mtx_sleep((void *) dpt, &dpt->lock,
2305 PCATCH | PRIBIO, "dptqt", 100 * hz);
2306 switch (huh) {
2307 case 0:
2308 /* Wakeup call received */
2309 break;
2310 case EWOULDBLOCK:
2311 /* Timer Expired */
2312 break;
2313 default:
2314 /* anything else */
2315 break;
2316 }
2317 }
2318 }
2319 /* Resume normal operation */
2320 if ((ccb->eata_ccb.cp_cdb[0] == MULTIFUNCTION_CMD)
2321 && (ccb->eata_ccb.cp_cdb[2] == BUS_UNQUIET)) {
2322 dpt->state &= ~DPT_HA_QUIET;
2323 }
2324 /**
2325 * Schedule the command and submit it.
2326 * We bypass dpt_sched_queue, as it will block on DPT_HA_QUIET
2327 */
2328 ccb->xs = NULL;
2329 ccb->flags = 0;
2330 ccb->eata_ccb.Auto_Req_Sen = 1; /* We always want this feature */
2331
2332 ccb->transaction_id = ++dpt->commands_processed;
2333 ccb->std_callback = (ccb_callback) dpt_user_cmd_done;
2334 ccb->result = (u_int32_t) & cmdarg;
2335 ccb->data = data;
2336
2337 #ifdef DPT_MEASURE_PERFORMANCE
2338 ++dpt->performance.command_count[ccb->eata_ccb.cp_scsi_cmd];
2339 ccb->command_started = microtime_now;
2340 #endif
2341 dpt_Qadd_waiting(dpt, ccb);
2342
2343 dpt_sched_queue(dpt);
2344
2345 /* Wait for the command to complete */
2346 (void) mtx_sleep((void *) ccb, &dpt->lock, PCATCH | PRIBIO, "dptucw",
2347 100 * hz);
2348
2349 /* Free allocated memory */
2350 if (data != NULL)
2351 free(data, M_TEMP);
2352
2353 return (0);
2354 }
2355
2356 static void
2357 dpt_user_cmd_done(dpt_softc_t * dpt, int bus, dpt_ccb_t * ccb)
2358 {
2359 u_int32_t result;
2360 caddr_t cmd_arg;
2361
2362 mtx_unlock(&dpt->lock);
2363
2364 /**
2365 * If Auto Request Sense is on, copyout the sense struct
2366 */
2367 #define usr_pckt_DMA (caddr_t)(intptr_t)ntohl(ccb->eata_ccb.cp_reqDMA)
2368 #define usr_pckt_len ntohl(ccb->eata_ccb.cp_datalen)
2369 if (ccb->eata_ccb.Auto_Req_Sen == 1) {
2370 if (copyout((caddr_t) & ccb->sense_data, usr_pckt_DMA,
2371 sizeof(struct scsi_sense_data))) {
2372 mtx_lock(&dpt->lock);
2373 ccb->result = EFAULT;
2374 dpt_Qpush_free(dpt, ccb);
2375 wakeup(ccb);
2376 return;
2377 }
2378 }
2379 /* If DataIn is on, copyout the data */
2380 if ((ccb->eata_ccb.DataIn == 1)
2381 && (ccb->status_packet.hba_stat == HA_NO_ERROR)) {
2382 if (copyout(ccb->data, usr_pckt_DMA, usr_pckt_len)) {
2383 mtx_lock(&dpt->lock);
2384 dpt_Qpush_free(dpt, ccb);
2385 ccb->result = EFAULT;
2386
2387 wakeup(ccb);
2388 return;
2389 }
2390 }
2391 /* Copyout the status */
2392 result = ccb->status_packet.hba_stat;
2393 cmd_arg = (caddr_t) ccb->result;
2394
2395 if (copyout((caddr_t) & result, cmd_arg, sizeof(result))) {
2396 mtx_lock(&dpt->lock);
2397 dpt_Qpush_free(dpt, ccb);
2398 ccb->result = EFAULT;
2399 wakeup(ccb);
2400 return;
2401 }
2402 mtx_lock(&dpt->lock);
2403 /* Put the CCB back in the freelist */
2404 ccb->state |= DPT_CCB_STATE_COMPLETED;
2405 dpt_Qpush_free(dpt, ccb);
2406
2407 /* Free allocated memory */
2408 return;
2409 }
2410
2411 #endif
2412