1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * All rights reserved.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: stable/12/sys/dev/cxgbe/adapter.h 370949 2021-10-21 00:10:45Z np $
30 *
31 */
32
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
35
36 #include <sys/kernel.h>
37 #include <sys/bus.h>
38 #include <sys/rman.h>
39 #include <sys/types.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/rwlock.h>
43 #include <sys/sx.h>
44 #include <sys/vmem.h>
45 #include <vm/uma.h>
46
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <machine/bus.h>
50 #include <sys/socket.h>
51 #include <sys/sysctl.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_var.h>
55 #include <net/if_media.h>
56 #include <netinet/in.h>
57 #include <netinet/tcp_lro.h>
58
59 #include "offload.h"
60 #include "t4_ioctl.h"
61 #include "common/t4_msg.h"
62 #include "firmware/t4fw_interface.h"
63
64 #define KTR_CXGBE KTR_SPARE3
65 MALLOC_DECLARE(M_CXGBE);
66 #define CXGBE_UNIMPLEMENTED(s) \
67 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
68
69 #if defined(__i386__) || defined(__amd64__)
70 static __inline void
prefetch(void * x)71 prefetch(void *x)
72 {
73 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
74 }
75 #else
76 #define prefetch(x) __builtin_prefetch(x)
77 #endif
78
79 #ifndef SYSCTL_ADD_UQUAD
80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
81 #define sysctl_handle_64 sysctl_handle_quad
82 #define CTLTYPE_U64 CTLTYPE_QUAD
83 #endif
84
85 #ifndef IFCAP_NOMAP
86 #define IFCAP_NOMAP (0)
87 #endif
88
89 SYSCTL_DECL(_hw_cxgbe);
90
91 struct adapter;
92 typedef struct adapter adapter_t;
93
94 enum {
95 /*
96 * All ingress queues use this entry size. Note that the firmware event
97 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
98 * be at least 64.
99 */
100 IQ_ESIZE = 64,
101
102 /* Default queue sizes for all kinds of ingress queues */
103 FW_IQ_QSIZE = 256,
104 RX_IQ_QSIZE = 1024,
105
106 /* All egress queues use this entry size */
107 EQ_ESIZE = 64,
108
109 /* Default queue sizes for all kinds of egress queues */
110 CTRL_EQ_QSIZE = 1024,
111 TX_EQ_QSIZE = 1024,
112
113 #if MJUMPAGESIZE != MCLBYTES
114 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
115 #else
116 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
117 #endif
118 CL_METADATA_SIZE = CACHE_LINE_SIZE,
119
120 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
121 TX_SGL_SEGS = 39,
122 TX_SGL_SEGS_TSO = 38,
123 TX_SGL_SEGS_VM = 38,
124 TX_SGL_SEGS_VM_TSO = 37,
125 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */
126 TX_SGL_SEGS_VXLAN_TSO = 37,
127 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
128 };
129
130 enum {
131 /* adapter intr_type */
132 INTR_INTX = (1 << 0),
133 INTR_MSI = (1 << 1),
134 INTR_MSIX = (1 << 2)
135 };
136
137 enum {
138 XGMAC_MTU = (1 << 0),
139 XGMAC_PROMISC = (1 << 1),
140 XGMAC_ALLMULTI = (1 << 2),
141 XGMAC_VLANEX = (1 << 3),
142 XGMAC_UCADDR = (1 << 4),
143 XGMAC_MCADDRS = (1 << 5),
144
145 XGMAC_ALL = 0xffff
146 };
147
148 enum {
149 /* flags understood by begin_synchronized_op */
150 HOLD_LOCK = (1 << 0),
151 SLEEP_OK = (1 << 1),
152 INTR_OK = (1 << 2),
153
154 /* flags understood by end_synchronized_op */
155 LOCK_HELD = HOLD_LOCK,
156 };
157
158 enum {
159 /* adapter flags */
160 FULL_INIT_DONE = (1 << 0),
161 FW_OK = (1 << 1),
162 CHK_MBOX_ACCESS = (1 << 2),
163 MASTER_PF = (1 << 3),
164 ADAP_SYSCTL_CTX = (1 << 4),
165 ADAP_ERR = (1 << 5),
166 BUF_PACKING_OK = (1 << 6),
167 IS_VF = (1 << 7),
168
169 CXGBE_BUSY = (1 << 9),
170
171 /* port flags */
172 HAS_TRACEQ = (1 << 3),
173 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */
174
175 /* VI flags */
176 DOOMED = (1 << 0),
177 VI_INIT_DONE = (1 << 1),
178 VI_SYSCTL_CTX = (1 << 2),
179 TX_USES_VM_WR = (1 << 3),
180
181 /* adapter debug_flags */
182 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
183 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
184 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
185 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */
186 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */
187 };
188
189 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
190 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
191 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
192 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
193 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
194
195 struct vi_info {
196 device_t dev;
197 struct port_info *pi;
198 struct adapter *adapter;
199
200 struct ifnet *ifp;
201
202 unsigned long flags;
203 int if_flags;
204
205 uint16_t *rss, *nm_rss;
206 uint16_t viid; /* opaque VI identifier */
207 uint16_t smt_idx;
208 uint16_t vin;
209 uint8_t vfvld;
210 int16_t xact_addr_filt;/* index of exact MAC address filter */
211 uint16_t rss_size; /* size of VI's RSS table slice */
212 uint16_t rss_base; /* start of VI's RSS table slice */
213 int hashen;
214
215 int nintr;
216 int first_intr;
217
218 /* These need to be int as they are used in sysctl */
219 int ntxq; /* # of tx queues */
220 int first_txq; /* index of first tx queue */
221 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
222 int nrxq; /* # of rx queues */
223 int first_rxq; /* index of first rx queue */
224 int nofldtxq; /* # of offload tx queues */
225 int first_ofld_txq; /* index of first offload tx queue */
226 int nofldrxq; /* # of offload rx queues */
227 int first_ofld_rxq; /* index of first offload rx queue */
228 int nnmtxq;
229 int first_nm_txq;
230 int nnmrxq;
231 int first_nm_rxq;
232 int tmr_idx;
233 int ofld_tmr_idx;
234 int pktc_idx;
235 int ofld_pktc_idx;
236 int qsize_rxq;
237 int qsize_txq;
238
239 struct timeval last_refreshed;
240 struct fw_vi_stats_vf stats;
241
242 struct callout tick;
243 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
244
245 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
246 };
247
248 struct tx_ch_rl_params {
249 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
250 uint32_t maxrate;
251 };
252
253 enum {
254 CLRL_USER = (1 << 0), /* allocated manually. */
255 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */
256 CLRL_ASYNC = (1 << 2), /* async hw update requested. */
257 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */
258 };
259
260 struct tx_cl_rl_params {
261 int refcount;
262 uint8_t flags;
263 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
264 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
265 enum fw_sched_params_mode mode; /* aggr or per-flow */
266 uint32_t maxrate;
267 uint16_t pktsize;
268 uint16_t burstsize;
269 };
270
271 /* Tx scheduler parameters for a channel/port */
272 struct tx_sched_params {
273 /* Channel Rate Limiter */
274 struct tx_ch_rl_params ch_rl;
275
276 /* Class WRR */
277 /* XXX */
278
279 /* Class Rate Limiter (including the default pktsize and burstsize). */
280 int pktsize;
281 int burstsize;
282 struct tx_cl_rl_params cl_rl[];
283 };
284
285 struct port_info {
286 device_t dev;
287 struct adapter *adapter;
288
289 struct vi_info *vi;
290 int nvi;
291 int up_vis;
292 int uld_vis;
293 bool vxlan_tcam_entry;
294
295 struct tx_sched_params *sched_params;
296
297 struct mtx pi_lock;
298 char lockname[16];
299 unsigned long flags;
300
301 uint8_t lport; /* associated offload logical port */
302 int8_t mdio_addr;
303 uint8_t port_type;
304 uint8_t mod_type;
305 uint8_t port_id;
306 uint8_t tx_chan;
307 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
308 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
309
310 struct link_config link_cfg;
311 struct ifmedia media;
312
313 struct timeval last_refreshed;
314 struct port_stats stats;
315 u_int tnl_cong_drops;
316 u_int tx_parse_error;
317 int fcs_reg;
318 uint64_t fcs_base;
319 u_long tx_toe_tls_records;
320 u_long tx_toe_tls_octets;
321 u_long rx_toe_tls_records;
322 u_long rx_toe_tls_octets;
323
324 struct callout tick;
325 };
326
327 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
328
329 struct cluster_metadata {
330 uma_zone_t zone;
331 caddr_t cl;
332 u_int refcount;
333 };
334
335 struct fl_sdesc {
336 caddr_t cl;
337 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
338 int16_t moff; /* offset of metadata from cl */
339 uint8_t zidx;
340 };
341
342 struct tx_desc {
343 __be64 flit[8];
344 };
345
346 struct tx_sdesc {
347 struct mbuf *m; /* m_nextpkt linked chain of frames */
348 uint8_t desc_used; /* # of hardware descriptors used by the WR */
349 };
350
351
352 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
353 struct iq_desc {
354 struct rss_header rss;
355 uint8_t cpl[IQ_PAD];
356 struct rsp_ctrl rsp;
357 };
358 #undef IQ_PAD
359 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
360
361 enum {
362 /* iq flags */
363 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
364 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
365 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */
366 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
367 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
368
369 /* iq state */
370 IQS_DISABLED = 0,
371 IQS_BUSY = 1,
372 IQS_IDLE = 2,
373
374 /* netmap related flags */
375 NM_OFF = 0,
376 NM_ON = 1,
377 NM_BUSY = 2,
378 };
379
380 enum {
381 CPL_COOKIE_RESERVED = 0,
382 CPL_COOKIE_FILTER,
383 CPL_COOKIE_DDP0,
384 CPL_COOKIE_DDP1,
385 CPL_COOKIE_TOM,
386 CPL_COOKIE_HASHFILTER,
387 CPL_COOKIE_ETHOFLD,
388 CPL_COOKIE_AVAILABLE3,
389
390 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
391 };
392
393 struct sge_iq;
394 struct rss_header;
395 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
396 struct mbuf *);
397 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
398 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
399
400 /*
401 * Ingress Queue: T4 is producer, driver is consumer.
402 */
403 struct sge_iq {
404 uint32_t flags;
405 volatile int state;
406 struct adapter *adapter;
407 struct iq_desc *desc; /* KVA of descriptor ring */
408 int8_t intr_pktc_idx; /* packet count threshold index */
409 uint8_t gen; /* generation bit */
410 uint8_t intr_params; /* interrupt holdoff parameters */
411 uint8_t intr_next; /* XXX: holdoff for next interrupt */
412 uint16_t qsize; /* size (# of entries) of the queue */
413 uint16_t sidx; /* index of the entry with the status page */
414 uint16_t cidx; /* consumer index */
415 uint16_t cntxt_id; /* SGE context id for the iq */
416 uint16_t abs_id; /* absolute SGE id for the iq */
417
418 STAILQ_ENTRY(sge_iq) link;
419
420 bus_dma_tag_t desc_tag;
421 bus_dmamap_t desc_map;
422 bus_addr_t ba; /* bus address of descriptor ring */
423 };
424
425 enum {
426 EQ_CTRL = 1,
427 EQ_ETH = 2,
428 EQ_OFLD = 3,
429
430 /* eq flags */
431 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
432 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
433 EQ_ENABLED = (1 << 3), /* open for business */
434 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
435 };
436
437 /* Listed in order of preference. Update t4_sysctls too if you change these */
438 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
439
440 /*
441 * Egress Queue: driver is producer, T4 is consumer.
442 *
443 * Note: A free list is an egress queue (driver produces the buffers and T4
444 * consumes them) but it's special enough to have its own struct (see sge_fl).
445 */
446 struct sge_eq {
447 unsigned int flags; /* MUST be first */
448 unsigned int cntxt_id; /* SGE context id for the eq */
449 unsigned int abs_id; /* absolute SGE id for the eq */
450 struct mtx eq_lock;
451
452 struct tx_desc *desc; /* KVA of descriptor ring */
453 uint8_t doorbells;
454 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
455 u_int udb_qid; /* relative qid within the doorbell page */
456 uint16_t sidx; /* index of the entry with the status page */
457 uint16_t cidx; /* consumer idx (desc idx) */
458 uint16_t pidx; /* producer idx (desc idx) */
459 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
460 uint16_t dbidx; /* pidx of the most recent doorbell */
461 uint16_t iqid; /* iq that gets egr_update for the eq */
462 uint8_t tx_chan; /* tx channel used by the eq */
463 volatile u_int equiq; /* EQUIQ outstanding */
464
465 bus_dma_tag_t desc_tag;
466 bus_dmamap_t desc_map;
467 bus_addr_t ba; /* bus address of descriptor ring */
468 char lockname[16];
469 };
470
471 struct rx_buf_info {
472 uma_zone_t zone; /* zone that this cluster comes from */
473 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K.
474 * hwsize[hwidx1] = size1. No spare. */
475 uint16_t size2; /* hwsize[hwidx2] = size2.
476 * spare in cluster = size1 - size2. */
477 int8_t hwidx1; /* SGE bufsize idx for size1 */
478 int8_t hwidx2; /* SGE bufsize idx for size2 */
479 uint8_t type; /* EXT_xxx type of the cluster */
480 };
481
482 enum {
483 NUM_MEMWIN = 3,
484
485 MEMWIN0_APERTURE = 2048,
486 MEMWIN0_BASE = 0x1b800,
487
488 MEMWIN1_APERTURE = 32768,
489 MEMWIN1_BASE = 0x28000,
490
491 MEMWIN2_APERTURE_T4 = 65536,
492 MEMWIN2_BASE_T4 = 0x30000,
493
494 MEMWIN2_APERTURE_T5 = 128 * 1024,
495 MEMWIN2_BASE_T5 = 0x60000,
496 };
497
498 struct memwin {
499 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
500 uint32_t mw_base; /* constant after setup_memwin */
501 uint32_t mw_aperture; /* ditto */
502 uint32_t mw_curpos; /* protected by mw_lock */
503 };
504
505 enum {
506 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
507 FL_DOOMED = (1 << 1), /* about to be destroyed */
508 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
509 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
510 };
511
512 #define FL_RUNNING_LOW(fl) \
513 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
514 #define FL_NOT_RUNNING_LOW(fl) \
515 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
516
517 struct sge_fl {
518 struct mtx fl_lock;
519 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
520 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
521 uint16_t zidx; /* refill zone idx */
522 uint16_t safe_zidx;
523 uint16_t lowat; /* # of buffers <= this means fl needs help */
524 int flags;
525 uint16_t buf_boundary;
526
527 /* The 16b idx all deal with hw descriptors */
528 uint16_t dbidx; /* hw pidx after last doorbell */
529 uint16_t sidx; /* index of status page */
530 volatile uint16_t hw_cidx;
531
532 /* The 32b idx are all buffer idx, not hardware descriptor idx */
533 uint32_t cidx; /* consumer index */
534 uint32_t pidx; /* producer index */
535
536 uint32_t dbval;
537 u_int rx_offset; /* offset in fl buf (when buffer packing) */
538 volatile uint32_t *udb;
539
540 uint64_t cl_allocated; /* # of clusters allocated */
541 uint64_t cl_recycled; /* # of clusters recycled */
542 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
543
544 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
545 struct mbuf *m0;
546 struct mbuf **pnext;
547 u_int remaining;
548
549 uint16_t qsize; /* # of hw descriptors (status page included) */
550 uint16_t cntxt_id; /* SGE context id for the freelist */
551 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
552 bus_dma_tag_t desc_tag;
553 bus_dmamap_t desc_map;
554 char lockname[16];
555 bus_addr_t ba; /* bus address of descriptor ring */
556 };
557
558 struct mp_ring;
559
560 struct txpkts {
561 uint8_t wr_type; /* type 0 or type 1 */
562 uint8_t npkt; /* # of packets in this work request */
563 uint8_t len16; /* # of 16B pieces used by this work request */
564 uint8_t score;
565 uint8_t max_npkt; /* maximum number of packets allowed */
566 uint16_t plen; /* total payload (sum of all packets) */
567
568 /* straight from fw_eth_tx_pkts_vm_wr. */
569 __u8 ethmacdst[6];
570 __u8 ethmacsrc[6];
571 __be16 ethtype;
572 __be16 vlantci;
573
574 struct mbuf *mb[15];
575 };
576
577 /* txq: SGE egress queue + what's needed for Ethernet NIC */
578 struct sge_txq {
579 struct sge_eq eq; /* MUST be first */
580
581 struct ifnet *ifp; /* the interface this txq belongs to */
582 struct mp_ring *r; /* tx software ring */
583 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
584 struct sglist *gl;
585 __be32 cpl_ctrl0; /* for convenience */
586 int tc_idx; /* traffic class */
587 uint64_t last_tx; /* cycle count when eth_tx was last called */
588 struct txpkts txp;
589
590 struct task tx_reclaim_task;
591 /* stats for common events first */
592
593 uint64_t txcsum; /* # of times hardware assisted with checksum */
594 uint64_t tso_wrs; /* # of TSO work requests */
595 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
596 uint64_t imm_wrs; /* # of work requests with immediate data */
597 uint64_t sgl_wrs; /* # of work requests with direct SGL */
598 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
599 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
600 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
601 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
602 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
603 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */
604 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */
605 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */
606 uint64_t vxlan_txcsum;
607
608 /* stats for not-that-common events */
609 } __aligned(CACHE_LINE_SIZE);
610
611 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
612 struct sge_rxq {
613 struct sge_iq iq; /* MUST be first */
614 struct sge_fl fl; /* MUST follow iq */
615
616 struct ifnet *ifp; /* the interface this rxq belongs to */
617 #if defined(INET) || defined(INET6)
618 struct lro_ctrl lro; /* LRO state */
619 #endif
620
621 /* stats for common events first */
622
623 uint64_t rxcsum; /* # of times hardware assisted with checksum */
624 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
625 uint64_t vxlan_rxcsum;
626
627 /* stats for not-that-common events */
628
629 } __aligned(CACHE_LINE_SIZE);
630
631 static inline struct sge_rxq *
iq_to_rxq(struct sge_iq * iq)632 iq_to_rxq(struct sge_iq *iq)
633 {
634
635 return (__containerof(iq, struct sge_rxq, iq));
636 }
637
638
639 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
640 struct sge_ofld_rxq {
641 struct sge_iq iq; /* MUST be first */
642 struct sge_fl fl; /* MUST follow iq */
643 } __aligned(CACHE_LINE_SIZE);
644
645 static inline struct sge_ofld_rxq *
iq_to_ofld_rxq(struct sge_iq * iq)646 iq_to_ofld_rxq(struct sge_iq *iq)
647 {
648
649 return (__containerof(iq, struct sge_ofld_rxq, iq));
650 }
651
652 struct wrqe {
653 STAILQ_ENTRY(wrqe) link;
654 struct sge_wrq *wrq;
655 int wr_len;
656 char wr[] __aligned(16);
657 };
658
659 struct wrq_cookie {
660 TAILQ_ENTRY(wrq_cookie) link;
661 int ndesc;
662 int pidx;
663 };
664
665 /*
666 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
667 * and offload tx queues are of this type.
668 */
669 struct sge_wrq {
670 struct sge_eq eq; /* MUST be first */
671
672 struct adapter *adapter;
673 struct task wrq_tx_task;
674
675 /* Tx desc reserved but WR not "committed" yet. */
676 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
677
678 /* List of WRs ready to go out as soon as descriptors are available. */
679 STAILQ_HEAD(, wrqe) wr_list;
680 u_int nwr_pending;
681 u_int ndesc_needed;
682
683 /* stats for common events first */
684
685 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
686 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
687 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
688
689 /* stats for not-that-common events */
690
691 /*
692 * Scratch space for work requests that wrap around after reaching the
693 * status page, and some information about the last WR that used it.
694 */
695 uint16_t ss_pidx;
696 uint16_t ss_len;
697 uint8_t ss[SGE_MAX_WR_LEN];
698
699 } __aligned(CACHE_LINE_SIZE);
700
701 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
702 struct sge_nm_rxq {
703 /* Items used by the driver rx ithread are in this cacheline. */
704 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */
705 u_int nid; /* netmap ring # for this queue */
706 struct vi_info *vi;
707
708 struct iq_desc *iq_desc;
709 uint16_t iq_abs_id;
710 uint16_t iq_cntxt_id;
711 uint16_t iq_cidx;
712 uint16_t iq_sidx;
713 uint8_t iq_gen;
714 uint32_t fl_sidx;
715
716 /* Items used by netmap rxsync are in this cacheline. */
717 __be64 *fl_desc __aligned(CACHE_LINE_SIZE);
718 uint16_t fl_cntxt_id;
719 uint32_t fl_pidx;
720 uint32_t fl_sidx2; /* copy of fl_sidx */
721 uint32_t fl_db_val;
722 u_int fl_db_saved;
723 u_int fl_db_threshold; /* in descriptors */
724 u_int fl_hwidx:4;
725
726 /*
727 * fl_cidx is used by both the ithread and rxsync, the rest are not used
728 * in the rx fast path.
729 */
730 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE);
731
732 bus_dma_tag_t iq_desc_tag;
733 bus_dmamap_t iq_desc_map;
734 bus_addr_t iq_ba;
735 int intr_idx;
736
737 bus_dma_tag_t fl_desc_tag;
738 bus_dmamap_t fl_desc_map;
739 bus_addr_t fl_ba;
740 };
741
742 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
743 struct sge_nm_txq {
744 struct tx_desc *desc;
745 uint16_t cidx;
746 uint16_t pidx;
747 uint16_t sidx;
748 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
749 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
750 uint16_t dbidx; /* pidx of the most recent doorbell */
751 uint8_t doorbells;
752 volatile uint32_t *udb;
753 u_int udb_qid;
754 u_int cntxt_id;
755 __be32 cpl_ctrl0; /* for convenience */
756 __be32 op_pkd; /* ditto */
757 u_int nid; /* netmap ring # for this queue */
758
759 /* infrequently used items after this */
760
761 bus_dma_tag_t desc_tag;
762 bus_dmamap_t desc_map;
763 bus_addr_t ba;
764 int iqidx;
765 } __aligned(CACHE_LINE_SIZE);
766
767 struct sge {
768 int nrxq; /* total # of Ethernet rx queues */
769 int ntxq; /* total # of Ethernet tx queues */
770 int nofldrxq; /* total # of TOE rx queues */
771 int nofldtxq; /* total # of TOE tx queues */
772 int nnmrxq; /* total # of netmap rx queues */
773 int nnmtxq; /* total # of netmap tx queues */
774 int niq; /* total # of ingress queues */
775 int neq; /* total # of egress queues */
776
777 struct sge_iq fwq; /* Firmware event queue */
778 struct sge_wrq *ctrlq; /* Control queues */
779 struct sge_txq *txq; /* NIC tx queues */
780 struct sge_rxq *rxq; /* NIC rx queues */
781 struct sge_wrq *ofld_txq; /* TOE tx queues */
782 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
783 struct sge_nm_txq *nm_txq; /* netmap tx queues */
784 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
785
786 uint16_t iq_start; /* first cntxt_id */
787 uint16_t iq_base; /* first abs_id */
788 int eq_start; /* first cntxt_id */
789 int eq_base; /* first abs_id */
790 int iqmap_sz;
791 int eqmap_sz;
792 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
793 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
794
795 int8_t safe_zidx;
796 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES];
797 };
798
799 struct devnames {
800 const char *nexus_name;
801 const char *ifnet_name;
802 const char *vi_ifnet_name;
803 const char *pf03_drv_name;
804 const char *vf_nexus_name;
805 const char *vf_ifnet_name;
806 };
807
808 struct clip_entry;
809
810 struct adapter {
811 SLIST_ENTRY(adapter) link;
812 device_t dev;
813 struct cdev *cdev;
814 const struct devnames *names;
815
816 /* PCIe register resources */
817 int regs_rid;
818 struct resource *regs_res;
819 int msix_rid;
820 struct resource *msix_res;
821 bus_space_handle_t bh;
822 bus_space_tag_t bt;
823 bus_size_t mmio_len;
824 int udbs_rid;
825 struct resource *udbs_res;
826 volatile uint8_t *udbs_base;
827
828 unsigned int pf;
829 unsigned int mbox;
830 unsigned int vpd_busy;
831 unsigned int vpd_flag;
832
833 /* Interrupt information */
834 int intr_type;
835 int intr_count;
836 struct irq {
837 struct resource *res;
838 int rid;
839 void *tag;
840 struct sge_rxq *rxq;
841 struct sge_nm_rxq *nm_rxq;
842 } __aligned(CACHE_LINE_SIZE) *irq;
843 int sge_gts_reg;
844 int sge_kdoorbell_reg;
845
846 bus_dma_tag_t dmat; /* Parent DMA tag */
847
848 struct sge sge;
849 int lro_timeout;
850 int sc_do_rxcopy;
851
852 int vxlan_port;
853 u_int vxlan_refcount;
854 int rawf_base;
855 int nrawf;
856
857 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
858 struct port_info *port[MAX_NPORTS];
859 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
860
861 struct mtx clip_table_lock;
862 TAILQ_HEAD(, clip_entry) clip_table;
863 int clip_gen;
864
865 void *tom_softc; /* (struct tom_data *) */
866 struct tom_tunables tt;
867 struct t4_offload_policy *policy;
868 struct rwlock policy_lock;
869
870 void *iwarp_softc; /* (struct c4iw_dev *) */
871 struct iw_tunables iwt;
872 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
873 void *ccr_softc; /* (struct ccr_softc *) */
874 struct l2t_data *l2t; /* L2 table */
875 struct smt_data *smt; /* Source MAC Table */
876 struct tid_info tids;
877 vmem_t *key_map;
878
879 uint8_t doorbells;
880 int offload_map; /* ports with IFCAP_TOE enabled */
881 int active_ulds; /* ULDs activated on this adapter */
882 int flags;
883 int debug_flags;
884
885 char ifp_lockname[16];
886 struct mtx ifp_lock;
887 struct ifnet *ifp; /* tracer ifp */
888 struct ifmedia media;
889 int traceq; /* iq used by all tracers, -1 if none */
890 int tracer_valid; /* bitmap of valid tracers */
891 int tracer_enabled; /* bitmap of enabled tracers */
892
893 char fw_version[16];
894 char tp_version[16];
895 char er_version[16];
896 char bs_version[16];
897 char cfg_file[32];
898 u_int cfcsum;
899 struct adapter_params params;
900 const struct chip_params *chip_params;
901 struct t4_virt_res vres;
902
903 uint16_t nbmcaps;
904 uint16_t linkcaps;
905 uint16_t switchcaps;
906 uint16_t niccaps;
907 uint16_t toecaps;
908 uint16_t rdmacaps;
909 uint16_t cryptocaps;
910 uint16_t iscsicaps;
911 uint16_t fcoecaps;
912
913 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
914
915 struct mtx sc_lock;
916 char lockname[16];
917
918 /* Starving free lists */
919 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
920 TAILQ_HEAD(, sge_fl) sfl;
921 struct callout sfl_callout;
922
923 struct mtx reg_lock; /* for indirect register access */
924
925 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
926
927 struct mtx tc_lock;
928 struct task tc_task;
929
930 const char *last_op;
931 const void *last_op_thr;
932 int last_op_flags;
933
934 int swintr;
935 int sensor_resets;
936 };
937
938 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
939 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
940 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
941 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
942
943 #define ASSERT_SYNCHRONIZED_OP(sc) \
944 KASSERT(IS_BUSY(sc) && \
945 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
946 ("%s: operation not synchronized.", __func__))
947
948 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
949 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
950 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
951 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
952
953 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
954 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
955 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
956 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
957 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
958
959 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
960 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
961 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
962 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
963
964 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
965 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
966 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
967 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
968 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
969
970 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
971 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
972 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
973 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
974 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
975
976 #define for_each_txq(vi, iter, q) \
977 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \
978 iter < vi->ntxq; ++iter, ++q)
979 #define for_each_rxq(vi, iter, q) \
980 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
981 iter < vi->nrxq; ++iter, ++q)
982 #define for_each_ofld_txq(vi, iter, q) \
983 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
984 iter < vi->nofldtxq; ++iter, ++q)
985 #define for_each_ofld_rxq(vi, iter, q) \
986 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
987 iter < vi->nofldrxq; ++iter, ++q)
988 #define for_each_nm_txq(vi, iter, q) \
989 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
990 iter < vi->nnmtxq; ++iter, ++q)
991 #define for_each_nm_rxq(vi, iter, q) \
992 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
993 iter < vi->nnmrxq; ++iter, ++q)
994 #define for_each_vi(_pi, _iter, _vi) \
995 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
996 ++(_iter), ++(_vi))
997
998 #define IDXINCR(idx, incr, wrap) do { \
999 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
1000 } while (0)
1001 #define IDXDIFF(head, tail, wrap) \
1002 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
1003
1004 /* One for errors, one for firmware events */
1005 #define T4_EXTRA_INTR 2
1006
1007 /* One for firmware events */
1008 #define T4VF_EXTRA_INTR 1
1009
1010 static inline int
forwarding_intr_to_fwq(struct adapter * sc)1011 forwarding_intr_to_fwq(struct adapter *sc)
1012 {
1013
1014 return (sc->intr_count == 1);
1015 }
1016
1017 static inline uint32_t
t4_read_reg(struct adapter * sc,uint32_t reg)1018 t4_read_reg(struct adapter *sc, uint32_t reg)
1019 {
1020
1021 return bus_space_read_4(sc->bt, sc->bh, reg);
1022 }
1023
1024 static inline void
t4_write_reg(struct adapter * sc,uint32_t reg,uint32_t val)1025 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
1026 {
1027
1028 bus_space_write_4(sc->bt, sc->bh, reg, val);
1029 }
1030
1031 static inline uint64_t
t4_read_reg64(struct adapter * sc,uint32_t reg)1032 t4_read_reg64(struct adapter *sc, uint32_t reg)
1033 {
1034
1035 #ifdef __LP64__
1036 return bus_space_read_8(sc->bt, sc->bh, reg);
1037 #else
1038 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1039 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1040
1041 #endif
1042 }
1043
1044 static inline void
t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val)1045 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1046 {
1047
1048 #ifdef __LP64__
1049 bus_space_write_8(sc->bt, sc->bh, reg, val);
1050 #else
1051 bus_space_write_4(sc->bt, sc->bh, reg, val);
1052 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1053 #endif
1054 }
1055
1056 static inline void
t4_os_pci_read_cfg1(struct adapter * sc,int reg,uint8_t * val)1057 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1058 {
1059
1060 *val = pci_read_config(sc->dev, reg, 1);
1061 }
1062
1063 static inline void
t4_os_pci_write_cfg1(struct adapter * sc,int reg,uint8_t val)1064 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1065 {
1066
1067 pci_write_config(sc->dev, reg, val, 1);
1068 }
1069
1070 static inline void
t4_os_pci_read_cfg2(struct adapter * sc,int reg,uint16_t * val)1071 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1072 {
1073
1074 *val = pci_read_config(sc->dev, reg, 2);
1075 }
1076
1077 static inline void
t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val)1078 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1079 {
1080
1081 pci_write_config(sc->dev, reg, val, 2);
1082 }
1083
1084 static inline void
t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val)1085 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1086 {
1087
1088 *val = pci_read_config(sc->dev, reg, 4);
1089 }
1090
1091 static inline void
t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val)1092 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1093 {
1094
1095 pci_write_config(sc->dev, reg, val, 4);
1096 }
1097
1098 static inline struct port_info *
adap2pinfo(struct adapter * sc,int idx)1099 adap2pinfo(struct adapter *sc, int idx)
1100 {
1101
1102 return (sc->port[idx]);
1103 }
1104
1105 static inline void
t4_os_set_hw_addr(struct port_info * pi,uint8_t hw_addr[])1106 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1107 {
1108
1109 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1110 }
1111
1112 static inline int
tx_resume_threshold(struct sge_eq * eq)1113 tx_resume_threshold(struct sge_eq *eq)
1114 {
1115
1116 /* not quite the same as qsize / 4, but this will do. */
1117 return (eq->sidx / 4);
1118 }
1119
1120 static inline int
t4_use_ldst(struct adapter * sc)1121 t4_use_ldst(struct adapter *sc)
1122 {
1123
1124 #ifdef notyet
1125 return (sc->flags & FW_OK || !sc->use_bd);
1126 #else
1127 return (0);
1128 #endif
1129 }
1130
1131 static inline void
CH_DUMP_MBOX(struct adapter * sc,int mbox,const int reg,const char * msg,const __be64 * const p,const bool err)1132 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1133 const char *msg, const __be64 *const p, const bool err)
1134 {
1135
1136 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1137 return;
1138 if (p != NULL) {
1139 log(err ? LOG_ERR : LOG_DEBUG,
1140 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1141 "%016llx %016llx %016llx %016llx\n",
1142 device_get_nameunit(sc->dev), mbox, msg,
1143 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1144 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1145 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1146 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1147 } else {
1148 log(err ? LOG_ERR : LOG_DEBUG,
1149 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1150 "%016llx %016llx %016llx %016llx\n",
1151 device_get_nameunit(sc->dev), mbox, msg,
1152 (long long)t4_read_reg64(sc, reg),
1153 (long long)t4_read_reg64(sc, reg + 8),
1154 (long long)t4_read_reg64(sc, reg + 16),
1155 (long long)t4_read_reg64(sc, reg + 24),
1156 (long long)t4_read_reg64(sc, reg + 32),
1157 (long long)t4_read_reg64(sc, reg + 40),
1158 (long long)t4_read_reg64(sc, reg + 48),
1159 (long long)t4_read_reg64(sc, reg + 56));
1160 }
1161 }
1162
1163 /* t4_main.c */
1164 extern int t4_ntxq;
1165 extern int t4_nrxq;
1166 extern int t4_intr_types;
1167 extern int t4_tmr_idx;
1168 extern int t4_pktc_idx;
1169 extern unsigned int t4_qsize_rxq;
1170 extern unsigned int t4_qsize_txq;
1171 extern device_method_t cxgbe_methods[];
1172
1173 int t4_os_find_pci_capability(struct adapter *, int);
1174 int t4_os_pci_save_state(struct adapter *);
1175 int t4_os_pci_restore_state(struct adapter *);
1176 void t4_os_portmod_changed(struct port_info *);
1177 void t4_os_link_changed(struct port_info *);
1178 void t4_iterate(void (*)(struct adapter *, void *), void *);
1179 void t4_init_devnames(struct adapter *);
1180 void t4_add_adapter(struct adapter *);
1181 int t4_detach_common(device_t);
1182 int t4_map_bars_0_and_4(struct adapter *);
1183 int t4_map_bar_2(struct adapter *);
1184 int t4_setup_intr_handlers(struct adapter *);
1185 void t4_sysctls(struct adapter *);
1186 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1187 void doom_vi(struct adapter *, struct vi_info *);
1188 void end_synchronized_op(struct adapter *, int);
1189 int update_mac_settings(struct ifnet *, int);
1190 int adapter_full_init(struct adapter *);
1191 int adapter_full_uninit(struct adapter *);
1192 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1193 int vi_full_init(struct vi_info *);
1194 int vi_full_uninit(struct vi_info *);
1195 void vi_sysctls(struct vi_info *);
1196 void vi_tick(void *);
1197 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1198 int alloc_atid_tab(struct tid_info *, int);
1199 void free_atid_tab(struct tid_info *);
1200 int alloc_atid(struct adapter *, void *);
1201 void *lookup_atid(struct adapter *, int);
1202 void free_atid(struct adapter *, int);
1203 void release_tid(struct adapter *, int, struct sge_wrq *);
1204 int cxgbe_media_change(struct ifnet *);
1205 void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
1206 bool t4_os_dump_cimla(struct adapter *, int, bool);
1207 void t4_os_dump_devlog(struct adapter *);
1208
1209 /* t4_keyctx.c */
1210 struct auth_hash;
1211 union authctx;
1212
1213 void t4_aes_getdeckey(void *, const void *, unsigned int);
1214 void t4_copy_partial_hash(int, union authctx *, void *);
1215 void t4_init_gmac_hash(const char *, int, char *);
1216 void t4_init_hmac_digest(struct auth_hash *, u_int, char *, int, char *);
1217
1218 #ifdef DEV_NETMAP
1219 /* t4_netmap.c */
1220 struct sge_nm_rxq;
1221 void cxgbe_nm_attach(struct vi_info *);
1222 void cxgbe_nm_detach(struct vi_info *);
1223 void service_nm_rxq(struct sge_nm_rxq *);
1224 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
1225 struct sysctl_oid *);
1226 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
1227 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
1228 struct sysctl_oid *);
1229 int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
1230 #endif
1231
1232 /* t4_sge.c */
1233 void t4_sge_modload(void);
1234 void t4_sge_modunload(void);
1235 uint64_t t4_sge_extfree_refs(void);
1236 void t4_tweak_chip_settings(struct adapter *);
1237 int t4_read_chip_settings(struct adapter *);
1238 int t4_create_dma_tag(struct adapter *);
1239 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1240 struct sysctl_oid_list *);
1241 int t4_destroy_dma_tag(struct adapter *);
1242 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
1243 bus_addr_t *, void **);
1244 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
1245 void *);
1246 int sysctl_uint16(SYSCTL_HANDLER_ARGS);
1247 int t4_setup_adapter_queues(struct adapter *);
1248 int t4_teardown_adapter_queues(struct adapter *);
1249 int t4_setup_vi_queues(struct vi_info *);
1250 int t4_teardown_vi_queues(struct vi_info *);
1251 void t4_intr_all(void *);
1252 void t4_intr(void *);
1253 #ifdef DEV_NETMAP
1254 void t4_nm_intr(void *);
1255 void t4_vi_intr(void *);
1256 #endif
1257 void t4_intr_err(void *);
1258 void t4_intr_evt(void *);
1259 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1260 void t4_update_fl_bufsize(struct ifnet *);
1261 struct mbuf *alloc_wr_mbuf(int, int);
1262 int parse_pkt(struct mbuf **, bool);
1263 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1264 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1265 int tnl_cong(struct port_info *, int);
1266 void t4_register_an_handler(an_handler_t);
1267 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1268 void t4_register_cpl_handler(int, cpl_handler_t);
1269 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1270 #ifdef RATELIMIT
1271 int ethofld_transmit(struct ifnet *, struct mbuf *);
1272 void send_etid_flush_wr(struct cxgbe_snd_tag *);
1273 #endif
1274
1275 /* t4_tracer.c */
1276 struct t4_tracer;
1277 void t4_tracer_modload(void);
1278 void t4_tracer_modunload(void);
1279 void t4_tracer_port_detach(struct adapter *);
1280 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1281 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1282 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1283 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1284
1285 /* t4_sched.c */
1286 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1287 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1288 int t4_init_tx_sched(struct adapter *);
1289 int t4_free_tx_sched(struct adapter *);
1290 void t4_update_tx_sched(struct adapter *);
1291 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1292 void t4_release_cl_rl(struct adapter *, int, int);
1293 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1294 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1295 #ifdef RATELIMIT
1296 void t4_init_etid_table(struct adapter *);
1297 void t4_free_etid_table(struct adapter *);
1298 struct cxgbe_snd_tag *lookup_etid(struct adapter *, int);
1299 int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1300 struct m_snd_tag **);
1301 int cxgbe_snd_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *);
1302 int cxgbe_snd_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *);
1303 void cxgbe_snd_tag_free(struct m_snd_tag *);
1304 void cxgbe_snd_tag_free_locked(struct cxgbe_snd_tag *);
1305 #endif
1306
1307 /* t4_filter.c */
1308 int get_filter_mode(struct adapter *, uint32_t *);
1309 int set_filter_mode(struct adapter *, uint32_t);
1310 int get_filter(struct adapter *, struct t4_filter *);
1311 int set_filter(struct adapter *, struct t4_filter *);
1312 int del_filter(struct adapter *, struct t4_filter *);
1313 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1314 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1315 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1316 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1317 void free_hftid_hash(struct tid_info *);
1318
1319 static inline struct wrqe *
alloc_wrqe(int wr_len,struct sge_wrq * wrq)1320 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1321 {
1322 int len = offsetof(struct wrqe, wr) + wr_len;
1323 struct wrqe *wr;
1324
1325 wr = malloc(len, M_CXGBE, M_NOWAIT);
1326 if (__predict_false(wr == NULL))
1327 return (NULL);
1328 wr->wr_len = wr_len;
1329 wr->wrq = wrq;
1330 return (wr);
1331 }
1332
1333 static inline void *
wrtod(struct wrqe * wr)1334 wrtod(struct wrqe *wr)
1335 {
1336 return (&wr->wr[0]);
1337 }
1338
1339 static inline void
free_wrqe(struct wrqe * wr)1340 free_wrqe(struct wrqe *wr)
1341 {
1342 free(wr, M_CXGBE);
1343 }
1344
1345 static inline void
t4_wrq_tx(struct adapter * sc,struct wrqe * wr)1346 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1347 {
1348 struct sge_wrq *wrq = wr->wrq;
1349
1350 TXQ_LOCK(wrq);
1351 t4_wrq_tx_locked(sc, wrq, wr);
1352 TXQ_UNLOCK(wrq);
1353 }
1354
1355 static inline int
read_via_memwin(struct adapter * sc,int idx,uint32_t addr,uint32_t * val,int len)1356 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1357 int len)
1358 {
1359
1360 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1361 }
1362
1363 static inline int
write_via_memwin(struct adapter * sc,int idx,uint32_t addr,const uint32_t * val,int len)1364 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1365 const uint32_t *val, int len)
1366 {
1367
1368 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
1369 }
1370
1371 /* Number of len16 -> number of descriptors */
1372 static inline int
tx_len16_to_desc(int len16)1373 tx_len16_to_desc(int len16)
1374 {
1375
1376 return (howmany(len16, EQ_ESIZE / 16));
1377 }
1378 #endif
1379