1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2017 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * This software was developed by Landon Fuller under sponsorship from
8 * the FreeBSD Foundation.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: stable/12/sys/dev/bhnd/cores/chipc/chipc_gpio.c 326695 2017-12-08 15:57:29Z pfg $
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: stable/12/sys/dev/bhnd/cores/chipc/chipc_gpio.c 326695 2017-12-08 15:57:29Z pfg $");
36
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/bus.h>
40 #include <sys/gpio.h>
41 #include <sys/limits.h>
42 #include <sys/module.h>
43
44 #include <machine/_inttypes.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <machine/resource.h>
48
49 #include <dev/bhnd/bhnd.h>
50 #include <dev/gpio/gpiobusvar.h>
51
52 #include "gpio_if.h"
53
54 #include "bhnd_nvram_map.h"
55
56 #include "chipcreg.h"
57 #include "chipc_gpiovar.h"
58
59 /*
60 * ChipCommon GPIO driver
61 */
62
63 static int chipc_gpio_check_flags(
64 struct chipc_gpio_softc *sc,
65 uint32_t pin_num, uint32_t flags,
66 chipc_gpio_pin_mode *mode);
67 static int chipc_gpio_pin_update(
68 struct chipc_gpio_softc *sc,
69 struct chipc_gpio_update *update,
70 uint32_t pin_num, uint32_t flags);
71 static int chipc_gpio_commit_update(
72 struct chipc_gpio_softc *sc,
73 struct chipc_gpio_update *update);
74 static chipc_gpio_pin_mode chipc_gpio_pin_get_mode(
75 struct chipc_gpio_softc *sc,
76 uint32_t pin_num);
77
78
79 /* Debugging flags */
80 static u_long chipc_gpio_debug = 0;
81 TUNABLE_ULONG("hw.bhnd_chipc.gpio_debug", &chipc_gpio_debug);
82
83 enum {
84 /** Allow userspace GPIO access on bridged network (e.g. wi-fi)
85 * adapters */
86 CC_GPIO_DEBUG_ADAPTER_GPIOC = 1 << 0,
87 };
88
89 #define CC_GPIO_DEBUG(_type) (CC_GPIO_DEBUG_ ## _type & chipc_gpio_debug)
90
91 static struct bhnd_device_quirk chipc_gpio_quirks[];
92
93 /* Supported parent core device identifiers */
94 static const struct bhnd_device chipc_gpio_devices[] = {
95 BHND_DEVICE(BCM, CC, "Broadcom ChipCommon GPIO", chipc_gpio_quirks),
96 BHND_DEVICE_END
97 };
98
99 /* Device quirks table */
100 static struct bhnd_device_quirk chipc_gpio_quirks[] = {
101 BHND_CORE_QUIRK (HWREV_LTE(10), CC_GPIO_QUIRK_NO_EVENTS),
102 BHND_CORE_QUIRK (HWREV_LTE(15), CC_GPIO_QUIRK_NO_DCTIMER),
103 BHND_CORE_QUIRK (HWREV_LTE(19), CC_GPIO_QUIRK_NO_PULLUPDOWN),
104
105 BHND_DEVICE_QUIRK_END
106 };
107
108 static int
chipc_gpio_probe(device_t dev)109 chipc_gpio_probe(device_t dev)
110 {
111 const struct bhnd_device *id;
112 device_t chipc;
113
114 /* Look for compatible chipc parent */
115 chipc = device_get_parent(dev);
116 id = bhnd_device_lookup(chipc, chipc_gpio_devices,
117 sizeof(chipc_gpio_devices[0]));
118 if (id == NULL)
119 return (ENXIO);
120
121 device_set_desc(dev, id->desc);
122 return (BUS_PROBE_NOWILDCARD);
123 }
124
125 static int
chipc_gpio_attach(device_t dev)126 chipc_gpio_attach(device_t dev)
127 {
128 struct chipc_gpio_softc *sc;
129 device_t chipc;
130 int error;
131
132 chipc = device_get_parent(dev);
133
134 sc = device_get_softc(dev);
135 sc->dev = dev;
136 sc->quirks = bhnd_device_quirks(chipc, chipc_gpio_devices,
137 sizeof(chipc_gpio_devices[0]));
138
139 /* If this is a bridged wi-fi adapter, we don't want to support
140 * userspace requests via gpioc(4) */
141 if (bhnd_get_attach_type(chipc) == BHND_ATTACH_ADAPTER) {
142 if (!CC_GPIO_DEBUG(ADAPTER_GPIOC))
143 sc->quirks |= CC_GPIO_QUIRK_NO_GPIOC;
144 }
145
146 CC_GPIO_LOCK_INIT(sc);
147
148 sc->mem_rid = 0;
149 sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
150 RF_ACTIVE|RF_SHAREABLE);
151 if (sc->mem_res == NULL) {
152 device_printf(dev, "failed to allocate chipcommon registers\n");
153 error = ENXIO;
154 goto failed;
155 }
156
157 /*
158 * If hardware 'pulsate' support is available, set the timer duty-cycle
159 * to either the NVRAM 'leddc' value if available, or the default duty
160 * cycle.
161 */
162 if (!CC_GPIO_QUIRK(sc, NO_DCTIMER)) {
163 uint32_t dctimerval;
164
165 error = bhnd_nvram_getvar_uint32(chipc, BHND_NVAR_LEDDC,
166 &dctimerval);
167 if (error == ENOENT) {
168 /* Fall back on default duty cycle */
169 dctimerval = CHIPC_GPIOTIMERVAL_DEFAULT;
170 } else if (error) {
171 device_printf(dev, "error reading %s from NVRAM: %d\n",
172 BHND_NVAR_LEDDC, error);
173 goto failed;
174 }
175
176 CC_GPIO_WR4(sc, CHIPC_GPIOTIMERVAL, dctimerval);
177 }
178
179 /* Attach gpioc/gpiobus */
180 if (CC_GPIO_QUIRK(sc, NO_GPIOC)) {
181 sc->gpiobus = NULL;
182 } else {
183 if ((sc->gpiobus = gpiobus_attach_bus(dev)) == NULL) {
184 device_printf(dev, "failed to attach gpiobus\n");
185 error = ENXIO;
186 goto failed;
187 }
188 }
189
190 /* Register as the bus GPIO provider */
191 if ((error = bhnd_register_provider(dev, BHND_SERVICE_GPIO))) {
192 device_printf(dev, "failed to register gpio with bus: %d\n",
193 error);
194 goto failed;
195 }
196
197 return (0);
198
199 failed:
200 device_delete_children(dev);
201
202 if (sc->mem_res != NULL) {
203 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
204 sc->mem_res);
205 }
206
207 CC_GPIO_LOCK_DESTROY(sc);
208
209 return (error);
210 }
211
212 static int
chipc_gpio_detach(device_t dev)213 chipc_gpio_detach(device_t dev)
214 {
215 struct chipc_gpio_softc *sc;
216 int error;
217
218 sc = device_get_softc(dev);
219
220 if ((error = bus_generic_detach(dev)))
221 return (error);
222
223 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY)))
224 return (error);
225
226 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
227 CC_GPIO_LOCK_DESTROY(sc);
228
229 return (0);
230 }
231
232 static device_t
chipc_gpio_get_bus(device_t dev)233 chipc_gpio_get_bus(device_t dev)
234 {
235 struct chipc_gpio_softc *sc = device_get_softc(dev);
236
237 return (sc->gpiobus);
238 }
239
240 static int
chipc_gpio_pin_max(device_t dev,int * maxpin)241 chipc_gpio_pin_max(device_t dev, int *maxpin)
242 {
243 *maxpin = CC_GPIO_NPINS-1;
244 return (0);
245 }
246
247 static int
chipc_gpio_pin_set(device_t dev,uint32_t pin_num,uint32_t pin_value)248 chipc_gpio_pin_set(device_t dev, uint32_t pin_num, uint32_t pin_value)
249 {
250 struct chipc_gpio_softc *sc;
251 bool pin_high;
252 int error;
253
254 sc = device_get_softc(dev);
255 error = 0;
256
257 if (!CC_GPIO_VALID_PIN(pin_num))
258 return (EINVAL);
259
260 switch (pin_value) {
261 case GPIO_PIN_HIGH:
262 pin_high = true;
263 break;
264 case GPIO_PIN_LOW:
265 pin_high = false;
266 break;
267 default:
268 return (EINVAL);
269 }
270
271 CC_GPIO_LOCK(sc);
272
273 switch (chipc_gpio_pin_get_mode(sc, pin_num)) {
274 case CC_GPIO_PIN_INPUT:
275 case CC_GPIO_PIN_TRISTATE:
276 error = ENODEV;
277 break;
278
279 case CC_GPIO_PIN_OUTPUT:
280 CC_GPIO_WRFLAG(sc, pin_num, GPIOOUT, pin_high);
281 break;
282 }
283
284 CC_GPIO_UNLOCK(sc);
285
286 return (error);
287 }
288
289 static int
chipc_gpio_pin_get(device_t dev,uint32_t pin_num,uint32_t * pin_value)290 chipc_gpio_pin_get(device_t dev, uint32_t pin_num, uint32_t *pin_value)
291 {
292 struct chipc_gpio_softc *sc;
293 bool pin_high;
294
295 if (!CC_GPIO_VALID_PIN(pin_num))
296 return (EINVAL);
297
298 sc = device_get_softc(dev);
299 pin_high = false;
300
301 CC_GPIO_LOCK(sc);
302
303 switch (chipc_gpio_pin_get_mode(sc, pin_num)) {
304 case CC_GPIO_PIN_INPUT:
305 pin_high = CC_GPIO_RDFLAG(sc, pin_num, GPIOIN);
306 break;
307
308 case CC_GPIO_PIN_OUTPUT:
309 pin_high = CC_GPIO_RDFLAG(sc, pin_num, GPIOOUT);
310 break;
311
312 case CC_GPIO_PIN_TRISTATE:
313 pin_high = false;
314 break;
315 }
316
317 CC_GPIO_UNLOCK(sc);
318
319 *pin_value = pin_high ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
320
321 return (0);
322 }
323
324 static int
chipc_gpio_pin_toggle(device_t dev,uint32_t pin_num)325 chipc_gpio_pin_toggle(device_t dev, uint32_t pin_num)
326 {
327 struct chipc_gpio_softc *sc;
328 bool pin_high;
329 int error;
330
331 if (!CC_GPIO_VALID_PIN(pin_num))
332 return (EINVAL);
333
334 sc = device_get_softc(dev);
335 error = 0;
336
337 CC_GPIO_LOCK(sc);
338
339 switch (chipc_gpio_pin_get_mode(sc, pin_num)) {
340 case CC_GPIO_PIN_INPUT:
341 case CC_GPIO_PIN_TRISTATE:
342 error = ENODEV;
343 break;
344
345 case CC_GPIO_PIN_OUTPUT:
346 pin_high = CC_GPIO_RDFLAG(sc, pin_num, GPIOOUT);
347 CC_GPIO_WRFLAG(sc, pin_num, GPIOOUT, !pin_high);
348 break;
349 }
350
351 CC_GPIO_UNLOCK(sc);
352
353 return (error);
354 }
355
356 static int
chipc_gpio_pin_getcaps(device_t dev,uint32_t pin_num,uint32_t * caps)357 chipc_gpio_pin_getcaps(device_t dev, uint32_t pin_num, uint32_t *caps)
358 {
359 struct chipc_gpio_softc *sc = device_get_softc(dev);
360
361 if (!CC_GPIO_VALID_PIN(pin_num))
362 return (EINVAL);
363
364 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
365
366 if (!CC_GPIO_QUIRK(sc, NO_PULLUPDOWN))
367 *caps |= (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN);
368
369 if (!CC_GPIO_QUIRK(sc, NO_DCTIMER))
370 *caps |= GPIO_PIN_PULSATE;
371
372 return (0);
373 }
374
375 static int
chipc_gpio_pin_getflags(device_t dev,uint32_t pin_num,uint32_t * flags)376 chipc_gpio_pin_getflags(device_t dev, uint32_t pin_num, uint32_t *flags)
377 {
378 struct chipc_gpio_softc *sc = device_get_softc(dev);
379
380 if (!CC_GPIO_VALID_PIN(pin_num))
381 return (EINVAL);
382
383 CC_GPIO_LOCK(sc);
384
385 switch (chipc_gpio_pin_get_mode(sc, pin_num)) {
386 case CC_GPIO_PIN_INPUT:
387 *flags = GPIO_PIN_INPUT;
388
389 if (!CC_GPIO_QUIRK(sc, NO_PULLUPDOWN)) {
390 if (CC_GPIO_RDFLAG(sc, pin_num, GPIOPU)) {
391 *flags |= GPIO_PIN_PULLUP;
392 } else if (CC_GPIO_RDFLAG(sc, pin_num, GPIOPD)) {
393 *flags |= GPIO_PIN_PULLDOWN;
394 }
395 }
396 break;
397
398 case CC_GPIO_PIN_OUTPUT:
399 *flags = GPIO_PIN_OUTPUT;
400
401 if (!CC_GPIO_QUIRK(sc, NO_DCTIMER)) {
402 if (CC_GPIO_RDFLAG(sc, pin_num, GPIOTIMEROUTMASK))
403 *flags |= GPIO_PIN_PULSATE;
404 }
405
406 break;
407
408 case CC_GPIO_PIN_TRISTATE:
409 *flags = GPIO_PIN_TRISTATE|GPIO_PIN_OUTPUT;
410 break;
411 }
412
413 CC_GPIO_UNLOCK(sc);
414
415 return (0);
416 }
417
418 static int
chipc_gpio_pin_getname(device_t dev,uint32_t pin_num,char * name)419 chipc_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name)
420 {
421 int ret;
422
423 if (!CC_GPIO_VALID_PIN(pin_num))
424 return (EINVAL);
425
426 ret = snprintf(name, GPIOMAXNAME, "bhnd_gpio%02" PRIu32, pin_num);
427
428 if (ret < 0)
429 return (ENXIO);
430
431 if (ret >= GPIOMAXNAME)
432 return (ENOMEM);
433
434 return (0);
435 }
436
437 static int
chipc_gpio_pin_setflags(device_t dev,uint32_t pin_num,uint32_t flags)438 chipc_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
439 {
440 struct chipc_gpio_softc *sc;
441 struct chipc_gpio_update upd;
442 int error;
443
444 sc = device_get_softc(dev);
445
446 if (!CC_GPIO_VALID_PIN(pin_num))
447 return (EINVAL);
448
449 /* Produce an update descriptor */
450 memset(&upd, 0, sizeof(upd));
451 if ((error = chipc_gpio_pin_update(sc, &upd, pin_num, flags)))
452 return (error);
453
454 /* Commit the update */
455 CC_GPIO_LOCK(sc);
456 error = chipc_gpio_commit_update(sc, &upd);
457 CC_GPIO_UNLOCK(sc);
458
459 return (error);
460 }
461
462 static int
chipc_gpio_pin_access_32(device_t dev,uint32_t first_pin,uint32_t clear_pins,uint32_t change_pins,uint32_t * orig_pins)463 chipc_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
464 uint32_t change_pins, uint32_t *orig_pins)
465 {
466 struct chipc_gpio_softc *sc;
467 struct chipc_gpio_update upd;
468 uint32_t out, outen, ctrl;
469 uint32_t num_pins;
470 int error;
471
472 sc = device_get_softc(dev);
473
474 if (first_pin >= CC_GPIO_NPINS)
475 return (EINVAL);
476
477 /* Determine the actual number of referenced pins */
478 if (clear_pins == 0 && change_pins == 0) {
479 num_pins = CC_GPIO_NPINS - first_pin;
480 } else {
481 int num_clear_pins, num_change_pins;
482
483 num_clear_pins = flsl((u_long)clear_pins);
484 num_change_pins = flsl((u_long)change_pins);
485 num_pins = MAX(num_clear_pins, num_change_pins);
486 }
487
488 /* Validate the full pin range */
489 if (!CC_GPIO_VALID_PINS(first_pin, num_pins))
490 return (EINVAL);
491
492 /* Produce an update descriptor for all pins, relative to the current
493 * pin state */
494 CC_GPIO_LOCK(sc);
495 memset(&upd, 0, sizeof(upd));
496
497 out = CC_GPIO_RD4(sc, CHIPC_GPIOOUT);
498 outen = CC_GPIO_RD4(sc, CHIPC_GPIOOUTEN);
499 ctrl = CC_GPIO_RD4(sc, CHIPC_GPIOCTRL);
500
501 for (uint32_t i = 0; i < num_pins; i++) {
502 uint32_t pin;
503 bool pin_high;
504
505 pin = first_pin + i;
506
507 /* The pin must be configured for output */
508 if ((outen & (1 << pin)) == 0) {
509 CC_GPIO_UNLOCK(sc);
510 return (EINVAL);
511 }
512
513 /* The pin must not tristated */
514 if ((ctrl & (1 << pin)) != 0) {
515 CC_GPIO_UNLOCK(sc);
516 return (EINVAL);
517 }
518
519 /* Fetch current state */
520 if (out & (1 << pin)) {
521 pin_high = true;
522 } else {
523 pin_high = false;
524 }
525
526 /* Apply clear/toggle request */
527 if (clear_pins & (1 << pin))
528 pin_high = false;
529
530 if (change_pins & (1 << pin))
531 pin_high = !pin_high;
532
533 /* Add to our update descriptor */
534 CC_GPIO_UPDATE(&upd, pin, out, pin_high);
535 }
536
537 /* Commit the update */
538 error = chipc_gpio_commit_update(sc, &upd);
539 CC_GPIO_UNLOCK(sc);
540
541 return (error);
542 }
543
544 static int
chipc_gpio_pin_config_32(device_t dev,uint32_t first_pin,uint32_t num_pins,uint32_t * pin_flags)545 chipc_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
546 uint32_t *pin_flags)
547 {
548 struct chipc_gpio_softc *sc;
549 struct chipc_gpio_update upd;
550 int error;
551
552 sc = device_get_softc(dev);
553
554 if (!CC_GPIO_VALID_PINS(first_pin, num_pins))
555 return (EINVAL);
556
557 /* Produce an update descriptor */
558 memset(&upd, 0, sizeof(upd));
559 for (uint32_t i = 0; i < num_pins; i++) {
560 uint32_t pin, flags;
561
562 pin = first_pin + i;
563 flags = pin_flags[i];
564
565 /* As per the gpio_config_32 API documentation, any pins for
566 * which neither GPIO_PIN_OUTPUT or GPIO_PIN_INPUT are set
567 * should be ignored and left unmodified */
568 if ((flags & (GPIO_PIN_OUTPUT|GPIO_PIN_INPUT)) == 0)
569 continue;
570
571 if ((error = chipc_gpio_pin_update(sc, &upd, pin, flags)))
572 return (error);
573 }
574
575 /* Commit the update */
576 CC_GPIO_LOCK(sc);
577 error = chipc_gpio_commit_update(sc, &upd);
578 CC_GPIO_UNLOCK(sc);
579
580 return (error);
581 }
582
583
584 /**
585 * Commit a single @p reg register update.
586 */
587 static void
chipc_gpio_commit_reg(struct chipc_gpio_softc * sc,bus_size_t offset,struct chipc_gpio_reg * reg)588 chipc_gpio_commit_reg(struct chipc_gpio_softc *sc, bus_size_t offset,
589 struct chipc_gpio_reg *reg)
590 {
591 uint32_t value;
592
593 CC_GPIO_LOCK_ASSERT(sc, MA_OWNED);
594
595 if (reg->mask == 0)
596 return;
597
598 value = bhnd_bus_read_4(sc->mem_res, offset);
599 value &= ~reg->mask;
600 value |= reg->value;
601
602 bhnd_bus_write_4(sc->mem_res, offset, value);
603 }
604
605 /**
606 * Commit the set of GPIO register updates described by @p update.
607 */
608 static int
chipc_gpio_commit_update(struct chipc_gpio_softc * sc,struct chipc_gpio_update * update)609 chipc_gpio_commit_update(struct chipc_gpio_softc *sc,
610 struct chipc_gpio_update *update)
611 {
612 CC_GPIO_LOCK_ASSERT(sc, MA_OWNED);
613
614 /* Commit pulldown/pullup before potentially disabling an output pin */
615 chipc_gpio_commit_reg(sc, CHIPC_GPIOPD, &update->pulldown);
616 chipc_gpio_commit_reg(sc, CHIPC_GPIOPU, &update->pullup);
617
618 /* Commit output settings before potentially enabling an output pin */
619 chipc_gpio_commit_reg(sc, CHIPC_GPIOTIMEROUTMASK,
620 &update->timeroutmask);
621 chipc_gpio_commit_reg(sc, CHIPC_GPIOOUT, &update->out);
622
623 /* Commit input/output/tristate modes */
624 chipc_gpio_commit_reg(sc, CHIPC_GPIOOUTEN, &update->outen);
625 chipc_gpio_commit_reg(sc, CHIPC_GPIOCTRL, &update->ctrl);
626
627 return (0);
628 }
629
630 /**
631 * Apply the changes described by @p flags for @p pin_num to the given @p update
632 * descriptor.
633 */
634 static int
chipc_gpio_pin_update(struct chipc_gpio_softc * sc,struct chipc_gpio_update * update,uint32_t pin_num,uint32_t flags)635 chipc_gpio_pin_update(struct chipc_gpio_softc *sc,
636 struct chipc_gpio_update *update, uint32_t pin_num, uint32_t flags)
637 {
638 chipc_gpio_pin_mode mode;
639 int error;
640
641 if (!CC_GPIO_VALID_PIN(pin_num))
642 return (EINVAL);
643
644 /* Verify flag compatibility and determine the pin mode */
645 if ((error = chipc_gpio_check_flags(sc, pin_num, flags, &mode)))
646 return (error);
647
648 /* Apply the mode-specific changes */
649 switch (mode) {
650 case CC_GPIO_PIN_INPUT:
651 CC_GPIO_UPDATE(update, pin_num, pullup, false);
652 CC_GPIO_UPDATE(update, pin_num, pulldown, false);
653 CC_GPIO_UPDATE(update, pin_num, out, false);
654 CC_GPIO_UPDATE(update, pin_num, outen, false);
655 CC_GPIO_UPDATE(update, pin_num, timeroutmask, false);
656 CC_GPIO_UPDATE(update, pin_num, ctrl, false);
657
658 if (flags & GPIO_PIN_PULLUP) {
659 CC_GPIO_UPDATE(update, pin_num, pullup, true);
660 } else if (flags & GPIO_PIN_PULLDOWN) {
661 CC_GPIO_UPDATE(update, pin_num, pulldown, true);
662 }
663
664 return (0);
665
666 case CC_GPIO_PIN_OUTPUT:
667 CC_GPIO_UPDATE(update, pin_num, pullup, false);
668 CC_GPIO_UPDATE(update, pin_num, pulldown, false);
669 CC_GPIO_UPDATE(update, pin_num, outen, true);
670 CC_GPIO_UPDATE(update, pin_num, timeroutmask, false);
671 CC_GPIO_UPDATE(update, pin_num, ctrl, false);
672
673 if (flags & GPIO_PIN_PRESET_HIGH) {
674 CC_GPIO_UPDATE(update, pin_num, out, true);
675 } else if (flags & GPIO_PIN_PRESET_LOW) {
676 CC_GPIO_UPDATE(update, pin_num, out, false);
677 }
678
679 if (flags & GPIO_PIN_PULSATE)
680 CC_GPIO_UPDATE(update, pin_num, timeroutmask, true);
681
682 return (0);
683
684 case CC_GPIO_PIN_TRISTATE:
685 CC_GPIO_UPDATE(update, pin_num, pullup, false);
686 CC_GPIO_UPDATE(update, pin_num, pulldown, false);
687 CC_GPIO_UPDATE(update, pin_num, out, false);
688 CC_GPIO_UPDATE(update, pin_num, outen, false);
689 CC_GPIO_UPDATE(update, pin_num, timeroutmask, false);
690 CC_GPIO_UPDATE(update, pin_num, ctrl, true);
691
692 if (flags & GPIO_PIN_OUTPUT)
693 CC_GPIO_UPDATE(update, pin_num, outen, true);
694
695 return (0);
696 }
697
698 device_printf(sc->dev, "unknown pin mode %d\n", mode);
699 return (EINVAL);
700 }
701
702 /**
703 * Verify that @p flags are valid for use with @p pin_num, and on success,
704 * return the pin mode described by @p flags in @p mode.
705 *
706 * @param sc GPIO driver instance state.
707 * @param pin_num The pin number to configure.
708 * @param flags The pin flags to be validated.
709 * @param[out] mode On success, will be populated with the GPIO pin mode
710 * defined by @p flags.
711 *
712 * @retval 0 success
713 * @retval EINVAL if @p flags are invalid.
714 */
715 static int
chipc_gpio_check_flags(struct chipc_gpio_softc * sc,uint32_t pin_num,uint32_t flags,chipc_gpio_pin_mode * mode)716 chipc_gpio_check_flags(struct chipc_gpio_softc *sc, uint32_t pin_num,
717 uint32_t flags, chipc_gpio_pin_mode *mode)
718 {
719 uint32_t mode_flag, input_flag, output_flag;
720
721 CC_GPIO_ASSERT_VALID_PIN(sc, pin_num);
722
723 mode_flag = flags & (GPIO_PIN_OUTPUT | GPIO_PIN_INPUT |
724 GPIO_PIN_TRISTATE);
725 output_flag = flags & (GPIO_PIN_PRESET_HIGH | GPIO_PIN_PRESET_LOW
726 | GPIO_PIN_PULSATE);
727 input_flag = flags & (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN);
728
729 switch (mode_flag) {
730 case GPIO_PIN_OUTPUT:
731 /* No input flag(s) should be set */
732 if (input_flag != 0)
733 return (EINVAL);
734
735 /* Validate our output flag(s) */
736 switch (output_flag) {
737 case GPIO_PIN_PRESET_HIGH:
738 case GPIO_PIN_PRESET_LOW:
739 case (GPIO_PIN_PRESET_HIGH|GPIO_PIN_PULSATE):
740 case (GPIO_PIN_PRESET_LOW|GPIO_PIN_PULSATE):
741 case 0:
742 /* Check for unhandled flags */
743 if ((flags & ~(mode_flag | output_flag)) != 0)
744 return (EINVAL);
745
746 *mode = CC_GPIO_PIN_OUTPUT;
747 return (0);
748
749 default:
750 /* Incompatible output flags */
751 return (EINVAL);
752 }
753
754 case GPIO_PIN_INPUT:
755 /* No output flag(s) should be set */
756 if (output_flag != 0)
757 return (EINVAL);
758
759 /* Validate our input flag(s) */
760 switch (input_flag) {
761 case GPIO_PIN_PULLUP:
762 case GPIO_PIN_PULLDOWN:
763 case 0:
764 /* Check for unhandled flags */
765 if ((flags & ~(mode_flag | input_flag)) != 0)
766 return (EINVAL);
767
768 *mode = CC_GPIO_PIN_INPUT;
769 return (0);
770
771 default:
772 /* Incompatible input flags */
773 return (EINVAL);
774 }
775
776 break;
777
778 case (GPIO_PIN_TRISTATE|GPIO_PIN_OUTPUT):
779 case GPIO_PIN_TRISTATE:
780 /* No input or output flag(s) should be set */
781 if (input_flag != 0 || output_flag != 0)
782 return (EINVAL);
783
784 /* Check for unhandled flags */
785 if ((flags & ~mode_flag) != 0)
786 return (EINVAL);
787
788 *mode = CC_GPIO_PIN_TRISTATE;
789 return (0);
790
791 default:
792 /* Incompatible mode flags */
793 return (EINVAL);
794 }
795 }
796
797 /**
798 * Return the current pin mode for @p pin_num.
799 *
800 * @param sc GPIO driver instance state.
801 * @param pin_num The pin number to query.
802 */
803 static chipc_gpio_pin_mode
chipc_gpio_pin_get_mode(struct chipc_gpio_softc * sc,uint32_t pin_num)804 chipc_gpio_pin_get_mode(struct chipc_gpio_softc *sc, uint32_t pin_num)
805 {
806 CC_GPIO_LOCK_ASSERT(sc, MA_OWNED);
807 CC_GPIO_ASSERT_VALID_PIN(sc, pin_num);
808
809 if (CC_GPIO_RDFLAG(sc, pin_num, GPIOCTRL)) {
810 return (CC_GPIO_PIN_TRISTATE);
811 } else if (CC_GPIO_RDFLAG(sc, pin_num, GPIOOUTEN)) {
812 return (CC_GPIO_PIN_OUTPUT);
813 } else {
814 return (CC_GPIO_PIN_INPUT);
815 }
816 }
817
818 static device_method_t chipc_gpio_methods[] = {
819 /* Device interface */
820 DEVMETHOD(device_probe, chipc_gpio_probe),
821 DEVMETHOD(device_attach, chipc_gpio_attach),
822 DEVMETHOD(device_detach, chipc_gpio_detach),
823
824 /* GPIO interface */
825 DEVMETHOD(gpio_get_bus, chipc_gpio_get_bus),
826 DEVMETHOD(gpio_pin_max, chipc_gpio_pin_max),
827 DEVMETHOD(gpio_pin_getname, chipc_gpio_pin_getname),
828 DEVMETHOD(gpio_pin_getflags, chipc_gpio_pin_getflags),
829 DEVMETHOD(gpio_pin_getcaps, chipc_gpio_pin_getcaps),
830 DEVMETHOD(gpio_pin_setflags, chipc_gpio_pin_setflags),
831 DEVMETHOD(gpio_pin_get, chipc_gpio_pin_get),
832 DEVMETHOD(gpio_pin_set, chipc_gpio_pin_set),
833 DEVMETHOD(gpio_pin_toggle, chipc_gpio_pin_toggle),
834 DEVMETHOD(gpio_pin_access_32, chipc_gpio_pin_access_32),
835 DEVMETHOD(gpio_pin_config_32, chipc_gpio_pin_config_32),
836
837 DEVMETHOD_END
838 };
839
840 static devclass_t gpio_devclass;
841
842 DEFINE_CLASS_0(gpio, chipc_gpio_driver, chipc_gpio_methods, sizeof(struct chipc_gpio_softc));
843 EARLY_DRIVER_MODULE(chipc_gpio, bhnd_chipc, chipc_gpio_driver,
844 gpio_devclass, NULL, NULL, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
845
846 MODULE_DEPEND(chipc_gpio, bhnd, 1, 1, 1);
847 MODULE_DEPEND(chipc_gpio, gpiobus, 1, 1, 1);
848 MODULE_VERSION(chipc_gpio, 1);
849