1 /*
2 ********************************************************************************
3 ** OS : FreeBSD
4 ** FILE NAME : arcmsr.c
5 ** BY : Erich Chen, Ching Huang
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8 ** SATA/SAS RAID HOST Adapter
9 ********************************************************************************
10 ********************************************************************************
11 **
12 ** SPDX-License-Identifier: BSD-3-Clause
13 **
14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
15 **
16 ** Redistribution and use in source and binary forms, with or without
17 ** modification, are permitted provided that the following conditions
18 ** are met:
19 ** 1. Redistributions of source code must retain the above copyright
20 ** notice, this list of conditions and the following disclaimer.
21 ** 2. Redistributions in binary form must reproduce the above copyright
22 ** notice, this list of conditions and the following disclaimer in the
23 ** documentation and/or other materials provided with the distribution.
24 ** 3. The name of the author may not be used to endorse or promote products
25 ** derived from this software without specific prior written permission.
26 **
27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 ********************************************************************************
38 ** History
39 **
40 ** REV# DATE NAME DESCRIPTION
41 ** 1.00.00.00 03/31/2004 Erich Chen First release
42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error
43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support
44 ** clean unused function
45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling,
46 ** firmware version check
47 ** and firmware update notify for hardware bug fix
48 ** handling if none zero high part physical address
49 ** of srb resource
50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy
51 ** add iop message xfer
52 ** with scsi pass-through command
53 ** add new device id of sas raid adapters
54 ** code fit for SPARC64 & PPC
55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report
56 ** and cause g_vfs_done() read write error
57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x
58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x
59 ** bus_dmamem_alloc() with BUS_DMA_ZERO
60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880
61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
62 ** prevent cam_periph_error removing all LUN devices of one Target id
63 ** for any one LUN device failed
64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step"
65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function
68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout
69 ** 02/14/2011 Ching Huang Modified pktRequestCount
70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it
71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic
72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start
73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed
74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command
75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition
76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284
78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4
79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs
80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883
81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203
82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884
83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource
84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller
85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter
86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when
87 ** scatter-gather count large than some number
88 ** 1.50.00.03 05/04/2021 Ching Huang Fixed doorbell status arrived late on ARC-1886
89 ** 1.50.00.04 12/08/2021 Ching Huang Fixed boot up hung under ARC-1886 with no volume created
90 ******************************************************************************************
91 */
92
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD: stable/12/sys/dev/arcmsr/arcmsr.c 371454 2021-12-27 06:57:16Z git2svn $");
95
96 #if 0
97 #define ARCMSR_DEBUG1 1
98 #endif
99 #include <sys/param.h>
100 #include <sys/systm.h>
101 #include <sys/malloc.h>
102 #include <sys/kernel.h>
103 #include <sys/bus.h>
104 #include <sys/queue.h>
105 #include <sys/stat.h>
106 #include <sys/devicestat.h>
107 #include <sys/kthread.h>
108 #include <sys/module.h>
109 #include <sys/proc.h>
110 #include <sys/lock.h>
111 #include <sys/sysctl.h>
112 #include <sys/poll.h>
113 #include <sys/ioccom.h>
114 #include <vm/vm.h>
115 #include <vm/vm_param.h>
116 #include <vm/pmap.h>
117
118 #include <isa/rtc.h>
119
120 #include <machine/bus.h>
121 #include <machine/resource.h>
122 #include <machine/atomic.h>
123 #include <sys/conf.h>
124 #include <sys/rman.h>
125
126 #include <cam/cam.h>
127 #include <cam/cam_ccb.h>
128 #include <cam/cam_sim.h>
129 #include <cam/cam_periph.h>
130 #include <cam/cam_xpt_periph.h>
131 #include <cam/cam_xpt_sim.h>
132 #include <cam/cam_debug.h>
133 #include <cam/scsi/scsi_all.h>
134 #include <cam/scsi/scsi_message.h>
135 /*
136 **************************************************************************
137 **************************************************************************
138 */
139 #include <sys/selinfo.h>
140 #include <sys/mutex.h>
141 #include <sys/endian.h>
142 #include <dev/pci/pcivar.h>
143 #include <dev/pci/pcireg.h>
144
145 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1);
146
147 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.04 2021-12-08"
148 #include <dev/arcmsr/arcmsr.h>
149 /*
150 **************************************************************************
151 **************************************************************************
152 */
153 static void arcmsr_free_srb(struct CommandControlBlock *srb);
154 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
155 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
156 static int arcmsr_probe(device_t dev);
157 static int arcmsr_attach(device_t dev);
158 static int arcmsr_detach(device_t dev);
159 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
160 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
161 static int arcmsr_shutdown(device_t dev);
162 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
163 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
164 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
165 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
166 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
167 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
168 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
169 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
170 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
171 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
172 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
173 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
174 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
175 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
176 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
177 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
178 static int arcmsr_resume(device_t dev);
179 static int arcmsr_suspend(device_t dev);
180 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
181 static void arcmsr_polling_devmap(void *arg);
182 static void arcmsr_srb_timeout(void *arg);
183 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
184 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
185 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb);
186 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
187 #ifdef ARCMSR_DEBUG1
188 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
189 #endif
190 /*
191 **************************************************************************
192 **************************************************************************
193 */
UDELAY(u_int32_t us)194 static void UDELAY(u_int32_t us) { DELAY(us); }
195 /*
196 **************************************************************************
197 **************************************************************************
198 */
199 static bus_dmamap_callback_t arcmsr_map_free_srb;
200 static bus_dmamap_callback_t arcmsr_execute_srb;
201 /*
202 **************************************************************************
203 **************************************************************************
204 */
205 static d_open_t arcmsr_open;
206 static d_close_t arcmsr_close;
207 static d_ioctl_t arcmsr_ioctl;
208
209 static device_method_t arcmsr_methods[]={
210 DEVMETHOD(device_probe, arcmsr_probe),
211 DEVMETHOD(device_attach, arcmsr_attach),
212 DEVMETHOD(device_detach, arcmsr_detach),
213 DEVMETHOD(device_shutdown, arcmsr_shutdown),
214 DEVMETHOD(device_suspend, arcmsr_suspend),
215 DEVMETHOD(device_resume, arcmsr_resume),
216 DEVMETHOD_END
217 };
218
219 static driver_t arcmsr_driver={
220 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
221 };
222
223 static devclass_t arcmsr_devclass;
224 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
225 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
226 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
227 #ifndef BUS_DMA_COHERENT
228 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */
229 #endif
230 static struct cdevsw arcmsr_cdevsw={
231 .d_version = D_VERSION,
232 .d_open = arcmsr_open, /* open */
233 .d_close = arcmsr_close, /* close */
234 .d_ioctl = arcmsr_ioctl, /* ioctl */
235 .d_name = "arcmsr", /* name */
236 };
237 /*
238 **************************************************************************
239 **************************************************************************
240 */
arcmsr_open(struct cdev * dev,int flags,int fmt,struct thread * proc)241 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
242 {
243 int unit = dev2unit(dev);
244 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
245
246 if (acb == NULL) {
247 return ENXIO;
248 }
249 return (0);
250 }
251 /*
252 **************************************************************************
253 **************************************************************************
254 */
arcmsr_close(struct cdev * dev,int flags,int fmt,struct thread * proc)255 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
256 {
257 int unit = dev2unit(dev);
258 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
259
260 if (acb == NULL) {
261 return ENXIO;
262 }
263 return 0;
264 }
265 /*
266 **************************************************************************
267 **************************************************************************
268 */
arcmsr_ioctl(struct cdev * dev,u_long ioctl_cmd,caddr_t arg,int flags,struct thread * proc)269 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
270 {
271 int unit = dev2unit(dev);
272 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
273
274 if (acb == NULL) {
275 return ENXIO;
276 }
277 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
278 }
279 /*
280 **********************************************************************
281 **********************************************************************
282 */
arcmsr_disable_allintr(struct AdapterControlBlock * acb)283 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
284 {
285 u_int32_t intmask_org = 0;
286
287 switch (acb->adapter_type) {
288 case ACB_ADAPTER_TYPE_A: {
289 /* disable all outbound interrupt */
290 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
291 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
292 }
293 break;
294 case ACB_ADAPTER_TYPE_B: {
295 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
296 /* disable all outbound interrupt */
297 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
298 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
299 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
300 }
301 break;
302 case ACB_ADAPTER_TYPE_C: {
303 /* disable all outbound interrupt */
304 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
305 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
306 }
307 break;
308 case ACB_ADAPTER_TYPE_D: {
309 /* disable all outbound interrupt */
310 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */
311 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
312 }
313 break;
314 case ACB_ADAPTER_TYPE_E:
315 case ACB_ADAPTER_TYPE_F: {
316 /* disable all outbound interrupt */
317 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
318 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
319 }
320 break;
321 }
322 return (intmask_org);
323 }
324 /*
325 **********************************************************************
326 **********************************************************************
327 */
arcmsr_enable_allintr(struct AdapterControlBlock * acb,u_int32_t intmask_org)328 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
329 {
330 u_int32_t mask;
331
332 switch (acb->adapter_type) {
333 case ACB_ADAPTER_TYPE_A: {
334 /* enable outbound Post Queue, outbound doorbell Interrupt */
335 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
336 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
337 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
338 }
339 break;
340 case ACB_ADAPTER_TYPE_B: {
341 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
342 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
343 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
344 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
345 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
346 }
347 break;
348 case ACB_ADAPTER_TYPE_C: {
349 /* enable outbound Post Queue, outbound doorbell Interrupt */
350 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
351 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
352 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
353 }
354 break;
355 case ACB_ADAPTER_TYPE_D: {
356 /* enable outbound Post Queue, outbound doorbell Interrupt */
357 mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
358 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
359 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
360 acb->outbound_int_enable = mask;
361 }
362 break;
363 case ACB_ADAPTER_TYPE_E:
364 case ACB_ADAPTER_TYPE_F: {
365 /* enable outbound Post Queue, outbound doorbell Interrupt */
366 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
367 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
368 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
369 }
370 break;
371 }
372 }
373 /*
374 **********************************************************************
375 **********************************************************************
376 */
arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock * acb)377 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
378 {
379 u_int32_t Index;
380 u_int8_t Retries = 0x00;
381
382 do {
383 for(Index=0; Index < 100; Index++) {
384 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
385 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
386 return TRUE;
387 }
388 UDELAY(10000);
389 }/*max 1 seconds*/
390 }while(Retries++ < 20);/*max 20 sec*/
391 return (FALSE);
392 }
393 /*
394 **********************************************************************
395 **********************************************************************
396 */
arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock * acb)397 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
398 {
399 u_int32_t Index;
400 u_int8_t Retries = 0x00;
401 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
402
403 do {
404 for(Index=0; Index < 100; Index++) {
405 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
406 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
407 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
408 return TRUE;
409 }
410 UDELAY(10000);
411 }/*max 1 seconds*/
412 }while(Retries++ < 20);/*max 20 sec*/
413 return (FALSE);
414 }
415 /*
416 **********************************************************************
417 **********************************************************************
418 */
arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock * acb)419 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
420 {
421 u_int32_t Index;
422 u_int8_t Retries = 0x00;
423
424 do {
425 for(Index=0; Index < 100; Index++) {
426 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
427 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
428 return TRUE;
429 }
430 UDELAY(10000);
431 }/*max 1 seconds*/
432 }while(Retries++ < 20);/*max 20 sec*/
433 return (FALSE);
434 }
435 /*
436 **********************************************************************
437 **********************************************************************
438 */
arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock * acb)439 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
440 {
441 u_int32_t Index;
442 u_int8_t Retries = 0x00;
443
444 do {
445 for(Index=0; Index < 100; Index++) {
446 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
447 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
448 return TRUE;
449 }
450 UDELAY(10000);
451 }/*max 1 seconds*/
452 }while(Retries++ < 20);/*max 20 sec*/
453 return (FALSE);
454 }
455 /*
456 **********************************************************************
457 **********************************************************************
458 */
arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock * acb)459 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb)
460 {
461 u_int32_t Index, read_doorbell;
462 u_int8_t Retries = 0x00;
463
464 do {
465 for(Index=0; Index < 100; Index++) {
466 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
467 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
468 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/
469 acb->in_doorbell = read_doorbell;
470 return TRUE;
471 }
472 UDELAY(10000);
473 }/*max 1 seconds*/
474 }while(Retries++ < 20);/*max 20 sec*/
475 return (FALSE);
476 }
477 /*
478 ************************************************************************
479 ************************************************************************
480 */
arcmsr_flush_hba_cache(struct AdapterControlBlock * acb)481 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
482 {
483 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
484
485 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
486 do {
487 if(arcmsr_hba_wait_msgint_ready(acb)) {
488 break;
489 } else {
490 retry_count--;
491 }
492 }while(retry_count != 0);
493 }
494 /*
495 ************************************************************************
496 ************************************************************************
497 */
arcmsr_flush_hbb_cache(struct AdapterControlBlock * acb)498 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
499 {
500 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
501 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
502
503 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
504 do {
505 if(arcmsr_hbb_wait_msgint_ready(acb)) {
506 break;
507 } else {
508 retry_count--;
509 }
510 }while(retry_count != 0);
511 }
512 /*
513 ************************************************************************
514 ************************************************************************
515 */
arcmsr_flush_hbc_cache(struct AdapterControlBlock * acb)516 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
517 {
518 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
519
520 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
521 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
522 do {
523 if(arcmsr_hbc_wait_msgint_ready(acb)) {
524 break;
525 } else {
526 retry_count--;
527 }
528 }while(retry_count != 0);
529 }
530 /*
531 ************************************************************************
532 ************************************************************************
533 */
arcmsr_flush_hbd_cache(struct AdapterControlBlock * acb)534 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
535 {
536 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
537
538 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
539 do {
540 if(arcmsr_hbd_wait_msgint_ready(acb)) {
541 break;
542 } else {
543 retry_count--;
544 }
545 }while(retry_count != 0);
546 }
547 /*
548 ************************************************************************
549 ************************************************************************
550 */
arcmsr_flush_hbe_cache(struct AdapterControlBlock * acb)551 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb)
552 {
553 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
554
555 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
556 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
557 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
558 do {
559 if(arcmsr_hbe_wait_msgint_ready(acb)) {
560 break;
561 } else {
562 retry_count--;
563 }
564 }while(retry_count != 0);
565 }
566 /*
567 ************************************************************************
568 ************************************************************************
569 */
arcmsr_flush_adapter_cache(struct AdapterControlBlock * acb)570 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
571 {
572 switch (acb->adapter_type) {
573 case ACB_ADAPTER_TYPE_A: {
574 arcmsr_flush_hba_cache(acb);
575 }
576 break;
577 case ACB_ADAPTER_TYPE_B: {
578 arcmsr_flush_hbb_cache(acb);
579 }
580 break;
581 case ACB_ADAPTER_TYPE_C: {
582 arcmsr_flush_hbc_cache(acb);
583 }
584 break;
585 case ACB_ADAPTER_TYPE_D: {
586 arcmsr_flush_hbd_cache(acb);
587 }
588 break;
589 case ACB_ADAPTER_TYPE_E:
590 case ACB_ADAPTER_TYPE_F: {
591 arcmsr_flush_hbe_cache(acb);
592 }
593 break;
594 }
595 }
596 /*
597 *******************************************************************************
598 *******************************************************************************
599 */
arcmsr_suspend(device_t dev)600 static int arcmsr_suspend(device_t dev)
601 {
602 struct AdapterControlBlock *acb = device_get_softc(dev);
603
604 /* flush controller */
605 arcmsr_iop_parking(acb);
606 /* disable all outbound interrupt */
607 arcmsr_disable_allintr(acb);
608 return(0);
609 }
610 /*
611 *******************************************************************************
612 *******************************************************************************
613 */
arcmsr_resume(device_t dev)614 static int arcmsr_resume(device_t dev)
615 {
616 struct AdapterControlBlock *acb = device_get_softc(dev);
617
618 arcmsr_iop_init(acb);
619 return(0);
620 }
621 /*
622 *********************************************************************************
623 *********************************************************************************
624 */
arcmsr_async(void * cb_arg,u_int32_t code,struct cam_path * path,void * arg)625 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
626 {
627 struct AdapterControlBlock *acb;
628 u_int8_t target_id, target_lun;
629 struct cam_sim *sim;
630
631 sim = (struct cam_sim *) cb_arg;
632 acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
633 switch (code) {
634 case AC_LOST_DEVICE:
635 target_id = xpt_path_target_id(path);
636 target_lun = xpt_path_lun_id(path);
637 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
638 break;
639 }
640 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
641 break;
642 default:
643 break;
644 }
645 }
646 /*
647 **********************************************************************
648 **********************************************************************
649 */
arcmsr_report_sense_info(struct CommandControlBlock * srb)650 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
651 {
652 union ccb *pccb = srb->pccb;
653
654 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
655 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
656 if(pccb->csio.sense_len) {
657 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
658 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
659 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
660 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
661 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
662 }
663 }
664 /*
665 *********************************************************************
666 *********************************************************************
667 */
arcmsr_abort_hba_allcmd(struct AdapterControlBlock * acb)668 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
669 {
670 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
671 if(!arcmsr_hba_wait_msgint_ready(acb)) {
672 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
673 }
674 }
675 /*
676 *********************************************************************
677 *********************************************************************
678 */
arcmsr_abort_hbb_allcmd(struct AdapterControlBlock * acb)679 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
680 {
681 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
682 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
683 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
684 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
685 }
686 }
687 /*
688 *********************************************************************
689 *********************************************************************
690 */
arcmsr_abort_hbc_allcmd(struct AdapterControlBlock * acb)691 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
692 {
693 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
694 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
695 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
696 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
697 }
698 }
699 /*
700 *********************************************************************
701 *********************************************************************
702 */
arcmsr_abort_hbd_allcmd(struct AdapterControlBlock * acb)703 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
704 {
705 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
706 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
707 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
708 }
709 }
710 /*
711 *********************************************************************
712 *********************************************************************
713 */
arcmsr_abort_hbe_allcmd(struct AdapterControlBlock * acb)714 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb)
715 {
716 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
717 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
718 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
719 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
720 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
721 }
722 }
723 /*
724 *********************************************************************
725 *********************************************************************
726 */
arcmsr_abort_allcmd(struct AdapterControlBlock * acb)727 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
728 {
729 switch (acb->adapter_type) {
730 case ACB_ADAPTER_TYPE_A: {
731 arcmsr_abort_hba_allcmd(acb);
732 }
733 break;
734 case ACB_ADAPTER_TYPE_B: {
735 arcmsr_abort_hbb_allcmd(acb);
736 }
737 break;
738 case ACB_ADAPTER_TYPE_C: {
739 arcmsr_abort_hbc_allcmd(acb);
740 }
741 break;
742 case ACB_ADAPTER_TYPE_D: {
743 arcmsr_abort_hbd_allcmd(acb);
744 }
745 break;
746 case ACB_ADAPTER_TYPE_E:
747 case ACB_ADAPTER_TYPE_F: {
748 arcmsr_abort_hbe_allcmd(acb);
749 }
750 break;
751 }
752 }
753 /*
754 **********************************************************************
755 **********************************************************************
756 */
arcmsr_srb_complete(struct CommandControlBlock * srb,int stand_flag)757 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
758 {
759 struct AdapterControlBlock *acb = srb->acb;
760 union ccb *pccb = srb->pccb;
761
762 if(srb->srb_flags & SRB_FLAG_TIMER_START)
763 callout_stop(&srb->ccb_callout);
764 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
765 bus_dmasync_op_t op;
766
767 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
768 op = BUS_DMASYNC_POSTREAD;
769 } else {
770 op = BUS_DMASYNC_POSTWRITE;
771 }
772 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
773 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
774 }
775 if(stand_flag == 1) {
776 atomic_subtract_int(&acb->srboutstandingcount, 1);
777 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
778 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
779 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
780 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
781 }
782 }
783 if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
784 arcmsr_free_srb(srb);
785 acb->pktReturnCount++;
786 xpt_done(pccb);
787 }
788 /*
789 **************************************************************************
790 **************************************************************************
791 */
arcmsr_report_srb_state(struct AdapterControlBlock * acb,struct CommandControlBlock * srb,u_int16_t error)792 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
793 {
794 int target, lun;
795
796 target = srb->pccb->ccb_h.target_id;
797 lun = srb->pccb->ccb_h.target_lun;
798 if(error == FALSE) {
799 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
800 acb->devstate[target][lun] = ARECA_RAID_GOOD;
801 }
802 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
803 arcmsr_srb_complete(srb, 1);
804 } else {
805 switch(srb->arcmsr_cdb.DeviceStatus) {
806 case ARCMSR_DEV_SELECT_TIMEOUT: {
807 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
808 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
809 }
810 acb->devstate[target][lun] = ARECA_RAID_GONE;
811 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
812 arcmsr_srb_complete(srb, 1);
813 }
814 break;
815 case ARCMSR_DEV_ABORTED:
816 case ARCMSR_DEV_INIT_FAIL: {
817 acb->devstate[target][lun] = ARECA_RAID_GONE;
818 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
819 arcmsr_srb_complete(srb, 1);
820 }
821 break;
822 case SCSISTAT_CHECK_CONDITION: {
823 acb->devstate[target][lun] = ARECA_RAID_GOOD;
824 arcmsr_report_sense_info(srb);
825 arcmsr_srb_complete(srb, 1);
826 }
827 break;
828 default:
829 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
830 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
831 acb->devstate[target][lun] = ARECA_RAID_GONE;
832 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
833 /*unknown error or crc error just for retry*/
834 arcmsr_srb_complete(srb, 1);
835 break;
836 }
837 }
838 }
839 /*
840 **************************************************************************
841 **************************************************************************
842 */
arcmsr_drain_donequeue(struct AdapterControlBlock * acb,u_int32_t flag_srb,u_int16_t error)843 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
844 {
845 struct CommandControlBlock *srb;
846
847 /* check if command done with no error*/
848 switch (acb->adapter_type) {
849 case ACB_ADAPTER_TYPE_A:
850 case ACB_ADAPTER_TYPE_B:
851 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
852 break;
853 case ACB_ADAPTER_TYPE_C:
854 case ACB_ADAPTER_TYPE_D:
855 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
856 break;
857 case ACB_ADAPTER_TYPE_E:
858 case ACB_ADAPTER_TYPE_F:
859 srb = acb->psrb_pool[flag_srb];
860 break;
861 default:
862 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
863 break;
864 }
865 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
866 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
867 arcmsr_free_srb(srb);
868 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
869 return;
870 }
871 printf("arcmsr%d: return srb has been completed\n"
872 "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
873 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
874 return;
875 }
876 arcmsr_report_srb_state(acb, srb, error);
877 }
878 /*
879 **************************************************************************
880 **************************************************************************
881 */
arcmsr_srb_timeout(void * arg)882 static void arcmsr_srb_timeout(void *arg)
883 {
884 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
885 struct AdapterControlBlock *acb;
886 int target, lun;
887 u_int8_t cmd;
888
889 target = srb->pccb->ccb_h.target_id;
890 lun = srb->pccb->ccb_h.target_lun;
891 acb = srb->acb;
892 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
893 if(srb->srb_state == ARCMSR_SRB_START)
894 {
895 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0];
896 srb->srb_state = ARCMSR_SRB_TIMEOUT;
897 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
898 arcmsr_srb_complete(srb, 1);
899 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
900 acb->pci_unit, target, lun, cmd, srb);
901 }
902 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
903 #ifdef ARCMSR_DEBUG1
904 arcmsr_dump_data(acb);
905 #endif
906 }
907
908 /*
909 **********************************************************************
910 **********************************************************************
911 */
arcmsr_done4abort_postqueue(struct AdapterControlBlock * acb)912 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
913 {
914 int i=0;
915 u_int32_t flag_srb;
916 u_int16_t error;
917
918 switch (acb->adapter_type) {
919 case ACB_ADAPTER_TYPE_A: {
920 u_int32_t outbound_intstatus;
921
922 /*clear and abort all outbound posted Q*/
923 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
924 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
925 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
926 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
927 arcmsr_drain_donequeue(acb, flag_srb, error);
928 }
929 }
930 break;
931 case ACB_ADAPTER_TYPE_B: {
932 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
933
934 /*clear all outbound posted Q*/
935 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
936 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
937 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
938 phbbmu->done_qbuffer[i] = 0;
939 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
940 arcmsr_drain_donequeue(acb, flag_srb, error);
941 }
942 phbbmu->post_qbuffer[i] = 0;
943 }/*drain reply FIFO*/
944 phbbmu->doneq_index = 0;
945 phbbmu->postq_index = 0;
946 }
947 break;
948 case ACB_ADAPTER_TYPE_C: {
949 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
950 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
951 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
952 arcmsr_drain_donequeue(acb, flag_srb, error);
953 }
954 }
955 break;
956 case ACB_ADAPTER_TYPE_D:
957 arcmsr_hbd_postqueue_isr(acb);
958 break;
959 case ACB_ADAPTER_TYPE_E:
960 arcmsr_hbe_postqueue_isr(acb);
961 break;
962 case ACB_ADAPTER_TYPE_F:
963 arcmsr_hbf_postqueue_isr(acb);
964 break;
965 }
966 }
967 /*
968 ****************************************************************************
969 ****************************************************************************
970 */
arcmsr_iop_reset(struct AdapterControlBlock * acb)971 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
972 {
973 struct CommandControlBlock *srb;
974 u_int32_t intmask_org;
975 u_int32_t i=0;
976
977 if(acb->srboutstandingcount>0) {
978 /* disable all outbound interrupt */
979 intmask_org = arcmsr_disable_allintr(acb);
980 /*clear and abort all outbound posted Q*/
981 arcmsr_done4abort_postqueue(acb);
982 /* talk to iop 331 outstanding command aborted*/
983 arcmsr_abort_allcmd(acb);
984 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
985 srb = acb->psrb_pool[i];
986 if(srb->srb_state == ARCMSR_SRB_START) {
987 srb->srb_state = ARCMSR_SRB_ABORTED;
988 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
989 arcmsr_srb_complete(srb, 1);
990 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
991 , acb->pci_unit, srb->pccb->ccb_h.target_id
992 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
993 }
994 }
995 /* enable all outbound interrupt */
996 arcmsr_enable_allintr(acb, intmask_org);
997 }
998 acb->srboutstandingcount = 0;
999 acb->workingsrb_doneindex = 0;
1000 acb->workingsrb_startindex = 0;
1001 acb->pktRequestCount = 0;
1002 acb->pktReturnCount = 0;
1003 }
1004 /*
1005 **********************************************************************
1006 **********************************************************************
1007 */
arcmsr_build_srb(struct CommandControlBlock * srb,bus_dma_segment_t * dm_segs,u_int32_t nseg)1008 static void arcmsr_build_srb(struct CommandControlBlock *srb,
1009 bus_dma_segment_t *dm_segs, u_int32_t nseg)
1010 {
1011 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
1012 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
1013 u_int32_t address_lo, address_hi;
1014 union ccb *pccb = srb->pccb;
1015 struct ccb_scsiio *pcsio = &pccb->csio;
1016 u_int32_t arccdbsize = 0x30;
1017
1018 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1019 arcmsr_cdb->Bus = 0;
1020 arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
1021 arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
1022 arcmsr_cdb->Function = 1;
1023 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
1024 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len);
1025 if(nseg != 0) {
1026 struct AdapterControlBlock *acb = srb->acb;
1027 bus_dmasync_op_t op;
1028 u_int32_t length, i, cdb_sgcount = 0;
1029
1030 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1031 op = BUS_DMASYNC_PREREAD;
1032 } else {
1033 op = BUS_DMASYNC_PREWRITE;
1034 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1035 srb->srb_flags |= SRB_FLAG_WRITE;
1036 }
1037 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1038 for(i=0; i < nseg; i++) {
1039 /* Get the physical address of the current data pointer */
1040 length = arcmsr_htole32(dm_segs[i].ds_len);
1041 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1042 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1043 if(address_hi == 0) {
1044 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1045 pdma_sg->address = address_lo;
1046 pdma_sg->length = length;
1047 psge += sizeof(struct SG32ENTRY);
1048 arccdbsize += sizeof(struct SG32ENTRY);
1049 } else {
1050 u_int32_t sg64s_size = 0, tmplength = length;
1051
1052 while(1) {
1053 u_int64_t span4G, length0;
1054 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1055
1056 span4G = (u_int64_t)address_lo + tmplength;
1057 pdma_sg->addresshigh = address_hi;
1058 pdma_sg->address = address_lo;
1059 if(span4G > 0x100000000) {
1060 /*see if cross 4G boundary*/
1061 length0 = 0x100000000-address_lo;
1062 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1063 address_hi = address_hi+1;
1064 address_lo = 0;
1065 tmplength = tmplength - (u_int32_t)length0;
1066 sg64s_size += sizeof(struct SG64ENTRY);
1067 psge += sizeof(struct SG64ENTRY);
1068 cdb_sgcount++;
1069 } else {
1070 pdma_sg->length = tmplength | IS_SG64_ADDR;
1071 sg64s_size += sizeof(struct SG64ENTRY);
1072 psge += sizeof(struct SG64ENTRY);
1073 break;
1074 }
1075 }
1076 arccdbsize += sg64s_size;
1077 }
1078 cdb_sgcount++;
1079 }
1080 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1081 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1082 if( arccdbsize > 256) {
1083 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1084 }
1085 } else {
1086 arcmsr_cdb->DataLength = 0;
1087 }
1088 srb->arc_cdb_size = arccdbsize;
1089 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1090 }
1091 /*
1092 **************************************************************************
1093 **************************************************************************
1094 */
arcmsr_post_srb(struct AdapterControlBlock * acb,struct CommandControlBlock * srb)1095 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1096 {
1097 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1098 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1099
1100 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1101 atomic_add_int(&acb->srboutstandingcount, 1);
1102 srb->srb_state = ARCMSR_SRB_START;
1103
1104 switch (acb->adapter_type) {
1105 case ACB_ADAPTER_TYPE_A: {
1106 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1107 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1108 } else {
1109 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1110 }
1111 }
1112 break;
1113 case ACB_ADAPTER_TYPE_B: {
1114 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1115 int ending_index, index;
1116
1117 index = phbbmu->postq_index;
1118 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1119 phbbmu->post_qbuffer[ending_index] = 0;
1120 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1121 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1122 } else {
1123 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1124 }
1125 index++;
1126 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
1127 phbbmu->postq_index = index;
1128 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1129 }
1130 break;
1131 case ACB_ADAPTER_TYPE_C: {
1132 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1133
1134 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1135 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1136 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1137 if(cdb_phyaddr_hi32)
1138 {
1139 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1140 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1141 }
1142 else
1143 {
1144 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1145 }
1146 }
1147 break;
1148 case ACB_ADAPTER_TYPE_D: {
1149 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1150 u_int16_t index_stripped;
1151 u_int16_t postq_index;
1152 struct InBound_SRB *pinbound_srb;
1153
1154 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1155 postq_index = phbdmu->postq_index;
1156 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1157 pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1158 pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1159 pinbound_srb->length = srb->arc_cdb_size >> 2;
1160 arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1161 if (postq_index & 0x4000) {
1162 index_stripped = postq_index & 0xFF;
1163 index_stripped += 1;
1164 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1165 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1166 } else {
1167 index_stripped = postq_index;
1168 index_stripped += 1;
1169 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1170 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1171 }
1172 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1173 ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1174 }
1175 break;
1176 case ACB_ADAPTER_TYPE_E: {
1177 u_int32_t ccb_post_stamp, arc_cdb_size;
1178
1179 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1180 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
1181 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
1182 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1183 }
1184 break;
1185 case ACB_ADAPTER_TYPE_F: {
1186 u_int32_t ccb_post_stamp, arc_cdb_size;
1187
1188 if (srb->arc_cdb_size <= 0x300)
1189 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1;
1190 else {
1191 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2;
1192 if (arc_cdb_size > 0xF)
1193 arc_cdb_size = 0xF;
1194 arc_cdb_size = (arc_cdb_size << 1) | 1;
1195 }
1196 ccb_post_stamp = (srb->smid | arc_cdb_size);
1197 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0);
1198 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1199 }
1200 break;
1201 }
1202 }
1203 /*
1204 ************************************************************************
1205 ************************************************************************
1206 */
arcmsr_get_iop_rqbuffer(struct AdapterControlBlock * acb)1207 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1208 {
1209 struct QBUFFER *qbuffer=NULL;
1210
1211 switch (acb->adapter_type) {
1212 case ACB_ADAPTER_TYPE_A: {
1213 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1214
1215 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1216 }
1217 break;
1218 case ACB_ADAPTER_TYPE_B: {
1219 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1220
1221 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1222 }
1223 break;
1224 case ACB_ADAPTER_TYPE_C: {
1225 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1226
1227 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1228 }
1229 break;
1230 case ACB_ADAPTER_TYPE_D: {
1231 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1232
1233 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1234 }
1235 break;
1236 case ACB_ADAPTER_TYPE_E: {
1237 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1238
1239 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1240 }
1241 break;
1242 case ACB_ADAPTER_TYPE_F:
1243 qbuffer = (struct QBUFFER *)acb->message_rbuffer;
1244 break;
1245 }
1246 return(qbuffer);
1247 }
1248 /*
1249 ************************************************************************
1250 ************************************************************************
1251 */
arcmsr_get_iop_wqbuffer(struct AdapterControlBlock * acb)1252 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1253 {
1254 struct QBUFFER *qbuffer = NULL;
1255
1256 switch (acb->adapter_type) {
1257 case ACB_ADAPTER_TYPE_A: {
1258 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1259
1260 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1261 }
1262 break;
1263 case ACB_ADAPTER_TYPE_B: {
1264 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1265
1266 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1267 }
1268 break;
1269 case ACB_ADAPTER_TYPE_C: {
1270 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1271
1272 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1273 }
1274 break;
1275 case ACB_ADAPTER_TYPE_D: {
1276 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1277
1278 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1279 }
1280 break;
1281 case ACB_ADAPTER_TYPE_E: {
1282 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1283
1284 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1285 }
1286 break;
1287 case ACB_ADAPTER_TYPE_F:
1288 qbuffer = (struct QBUFFER *)acb->message_wbuffer;
1289 break;
1290 }
1291 return(qbuffer);
1292 }
1293 /*
1294 **************************************************************************
1295 **************************************************************************
1296 */
arcmsr_iop_message_read(struct AdapterControlBlock * acb)1297 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1298 {
1299 switch (acb->adapter_type) {
1300 case ACB_ADAPTER_TYPE_A: {
1301 /* let IOP know data has been read */
1302 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1303 }
1304 break;
1305 case ACB_ADAPTER_TYPE_B: {
1306 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1307 /* let IOP know data has been read */
1308 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1309 }
1310 break;
1311 case ACB_ADAPTER_TYPE_C: {
1312 /* let IOP know data has been read */
1313 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1314 }
1315 break;
1316 case ACB_ADAPTER_TYPE_D: {
1317 /* let IOP know data has been read */
1318 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1319 }
1320 break;
1321 case ACB_ADAPTER_TYPE_E:
1322 case ACB_ADAPTER_TYPE_F: {
1323 /* let IOP know data has been read */
1324 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1325 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1326 }
1327 break;
1328 }
1329 }
1330 /*
1331 **************************************************************************
1332 **************************************************************************
1333 */
arcmsr_iop_message_wrote(struct AdapterControlBlock * acb)1334 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1335 {
1336 switch (acb->adapter_type) {
1337 case ACB_ADAPTER_TYPE_A: {
1338 /*
1339 ** push inbound doorbell tell iop, driver data write ok
1340 ** and wait reply on next hwinterrupt for next Qbuffer post
1341 */
1342 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1343 }
1344 break;
1345 case ACB_ADAPTER_TYPE_B: {
1346 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1347 /*
1348 ** push inbound doorbell tell iop, driver data write ok
1349 ** and wait reply on next hwinterrupt for next Qbuffer post
1350 */
1351 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1352 }
1353 break;
1354 case ACB_ADAPTER_TYPE_C: {
1355 /*
1356 ** push inbound doorbell tell iop, driver data write ok
1357 ** and wait reply on next hwinterrupt for next Qbuffer post
1358 */
1359 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1360 }
1361 break;
1362 case ACB_ADAPTER_TYPE_D: {
1363 /*
1364 ** push inbound doorbell tell iop, driver data write ok
1365 ** and wait reply on next hwinterrupt for next Qbuffer post
1366 */
1367 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1368 }
1369 break;
1370 case ACB_ADAPTER_TYPE_E:
1371 case ACB_ADAPTER_TYPE_F: {
1372 /*
1373 ** push inbound doorbell tell iop, driver data write ok
1374 ** and wait reply on next hwinterrupt for next Qbuffer post
1375 */
1376 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
1377 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1378 }
1379 break;
1380 }
1381 }
1382 /*
1383 ************************************************************************
1384 ************************************************************************
1385 */
arcmsr_stop_hba_bgrb(struct AdapterControlBlock * acb)1386 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1387 {
1388 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1389 CHIP_REG_WRITE32(HBA_MessageUnit,
1390 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1391 if(!arcmsr_hba_wait_msgint_ready(acb)) {
1392 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1393 , acb->pci_unit);
1394 }
1395 }
1396 /*
1397 ************************************************************************
1398 ************************************************************************
1399 */
arcmsr_stop_hbb_bgrb(struct AdapterControlBlock * acb)1400 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1401 {
1402 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1403 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1404 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1405 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1406 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1407 , acb->pci_unit);
1408 }
1409 }
1410 /*
1411 ************************************************************************
1412 ************************************************************************
1413 */
arcmsr_stop_hbc_bgrb(struct AdapterControlBlock * acb)1414 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1415 {
1416 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1417 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1418 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1419 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1420 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1421 }
1422 }
1423 /*
1424 ************************************************************************
1425 ************************************************************************
1426 */
arcmsr_stop_hbd_bgrb(struct AdapterControlBlock * acb)1427 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1428 {
1429 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1430 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1431 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1432 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1433 }
1434 }
1435 /*
1436 ************************************************************************
1437 ************************************************************************
1438 */
arcmsr_stop_hbe_bgrb(struct AdapterControlBlock * acb)1439 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb)
1440 {
1441 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1442 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1443 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1444 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1445 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
1446 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1447 }
1448 }
1449 /*
1450 ************************************************************************
1451 ************************************************************************
1452 */
arcmsr_stop_adapter_bgrb(struct AdapterControlBlock * acb)1453 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1454 {
1455 switch (acb->adapter_type) {
1456 case ACB_ADAPTER_TYPE_A: {
1457 arcmsr_stop_hba_bgrb(acb);
1458 }
1459 break;
1460 case ACB_ADAPTER_TYPE_B: {
1461 arcmsr_stop_hbb_bgrb(acb);
1462 }
1463 break;
1464 case ACB_ADAPTER_TYPE_C: {
1465 arcmsr_stop_hbc_bgrb(acb);
1466 }
1467 break;
1468 case ACB_ADAPTER_TYPE_D: {
1469 arcmsr_stop_hbd_bgrb(acb);
1470 }
1471 break;
1472 case ACB_ADAPTER_TYPE_E:
1473 case ACB_ADAPTER_TYPE_F: {
1474 arcmsr_stop_hbe_bgrb(acb);
1475 }
1476 break;
1477 }
1478 }
1479 /*
1480 ************************************************************************
1481 ************************************************************************
1482 */
arcmsr_poll(struct cam_sim * psim)1483 static void arcmsr_poll(struct cam_sim *psim)
1484 {
1485 struct AdapterControlBlock *acb;
1486 int mutex;
1487
1488 acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1489 mutex = mtx_owned(&acb->isr_lock);
1490 if( mutex == 0 )
1491 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1492 arcmsr_interrupt(acb);
1493 if( mutex == 0 )
1494 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1495 }
1496 /*
1497 **************************************************************************
1498 **************************************************************************
1499 */
arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock * acb,struct QBUFFER * prbuffer)1500 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1501 struct QBUFFER *prbuffer) {
1502 u_int8_t *pQbuffer;
1503 u_int8_t *buf1 = NULL;
1504 u_int32_t *iop_data, *buf2 = NULL;
1505 u_int32_t iop_len, data_len;
1506
1507 iop_data = (u_int32_t *)prbuffer->data;
1508 iop_len = (u_int32_t)prbuffer->data_len;
1509 if ( iop_len > 0 )
1510 {
1511 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1512 buf2 = (u_int32_t *)buf1;
1513 if( buf1 == NULL)
1514 return (0);
1515 data_len = iop_len;
1516 while(data_len >= 4)
1517 {
1518 *buf2++ = *iop_data++;
1519 data_len -= 4;
1520 }
1521 if(data_len)
1522 *buf2 = *iop_data;
1523 buf2 = (u_int32_t *)buf1;
1524 }
1525 while (iop_len > 0) {
1526 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1527 *pQbuffer = *buf1;
1528 acb->rqbuf_lastindex++;
1529 /* if last, index number set it to 0 */
1530 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1531 buf1++;
1532 iop_len--;
1533 }
1534 if(buf2)
1535 free( (u_int8_t *)buf2, M_DEVBUF);
1536 /* let IOP know data has been read */
1537 arcmsr_iop_message_read(acb);
1538 return (1);
1539 }
1540 /*
1541 **************************************************************************
1542 **************************************************************************
1543 */
arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock * acb,struct QBUFFER * prbuffer)1544 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1545 struct QBUFFER *prbuffer) {
1546 u_int8_t *pQbuffer;
1547 u_int8_t *iop_data;
1548 u_int32_t iop_len;
1549
1550 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1551 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1552 }
1553 iop_data = (u_int8_t *)prbuffer->data;
1554 iop_len = (u_int32_t)prbuffer->data_len;
1555 while (iop_len > 0) {
1556 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1557 *pQbuffer = *iop_data;
1558 acb->rqbuf_lastindex++;
1559 /* if last, index number set it to 0 */
1560 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1561 iop_data++;
1562 iop_len--;
1563 }
1564 /* let IOP know data has been read */
1565 arcmsr_iop_message_read(acb);
1566 return (1);
1567 }
1568 /*
1569 **************************************************************************
1570 **************************************************************************
1571 */
arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock * acb)1572 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1573 {
1574 struct QBUFFER *prbuffer;
1575 int my_empty_len;
1576
1577 /*check this iop data if overflow my rqbuffer*/
1578 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1579 prbuffer = arcmsr_get_iop_rqbuffer(acb);
1580 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1581 (ARCMSR_MAX_QBUFFER-1);
1582 if(my_empty_len >= prbuffer->data_len) {
1583 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1584 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1585 } else {
1586 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1587 }
1588 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1589 }
1590 /*
1591 **********************************************************************
1592 **********************************************************************
1593 */
arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock * acb)1594 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1595 {
1596 u_int8_t *pQbuffer;
1597 struct QBUFFER *pwbuffer;
1598 u_int8_t *buf1 = NULL;
1599 u_int32_t *iop_data, *buf2 = NULL;
1600 u_int32_t allxfer_len = 0, data_len;
1601
1602 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1603 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1604 buf2 = (u_int32_t *)buf1;
1605 if( buf1 == NULL)
1606 return;
1607
1608 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1609 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1610 iop_data = (u_int32_t *)pwbuffer->data;
1611 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1612 && (allxfer_len < 124)) {
1613 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1614 *buf1 = *pQbuffer;
1615 acb->wqbuf_firstindex++;
1616 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1617 buf1++;
1618 allxfer_len++;
1619 }
1620 pwbuffer->data_len = allxfer_len;
1621 data_len = allxfer_len;
1622 buf1 = (u_int8_t *)buf2;
1623 while(data_len >= 4)
1624 {
1625 *iop_data++ = *buf2++;
1626 data_len -= 4;
1627 }
1628 if(data_len)
1629 *iop_data = *buf2;
1630 free( buf1, M_DEVBUF);
1631 arcmsr_iop_message_wrote(acb);
1632 }
1633 }
1634 /*
1635 **********************************************************************
1636 **********************************************************************
1637 */
arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock * acb)1638 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1639 {
1640 u_int8_t *pQbuffer;
1641 struct QBUFFER *pwbuffer;
1642 u_int8_t *iop_data;
1643 int32_t allxfer_len=0;
1644
1645 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1646 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1647 return;
1648 }
1649 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1650 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1651 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1652 iop_data = (u_int8_t *)pwbuffer->data;
1653 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1654 && (allxfer_len < 124)) {
1655 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1656 *iop_data = *pQbuffer;
1657 acb->wqbuf_firstindex++;
1658 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1659 iop_data++;
1660 allxfer_len++;
1661 }
1662 pwbuffer->data_len = allxfer_len;
1663 arcmsr_iop_message_wrote(acb);
1664 }
1665 }
1666 /*
1667 **************************************************************************
1668 **************************************************************************
1669 */
arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock * acb)1670 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1671 {
1672 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1673 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1674 /*
1675 *****************************************************************
1676 ** check if there are any mail packages from user space program
1677 ** in my post bag, now is the time to send them into Areca's firmware
1678 *****************************************************************
1679 */
1680 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1681 arcmsr_Write_data_2iop_wqbuffer(acb);
1682 }
1683 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1684 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1685 }
1686 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1687 }
1688 /*
1689 **************************************************************************
1690 **************************************************************************
1691 */
arcmsr_rescanLun_cb(struct cam_periph * periph,union ccb * ccb)1692 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1693 {
1694 /*
1695 if (ccb->ccb_h.status != CAM_REQ_CMP)
1696 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1697 "failure status=%x\n", ccb->ccb_h.target_id,
1698 ccb->ccb_h.target_lun, ccb->ccb_h.status);
1699 else
1700 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1701 */
1702 xpt_free_path(ccb->ccb_h.path);
1703 xpt_free_ccb(ccb);
1704 }
1705
arcmsr_rescan_lun(struct AdapterControlBlock * acb,int target,int lun)1706 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1707 {
1708 struct cam_path *path;
1709 union ccb *ccb;
1710
1711 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1712 return;
1713 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1714 {
1715 xpt_free_ccb(ccb);
1716 return;
1717 }
1718 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1719 bzero(ccb, sizeof(union ccb));
1720 xpt_setup_ccb(&ccb->ccb_h, path, 5);
1721 ccb->ccb_h.func_code = XPT_SCAN_LUN;
1722 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1723 ccb->crcn.flags = CAM_FLAG_NONE;
1724 xpt_action(ccb);
1725 }
1726
arcmsr_abort_dr_ccbs(struct AdapterControlBlock * acb,int target,int lun)1727 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1728 {
1729 struct CommandControlBlock *srb;
1730 u_int32_t intmask_org;
1731 int i;
1732
1733 /* disable all outbound interrupts */
1734 intmask_org = arcmsr_disable_allintr(acb);
1735 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1736 {
1737 srb = acb->psrb_pool[i];
1738 if (srb->srb_state == ARCMSR_SRB_START)
1739 {
1740 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1741 {
1742 srb->srb_state = ARCMSR_SRB_ABORTED;
1743 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1744 arcmsr_srb_complete(srb, 1);
1745 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1746 }
1747 }
1748 }
1749 /* enable outbound Post Queue, outbound doorbell Interrupt */
1750 arcmsr_enable_allintr(acb, intmask_org);
1751 }
1752 /*
1753 **************************************************************************
1754 **************************************************************************
1755 */
arcmsr_dr_handle(struct AdapterControlBlock * acb)1756 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1757 u_int32_t devicemap;
1758 u_int32_t target, lun;
1759 u_int32_t deviceMapCurrent[4]={0};
1760 u_int8_t *pDevMap;
1761
1762 switch (acb->adapter_type) {
1763 case ACB_ADAPTER_TYPE_A:
1764 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1765 for (target = 0; target < 4; target++)
1766 {
1767 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1768 devicemap += 4;
1769 }
1770 break;
1771
1772 case ACB_ADAPTER_TYPE_B:
1773 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1774 for (target = 0; target < 4; target++)
1775 {
1776 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap);
1777 devicemap += 4;
1778 }
1779 break;
1780
1781 case ACB_ADAPTER_TYPE_C:
1782 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1783 for (target = 0; target < 4; target++)
1784 {
1785 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1786 devicemap += 4;
1787 }
1788 break;
1789 case ACB_ADAPTER_TYPE_D:
1790 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1791 for (target = 0; target < 4; target++)
1792 {
1793 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1794 devicemap += 4;
1795 }
1796 break;
1797 case ACB_ADAPTER_TYPE_E:
1798 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1799 for (target = 0; target < 4; target++)
1800 {
1801 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1802 devicemap += 4;
1803 }
1804 break;
1805 case ACB_ADAPTER_TYPE_F:
1806 devicemap = ARCMSR_FW_DEVMAP_OFFSET;
1807 for (target = 0; target < 4; target++)
1808 {
1809 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap];
1810 devicemap += 1;
1811 }
1812 break;
1813 }
1814
1815 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1816 {
1817 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1818 }
1819 /*
1820 ** adapter posted CONFIG message
1821 ** copy the new map, note if there are differences with the current map
1822 */
1823 pDevMap = (u_int8_t *)&deviceMapCurrent[0];
1824 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1825 {
1826 if (*pDevMap != acb->device_map[target])
1827 {
1828 u_int8_t difference, bit_check;
1829
1830 difference = *pDevMap ^ acb->device_map[target];
1831 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1832 {
1833 bit_check = (1 << lun); /*check bit from 0....31*/
1834 if(difference & bit_check)
1835 {
1836 if(acb->device_map[target] & bit_check)
1837 {/* unit departed */
1838 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1839 arcmsr_abort_dr_ccbs(acb, target, lun);
1840 arcmsr_rescan_lun(acb, target, lun);
1841 acb->devstate[target][lun] = ARECA_RAID_GONE;
1842 }
1843 else
1844 {/* unit arrived */
1845 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1846 arcmsr_rescan_lun(acb, target, lun);
1847 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1848 }
1849 }
1850 }
1851 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1852 acb->device_map[target] = *pDevMap;
1853 }
1854 pDevMap++;
1855 }
1856 }
1857 /*
1858 **************************************************************************
1859 **************************************************************************
1860 */
arcmsr_hba_message_isr(struct AdapterControlBlock * acb)1861 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1862 u_int32_t outbound_message;
1863
1864 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1865 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1866 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1867 arcmsr_dr_handle( acb );
1868 }
1869 /*
1870 **************************************************************************
1871 **************************************************************************
1872 */
arcmsr_hbb_message_isr(struct AdapterControlBlock * acb)1873 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1874 u_int32_t outbound_message;
1875 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1876
1877 /* clear interrupts */
1878 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1879 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1880 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1881 arcmsr_dr_handle( acb );
1882 }
1883 /*
1884 **************************************************************************
1885 **************************************************************************
1886 */
arcmsr_hbc_message_isr(struct AdapterControlBlock * acb)1887 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1888 u_int32_t outbound_message;
1889
1890 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1891 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1892 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1893 arcmsr_dr_handle( acb );
1894 }
1895 /*
1896 **************************************************************************
1897 **************************************************************************
1898 */
arcmsr_hbd_message_isr(struct AdapterControlBlock * acb)1899 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1900 u_int32_t outbound_message;
1901
1902 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1903 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1904 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1905 arcmsr_dr_handle( acb );
1906 }
1907 /*
1908 **************************************************************************
1909 **************************************************************************
1910 */
arcmsr_hbe_message_isr(struct AdapterControlBlock * acb)1911 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) {
1912 u_int32_t outbound_message;
1913
1914 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);
1915 if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
1916 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]);
1917 else
1918 outbound_message = acb->msgcode_rwbuffer[0];
1919 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1920 arcmsr_dr_handle( acb );
1921 }
1922 /*
1923 **************************************************************************
1924 **************************************************************************
1925 */
arcmsr_hba_doorbell_isr(struct AdapterControlBlock * acb)1926 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1927 {
1928 u_int32_t doorbell_status;
1929
1930 /*
1931 *******************************************************************
1932 ** Maybe here we need to check wrqbuffer_lock is lock or not
1933 ** DOORBELL: din! don!
1934 ** check if there are any mail need to pack from firmware
1935 *******************************************************************
1936 */
1937 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1938 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1939 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1940 arcmsr_iop2drv_data_wrote_handle(acb);
1941 }
1942 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1943 arcmsr_iop2drv_data_read_handle(acb);
1944 }
1945 }
1946 /*
1947 **************************************************************************
1948 **************************************************************************
1949 */
arcmsr_hbc_doorbell_isr(struct AdapterControlBlock * acb)1950 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1951 {
1952 u_int32_t doorbell_status;
1953
1954 /*
1955 *******************************************************************
1956 ** Maybe here we need to check wrqbuffer_lock is lock or not
1957 ** DOORBELL: din! don!
1958 ** check if there are any mail need to pack from firmware
1959 *******************************************************************
1960 */
1961 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1962 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1963 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1964 arcmsr_iop2drv_data_wrote_handle(acb);
1965 }
1966 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1967 arcmsr_iop2drv_data_read_handle(acb);
1968 }
1969 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1970 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */
1971 }
1972 }
1973 /*
1974 **************************************************************************
1975 **************************************************************************
1976 */
arcmsr_hbd_doorbell_isr(struct AdapterControlBlock * acb)1977 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1978 {
1979 u_int32_t doorbell_status;
1980
1981 /*
1982 *******************************************************************
1983 ** Maybe here we need to check wrqbuffer_lock is lock or not
1984 ** DOORBELL: din! don!
1985 ** check if there are any mail need to pack from firmware
1986 *******************************************************************
1987 */
1988 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1989 if(doorbell_status)
1990 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1991 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1992 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1993 arcmsr_iop2drv_data_wrote_handle(acb);
1994 }
1995 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1996 arcmsr_iop2drv_data_read_handle(acb);
1997 }
1998 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1999 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */
2000 }
2001 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
2002 if(doorbell_status)
2003 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
2004 }
2005 }
2006 /*
2007 **************************************************************************
2008 **************************************************************************
2009 */
arcmsr_hbe_doorbell_isr(struct AdapterControlBlock * acb)2010 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb)
2011 {
2012 u_int32_t doorbell_status, in_doorbell;
2013
2014 /*
2015 *******************************************************************
2016 ** Maybe here we need to check wrqbuffer_lock is lock or not
2017 ** DOORBELL: din! don!
2018 ** check if there are any mail need to pack from firmware
2019 *******************************************************************
2020 */
2021 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
2022 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
2023 doorbell_status = in_doorbell ^ acb->in_doorbell;
2024 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2025 arcmsr_iop2drv_data_wrote_handle(acb);
2026 }
2027 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2028 arcmsr_iop2drv_data_read_handle(acb);
2029 }
2030 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2031 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */
2032 }
2033 acb->in_doorbell = in_doorbell;
2034 }
2035 /*
2036 **************************************************************************
2037 **************************************************************************
2038 */
arcmsr_hbf_doorbell_isr(struct AdapterControlBlock * acb)2039 static void arcmsr_hbf_doorbell_isr(struct AdapterControlBlock *acb)
2040 {
2041 u_int32_t doorbell_status, in_doorbell;
2042
2043 /*
2044 *******************************************************************
2045 ** Maybe here we need to check wrqbuffer_lock is lock or not
2046 ** DOORBELL: din! don!
2047 ** check if there are any mail need to pack from firmware
2048 *******************************************************************
2049 */
2050 while(1) {
2051 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
2052 if ((in_doorbell != 0) && (in_doorbell != 0xFFFFFFFF))
2053 break;
2054 }
2055 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
2056 doorbell_status = in_doorbell ^ acb->in_doorbell;
2057 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2058 arcmsr_iop2drv_data_wrote_handle(acb);
2059 }
2060 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2061 arcmsr_iop2drv_data_read_handle(acb);
2062 }
2063 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2064 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */
2065 }
2066 acb->in_doorbell = in_doorbell;
2067 }
2068 /*
2069 **************************************************************************
2070 **************************************************************************
2071 */
arcmsr_hba_postqueue_isr(struct AdapterControlBlock * acb)2072 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
2073 {
2074 u_int32_t flag_srb;
2075 u_int16_t error;
2076
2077 /*
2078 *****************************************************************************
2079 ** areca cdb command done
2080 *****************************************************************************
2081 */
2082 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2083 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2084 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
2085 0, outbound_queueport)) != 0xFFFFFFFF) {
2086 /* check if command done with no error*/
2087 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
2088 arcmsr_drain_donequeue(acb, flag_srb, error);
2089 } /*drain reply FIFO*/
2090 }
2091 /*
2092 **************************************************************************
2093 **************************************************************************
2094 */
arcmsr_hbb_postqueue_isr(struct AdapterControlBlock * acb)2095 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
2096 {
2097 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2098 u_int32_t flag_srb;
2099 int index;
2100 u_int16_t error;
2101
2102 /*
2103 *****************************************************************************
2104 ** areca cdb command done
2105 *****************************************************************************
2106 */
2107 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2108 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2109 index = phbbmu->doneq_index;
2110 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
2111 phbbmu->done_qbuffer[index] = 0;
2112 index++;
2113 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
2114 phbbmu->doneq_index = index;
2115 /* check if command done with no error*/
2116 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2117 arcmsr_drain_donequeue(acb, flag_srb, error);
2118 } /*drain reply FIFO*/
2119 }
2120 /*
2121 **************************************************************************
2122 **************************************************************************
2123 */
arcmsr_hbc_postqueue_isr(struct AdapterControlBlock * acb)2124 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
2125 {
2126 u_int32_t flag_srb,throttling = 0;
2127 u_int16_t error;
2128
2129 /*
2130 *****************************************************************************
2131 ** areca cdb command done
2132 *****************************************************************************
2133 */
2134 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2135 do {
2136 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
2137 if (flag_srb == 0xFFFFFFFF)
2138 break;
2139 /* check if command done with no error*/
2140 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
2141 arcmsr_drain_donequeue(acb, flag_srb, error);
2142 throttling++;
2143 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2144 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
2145 throttling = 0;
2146 }
2147 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
2148 }
2149 /*
2150 **********************************************************************
2151 **
2152 **********************************************************************
2153 */
arcmsr_get_doneq_index(struct HBD_MessageUnit0 * phbdmu)2154 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
2155 {
2156 uint16_t doneq_index, index_stripped;
2157
2158 doneq_index = phbdmu->doneq_index;
2159 if (doneq_index & 0x4000) {
2160 index_stripped = doneq_index & 0xFF;
2161 index_stripped += 1;
2162 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2163 phbdmu->doneq_index = index_stripped ?
2164 (index_stripped | 0x4000) : index_stripped;
2165 } else {
2166 index_stripped = doneq_index;
2167 index_stripped += 1;
2168 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2169 phbdmu->doneq_index = index_stripped ?
2170 index_stripped : (index_stripped | 0x4000);
2171 }
2172 return (phbdmu->doneq_index);
2173 }
2174 /*
2175 **************************************************************************
2176 **************************************************************************
2177 */
arcmsr_hbd_postqueue_isr(struct AdapterControlBlock * acb)2178 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
2179 {
2180 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
2181 u_int32_t outbound_write_pointer;
2182 u_int32_t addressLow;
2183 uint16_t doneq_index;
2184 u_int16_t error;
2185 /*
2186 *****************************************************************************
2187 ** areca cdb command done
2188 *****************************************************************************
2189 */
2190 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
2191 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
2192 return;
2193 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2194 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2195 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2196 doneq_index = phbdmu->doneq_index;
2197 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
2198 doneq_index = arcmsr_get_doneq_index(phbdmu);
2199 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2200 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2201 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2202 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2203 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2204 }
2205 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2206 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2207 }
2208 /*
2209 **************************************************************************
2210 **************************************************************************
2211 */
arcmsr_hbe_postqueue_isr(struct AdapterControlBlock * acb)2212 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb)
2213 {
2214 u_int16_t error;
2215 uint32_t doneq_index;
2216 uint16_t cmdSMID;
2217
2218 /*
2219 *****************************************************************************
2220 ** areca cdb command done
2221 *****************************************************************************
2222 */
2223 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2224 doneq_index = acb->doneq_index;
2225 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) {
2226 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2227 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2228 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2229 doneq_index++;
2230 if (doneq_index >= acb->completionQ_entry)
2231 doneq_index = 0;
2232 }
2233 acb->doneq_index = doneq_index;
2234 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2235 }
2236
arcmsr_hbf_postqueue_isr(struct AdapterControlBlock * acb)2237 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb)
2238 {
2239 uint16_t error;
2240 uint32_t doneq_index;
2241 uint16_t cmdSMID;
2242
2243 /*
2244 *****************************************************************************
2245 ** areca cdb command done
2246 *****************************************************************************
2247 */
2248 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2249 doneq_index = acb->doneq_index;
2250 while (1) {
2251 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2252 if (cmdSMID == 0xffff)
2253 break;
2254 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2255 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2256 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
2257 doneq_index++;
2258 if (doneq_index >= acb->completionQ_entry)
2259 doneq_index = 0;
2260 }
2261 acb->doneq_index = doneq_index;
2262 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2263 }
2264
2265 /*
2266 **********************************************************************
2267 **********************************************************************
2268 */
arcmsr_handle_hba_isr(struct AdapterControlBlock * acb)2269 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2270 {
2271 u_int32_t outbound_intStatus;
2272 /*
2273 *********************************************
2274 ** check outbound intstatus
2275 *********************************************
2276 */
2277 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2278 if(!outbound_intStatus) {
2279 /*it must be share irq*/
2280 return;
2281 }
2282 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2283 /* MU doorbell interrupts*/
2284 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2285 arcmsr_hba_doorbell_isr(acb);
2286 }
2287 /* MU post queue interrupts*/
2288 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2289 arcmsr_hba_postqueue_isr(acb);
2290 }
2291 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2292 arcmsr_hba_message_isr(acb);
2293 }
2294 }
2295 /*
2296 **********************************************************************
2297 **********************************************************************
2298 */
arcmsr_handle_hbb_isr(struct AdapterControlBlock * acb)2299 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2300 {
2301 u_int32_t outbound_doorbell;
2302 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2303 /*
2304 *********************************************
2305 ** check outbound intstatus
2306 *********************************************
2307 */
2308 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable;
2309 if(!outbound_doorbell) {
2310 /*it must be share irq*/
2311 return;
2312 }
2313 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2314 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell);
2315 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2316 /* MU ioctl transfer doorbell interrupts*/
2317 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2318 arcmsr_iop2drv_data_wrote_handle(acb);
2319 }
2320 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2321 arcmsr_iop2drv_data_read_handle(acb);
2322 }
2323 /* MU post queue interrupts*/
2324 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2325 arcmsr_hbb_postqueue_isr(acb);
2326 }
2327 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2328 arcmsr_hbb_message_isr(acb);
2329 }
2330 }
2331 /*
2332 **********************************************************************
2333 **********************************************************************
2334 */
arcmsr_handle_hbc_isr(struct AdapterControlBlock * acb)2335 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2336 {
2337 u_int32_t host_interrupt_status;
2338 /*
2339 *********************************************
2340 ** check outbound intstatus
2341 *********************************************
2342 */
2343 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2344 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2345 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2346 if(!host_interrupt_status) {
2347 /*it must be share irq*/
2348 return;
2349 }
2350 do {
2351 /* MU doorbell interrupts*/
2352 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2353 arcmsr_hbc_doorbell_isr(acb);
2354 }
2355 /* MU post queue interrupts*/
2356 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2357 arcmsr_hbc_postqueue_isr(acb);
2358 }
2359 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2360 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2361 }
2362 /*
2363 **********************************************************************
2364 **********************************************************************
2365 */
arcmsr_handle_hbd_isr(struct AdapterControlBlock * acb)2366 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2367 {
2368 u_int32_t host_interrupt_status;
2369 u_int32_t intmask_org;
2370 /*
2371 *********************************************
2372 ** check outbound intstatus
2373 *********************************************
2374 */
2375 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2376 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2377 /*it must be share irq*/
2378 return;
2379 }
2380 /* disable outbound interrupt */
2381 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */
2382 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2383 /* MU doorbell interrupts*/
2384 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2385 arcmsr_hbd_doorbell_isr(acb);
2386 }
2387 /* MU post queue interrupts*/
2388 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2389 arcmsr_hbd_postqueue_isr(acb);
2390 }
2391 /* enable all outbound interrupt */
2392 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2393 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2394 }
2395 /*
2396 **********************************************************************
2397 **********************************************************************
2398 */
arcmsr_handle_hbe_isr(struct AdapterControlBlock * acb)2399 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb)
2400 {
2401 u_int32_t host_interrupt_status;
2402 /*
2403 *********************************************
2404 ** check outbound intstatus
2405 *********************************************
2406 */
2407 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) &
2408 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2409 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2410 if(!host_interrupt_status) {
2411 /*it must be share irq*/
2412 return;
2413 }
2414 do {
2415 /* MU doorbell interrupts*/
2416 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2417 arcmsr_hbe_doorbell_isr(acb);
2418 }
2419 /* MU post queue interrupts*/
2420 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2421 arcmsr_hbe_postqueue_isr(acb);
2422 }
2423 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
2424 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2425 }
2426
arcmsr_handle_hbf_isr(struct AdapterControlBlock * acb)2427 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb)
2428 {
2429 u_int32_t host_interrupt_status;
2430 /*
2431 *********************************************
2432 ** check outbound intstatus
2433 *********************************************
2434 */
2435 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) &
2436 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2437 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2438 if(!host_interrupt_status) {
2439 /*it must be share irq*/
2440 return;
2441 }
2442 do {
2443 /* MU doorbell interrupts*/
2444 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2445 arcmsr_hbf_doorbell_isr(acb);
2446 }
2447 /* MU post queue interrupts*/
2448 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2449 arcmsr_hbf_postqueue_isr(acb);
2450 }
2451 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status);
2452 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2453 }
2454 /*
2455 ******************************************************************************
2456 ******************************************************************************
2457 */
arcmsr_interrupt(struct AdapterControlBlock * acb)2458 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2459 {
2460 switch (acb->adapter_type) {
2461 case ACB_ADAPTER_TYPE_A:
2462 arcmsr_handle_hba_isr(acb);
2463 break;
2464 case ACB_ADAPTER_TYPE_B:
2465 arcmsr_handle_hbb_isr(acb);
2466 break;
2467 case ACB_ADAPTER_TYPE_C:
2468 arcmsr_handle_hbc_isr(acb);
2469 break;
2470 case ACB_ADAPTER_TYPE_D:
2471 arcmsr_handle_hbd_isr(acb);
2472 break;
2473 case ACB_ADAPTER_TYPE_E:
2474 arcmsr_handle_hbe_isr(acb);
2475 break;
2476 case ACB_ADAPTER_TYPE_F:
2477 arcmsr_handle_hbf_isr(acb);
2478 break;
2479 default:
2480 printf("arcmsr%d: interrupt service,"
2481 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2482 break;
2483 }
2484 }
2485 /*
2486 **********************************************************************
2487 **********************************************************************
2488 */
arcmsr_intr_handler(void * arg)2489 static void arcmsr_intr_handler(void *arg)
2490 {
2491 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2492
2493 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2494 arcmsr_interrupt(acb);
2495 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2496 }
2497 /*
2498 ******************************************************************************
2499 ******************************************************************************
2500 */
arcmsr_polling_devmap(void * arg)2501 static void arcmsr_polling_devmap(void *arg)
2502 {
2503 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2504 switch (acb->adapter_type) {
2505 case ACB_ADAPTER_TYPE_A:
2506 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2507 break;
2508
2509 case ACB_ADAPTER_TYPE_B: {
2510 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2511 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2512 }
2513 break;
2514
2515 case ACB_ADAPTER_TYPE_C:
2516 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2517 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2518 break;
2519
2520 case ACB_ADAPTER_TYPE_D:
2521 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2522 break;
2523
2524 case ACB_ADAPTER_TYPE_E:
2525 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2526 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2527 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2528 break;
2529
2530 case ACB_ADAPTER_TYPE_F: {
2531 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1);
2532 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
2533 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
2534 goto nxt6s;
2535 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2536 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2537 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2538 break;
2539 }
2540 }
2541 nxt6s:
2542 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2543 {
2544 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */
2545 }
2546 }
2547
2548 /*
2549 *******************************************************************************
2550 **
2551 *******************************************************************************
2552 */
arcmsr_iop_parking(struct AdapterControlBlock * acb)2553 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2554 {
2555 u_int32_t intmask_org;
2556
2557 if(acb != NULL) {
2558 /* stop adapter background rebuild */
2559 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2560 intmask_org = arcmsr_disable_allintr(acb);
2561 arcmsr_stop_adapter_bgrb(acb);
2562 arcmsr_flush_adapter_cache(acb);
2563 arcmsr_enable_allintr(acb, intmask_org);
2564 }
2565 }
2566 }
2567 /*
2568 ***********************************************************************
2569 **
2570 ************************************************************************
2571 */
arcmsr_iop_ioctlcmd(struct AdapterControlBlock * acb,u_int32_t ioctl_cmd,caddr_t arg)2572 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2573 {
2574 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2575 u_int32_t retvalue = EINVAL;
2576
2577 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2578 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2579 return retvalue;
2580 }
2581 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2582 switch(ioctl_cmd) {
2583 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2584 u_int8_t *pQbuffer;
2585 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2586 u_int32_t allxfer_len=0;
2587
2588 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2589 && (allxfer_len < 1031)) {
2590 /*copy READ QBUFFER to srb*/
2591 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2592 *ptmpQbuffer = *pQbuffer;
2593 acb->rqbuf_firstindex++;
2594 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2595 /*if last index number set it to 0 */
2596 ptmpQbuffer++;
2597 allxfer_len++;
2598 }
2599 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2600 struct QBUFFER *prbuffer;
2601
2602 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2603 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2604 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2605 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2606 }
2607 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2608 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2609 retvalue = ARCMSR_MESSAGE_SUCCESS;
2610 }
2611 break;
2612 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2613 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2614 u_int8_t *pQbuffer;
2615 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2616
2617 user_len = pcmdmessagefld->cmdmessage.Length;
2618 /*check if data xfer length of this request will overflow my array qbuffer */
2619 wqbuf_lastindex = acb->wqbuf_lastindex;
2620 wqbuf_firstindex = acb->wqbuf_firstindex;
2621 if(wqbuf_lastindex != wqbuf_firstindex) {
2622 arcmsr_Write_data_2iop_wqbuffer(acb);
2623 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2624 } else {
2625 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2626 (ARCMSR_MAX_QBUFFER - 1);
2627 if(my_empty_len >= user_len) {
2628 while(user_len > 0) {
2629 /*copy srb data to wqbuffer*/
2630 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2631 *pQbuffer = *ptmpuserbuffer;
2632 acb->wqbuf_lastindex++;
2633 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2634 /*if last index number set it to 0 */
2635 ptmpuserbuffer++;
2636 user_len--;
2637 }
2638 /*post fist Qbuffer*/
2639 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2640 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2641 arcmsr_Write_data_2iop_wqbuffer(acb);
2642 }
2643 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2644 } else {
2645 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2646 }
2647 }
2648 retvalue = ARCMSR_MESSAGE_SUCCESS;
2649 }
2650 break;
2651 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2652 u_int8_t *pQbuffer = acb->rqbuffer;
2653
2654 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2655 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2656 arcmsr_iop_message_read(acb);
2657 /*signature, let IOP know data has been readed */
2658 }
2659 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2660 acb->rqbuf_firstindex = 0;
2661 acb->rqbuf_lastindex = 0;
2662 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2663 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2664 retvalue = ARCMSR_MESSAGE_SUCCESS;
2665 }
2666 break;
2667 case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2668 {
2669 u_int8_t *pQbuffer = acb->wqbuffer;
2670
2671 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2672 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2673 arcmsr_iop_message_read(acb);
2674 /*signature, let IOP know data has been readed */
2675 }
2676 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2677 acb->wqbuf_firstindex = 0;
2678 acb->wqbuf_lastindex = 0;
2679 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2680 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2681 retvalue = ARCMSR_MESSAGE_SUCCESS;
2682 }
2683 break;
2684 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2685 u_int8_t *pQbuffer;
2686
2687 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2688 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2689 arcmsr_iop_message_read(acb);
2690 /*signature, let IOP know data has been readed */
2691 }
2692 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2693 |ACB_F_MESSAGE_RQBUFFER_CLEARED
2694 |ACB_F_MESSAGE_WQBUFFER_READ);
2695 acb->rqbuf_firstindex = 0;
2696 acb->rqbuf_lastindex = 0;
2697 acb->wqbuf_firstindex = 0;
2698 acb->wqbuf_lastindex = 0;
2699 pQbuffer = acb->rqbuffer;
2700 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2701 pQbuffer = acb->wqbuffer;
2702 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2703 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2704 retvalue = ARCMSR_MESSAGE_SUCCESS;
2705 }
2706 break;
2707 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2708 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2709 retvalue = ARCMSR_MESSAGE_SUCCESS;
2710 }
2711 break;
2712 case ARCMSR_MESSAGE_SAY_HELLO: {
2713 u_int8_t *hello_string = "Hello! I am ARCMSR";
2714 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2715
2716 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2717 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2718 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2719 return ENOIOCTL;
2720 }
2721 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2722 retvalue = ARCMSR_MESSAGE_SUCCESS;
2723 }
2724 break;
2725 case ARCMSR_MESSAGE_SAY_GOODBYE: {
2726 arcmsr_iop_parking(acb);
2727 retvalue = ARCMSR_MESSAGE_SUCCESS;
2728 }
2729 break;
2730 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2731 arcmsr_flush_adapter_cache(acb);
2732 retvalue = ARCMSR_MESSAGE_SUCCESS;
2733 }
2734 break;
2735 }
2736 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2737 return (retvalue);
2738 }
2739 /*
2740 **************************************************************************
2741 **************************************************************************
2742 */
arcmsr_free_srb(struct CommandControlBlock * srb)2743 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2744 {
2745 struct AdapterControlBlock *acb;
2746
2747 acb = srb->acb;
2748 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2749 srb->srb_state = ARCMSR_SRB_DONE;
2750 srb->srb_flags = 0;
2751 acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2752 acb->workingsrb_doneindex++;
2753 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2754 ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2755 }
2756 /*
2757 **************************************************************************
2758 **************************************************************************
2759 */
arcmsr_get_freesrb(struct AdapterControlBlock * acb)2760 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2761 {
2762 struct CommandControlBlock *srb = NULL;
2763 u_int32_t workingsrb_startindex, workingsrb_doneindex;
2764
2765 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2766 workingsrb_doneindex = acb->workingsrb_doneindex;
2767 workingsrb_startindex = acb->workingsrb_startindex;
2768 srb = acb->srbworkingQ[workingsrb_startindex];
2769 workingsrb_startindex++;
2770 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2771 if(workingsrb_doneindex != workingsrb_startindex) {
2772 acb->workingsrb_startindex = workingsrb_startindex;
2773 } else {
2774 srb = NULL;
2775 }
2776 ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2777 return(srb);
2778 }
2779 /*
2780 **************************************************************************
2781 **************************************************************************
2782 */
arcmsr_iop_message_xfer(struct AdapterControlBlock * acb,union ccb * pccb)2783 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2784 {
2785 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2786 int retvalue = 0, transfer_len = 0;
2787 char *buffer;
2788 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio);
2789 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 |
2790 (u_int32_t ) ptr[6] << 16 |
2791 (u_int32_t ) ptr[7] << 8 |
2792 (u_int32_t ) ptr[8];
2793 /* 4 bytes: Areca io control code */
2794 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2795 buffer = pccb->csio.data_ptr;
2796 transfer_len = pccb->csio.dxfer_len;
2797 } else {
2798 retvalue = ARCMSR_MESSAGE_FAIL;
2799 goto message_out;
2800 }
2801 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2802 retvalue = ARCMSR_MESSAGE_FAIL;
2803 goto message_out;
2804 }
2805 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2806 switch(controlcode) {
2807 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2808 u_int8_t *pQbuffer;
2809 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2810 int32_t allxfer_len = 0;
2811
2812 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2813 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2814 && (allxfer_len < 1031)) {
2815 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2816 *ptmpQbuffer = *pQbuffer;
2817 acb->rqbuf_firstindex++;
2818 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2819 ptmpQbuffer++;
2820 allxfer_len++;
2821 }
2822 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2823 struct QBUFFER *prbuffer;
2824
2825 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2826 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2827 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2828 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2829 }
2830 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2831 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2832 retvalue = ARCMSR_MESSAGE_SUCCESS;
2833 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2834 }
2835 break;
2836 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2837 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2838 u_int8_t *pQbuffer;
2839 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2840
2841 user_len = pcmdmessagefld->cmdmessage.Length;
2842 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2843 wqbuf_lastindex = acb->wqbuf_lastindex;
2844 wqbuf_firstindex = acb->wqbuf_firstindex;
2845 if (wqbuf_lastindex != wqbuf_firstindex) {
2846 arcmsr_Write_data_2iop_wqbuffer(acb);
2847 /* has error report sensedata */
2848 if(pccb->csio.sense_len) {
2849 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2850 /* Valid,ErrorCode */
2851 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2852 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2853 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2854 /* AdditionalSenseLength */
2855 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2856 /* AdditionalSenseCode */
2857 }
2858 retvalue = ARCMSR_MESSAGE_FAIL;
2859 } else {
2860 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2861 &(ARCMSR_MAX_QBUFFER - 1);
2862 if (my_empty_len >= user_len) {
2863 while (user_len > 0) {
2864 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2865 *pQbuffer = *ptmpuserbuffer;
2866 acb->wqbuf_lastindex++;
2867 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2868 ptmpuserbuffer++;
2869 user_len--;
2870 }
2871 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2872 acb->acb_flags &=
2873 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2874 arcmsr_Write_data_2iop_wqbuffer(acb);
2875 }
2876 } else {
2877 /* has error report sensedata */
2878 if(pccb->csio.sense_len) {
2879 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2880 /* Valid,ErrorCode */
2881 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2882 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2883 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2884 /* AdditionalSenseLength */
2885 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2886 /* AdditionalSenseCode */
2887 }
2888 retvalue = ARCMSR_MESSAGE_FAIL;
2889 }
2890 }
2891 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2892 }
2893 break;
2894 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2895 u_int8_t *pQbuffer = acb->rqbuffer;
2896
2897 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2898 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2899 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2900 arcmsr_iop_message_read(acb);
2901 }
2902 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2903 acb->rqbuf_firstindex = 0;
2904 acb->rqbuf_lastindex = 0;
2905 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2906 pcmdmessagefld->cmdmessage.ReturnCode =
2907 ARCMSR_MESSAGE_RETURNCODE_OK;
2908 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2909 }
2910 break;
2911 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2912 u_int8_t *pQbuffer = acb->wqbuffer;
2913
2914 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2915 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2916 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2917 arcmsr_iop_message_read(acb);
2918 }
2919 acb->acb_flags |=
2920 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2921 ACB_F_MESSAGE_WQBUFFER_READ);
2922 acb->wqbuf_firstindex = 0;
2923 acb->wqbuf_lastindex = 0;
2924 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2925 pcmdmessagefld->cmdmessage.ReturnCode =
2926 ARCMSR_MESSAGE_RETURNCODE_OK;
2927 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2928 }
2929 break;
2930 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2931 u_int8_t *pQbuffer;
2932
2933 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2934 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2935 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2936 arcmsr_iop_message_read(acb);
2937 }
2938 acb->acb_flags |=
2939 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2940 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2941 | ACB_F_MESSAGE_WQBUFFER_READ);
2942 acb->rqbuf_firstindex = 0;
2943 acb->rqbuf_lastindex = 0;
2944 acb->wqbuf_firstindex = 0;
2945 acb->wqbuf_lastindex = 0;
2946 pQbuffer = acb->rqbuffer;
2947 memset(pQbuffer, 0, sizeof (struct QBUFFER));
2948 pQbuffer = acb->wqbuffer;
2949 memset(pQbuffer, 0, sizeof (struct QBUFFER));
2950 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2951 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2952 }
2953 break;
2954 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2955 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2956 }
2957 break;
2958 case ARCMSR_MESSAGE_SAY_HELLO: {
2959 int8_t *hello_string = "Hello! I am ARCMSR";
2960
2961 memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2962 , (int16_t)strlen(hello_string));
2963 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2964 }
2965 break;
2966 case ARCMSR_MESSAGE_SAY_GOODBYE:
2967 arcmsr_iop_parking(acb);
2968 break;
2969 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2970 arcmsr_flush_adapter_cache(acb);
2971 break;
2972 default:
2973 retvalue = ARCMSR_MESSAGE_FAIL;
2974 }
2975 message_out:
2976 return (retvalue);
2977 }
2978 /*
2979 *********************************************************************
2980 *********************************************************************
2981 */
arcmsr_execute_srb(void * arg,bus_dma_segment_t * dm_segs,int nseg,int error)2982 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2983 {
2984 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2985 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2986 union ccb *pccb;
2987 int target, lun;
2988
2989 pccb = srb->pccb;
2990 target = pccb->ccb_h.target_id;
2991 lun = pccb->ccb_h.target_lun;
2992 acb->pktRequestCount++;
2993 if(error != 0) {
2994 if(error != EFBIG) {
2995 printf("arcmsr%d: unexpected error %x"
2996 " returned from 'bus_dmamap_load' \n"
2997 , acb->pci_unit, error);
2998 }
2999 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
3000 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
3001 }
3002 arcmsr_srb_complete(srb, 0);
3003 return;
3004 }
3005 if(nseg > ARCMSR_MAX_SG_ENTRIES) {
3006 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
3007 arcmsr_srb_complete(srb, 0);
3008 return;
3009 }
3010 if(acb->acb_flags & ACB_F_BUS_RESET) {
3011 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
3012 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
3013 arcmsr_srb_complete(srb, 0);
3014 return;
3015 }
3016 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
3017 u_int8_t block_cmd, cmd;
3018
3019 cmd = scsiio_cdb_ptr(&pccb->csio)[0];
3020 block_cmd = cmd & 0x0f;
3021 if(block_cmd == 0x08 || block_cmd == 0x0a) {
3022 printf("arcmsr%d:block 'read/write' command "
3023 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
3024 , acb->pci_unit, cmd, target, lun);
3025 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
3026 arcmsr_srb_complete(srb, 0);
3027 return;
3028 }
3029 }
3030 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
3031 if(nseg != 0) {
3032 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
3033 }
3034 arcmsr_srb_complete(srb, 0);
3035 return;
3036 }
3037 if(acb->srboutstandingcount >= acb->maxOutstanding) {
3038 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
3039 {
3040 xpt_freeze_simq(acb->psim, 1);
3041 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
3042 }
3043 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
3044 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
3045 arcmsr_srb_complete(srb, 0);
3046 return;
3047 }
3048 pccb->ccb_h.status |= CAM_SIM_QUEUED;
3049 arcmsr_build_srb(srb, dm_segs, nseg);
3050 arcmsr_post_srb(acb, srb);
3051 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
3052 {
3053 arcmsr_callout_init(&srb->ccb_callout);
3054 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
3055 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
3056 arcmsr_srb_timeout, srb, 0);
3057 srb->srb_flags |= SRB_FLAG_TIMER_START;
3058 }
3059 }
3060 /*
3061 *****************************************************************************************
3062 *****************************************************************************************
3063 */
arcmsr_seek_cmd2abort(union ccb * abortccb)3064 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
3065 {
3066 struct CommandControlBlock *srb;
3067 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
3068 u_int32_t intmask_org;
3069 int i = 0;
3070
3071 acb->num_aborts++;
3072 /*
3073 ***************************************************************************
3074 ** It is the upper layer do abort command this lock just prior to calling us.
3075 ** First determine if we currently own this command.
3076 ** Start by searching the device queue. If not found
3077 ** at all, and the system wanted us to just abort the
3078 ** command return success.
3079 ***************************************************************************
3080 */
3081 if(acb->srboutstandingcount != 0) {
3082 /* disable all outbound interrupt */
3083 intmask_org = arcmsr_disable_allintr(acb);
3084 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3085 srb = acb->psrb_pool[i];
3086 if(srb->srb_state == ARCMSR_SRB_START) {
3087 if(srb->pccb == abortccb) {
3088 srb->srb_state = ARCMSR_SRB_ABORTED;
3089 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
3090 "outstanding command \n"
3091 , acb->pci_unit, abortccb->ccb_h.target_id
3092 , (uintmax_t)abortccb->ccb_h.target_lun, srb);
3093 arcmsr_polling_srbdone(acb, srb);
3094 /* enable outbound Post Queue, outbound doorbell Interrupt */
3095 arcmsr_enable_allintr(acb, intmask_org);
3096 return (TRUE);
3097 }
3098 }
3099 }
3100 /* enable outbound Post Queue, outbound doorbell Interrupt */
3101 arcmsr_enable_allintr(acb, intmask_org);
3102 }
3103 return(FALSE);
3104 }
3105 /*
3106 ****************************************************************************
3107 ****************************************************************************
3108 */
arcmsr_bus_reset(struct AdapterControlBlock * acb)3109 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
3110 {
3111 int retry = 0;
3112
3113 acb->num_resets++;
3114 acb->acb_flags |= ACB_F_BUS_RESET;
3115 while(acb->srboutstandingcount != 0 && retry < 400) {
3116 arcmsr_interrupt(acb);
3117 UDELAY(25000);
3118 retry++;
3119 }
3120 arcmsr_iop_reset(acb);
3121 acb->acb_flags &= ~ACB_F_BUS_RESET;
3122 }
3123 /*
3124 **************************************************************************
3125 **************************************************************************
3126 */
arcmsr_handle_virtual_command(struct AdapterControlBlock * acb,union ccb * pccb)3127 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
3128 union ccb *pccb)
3129 {
3130 if (pccb->ccb_h.target_lun) {
3131 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
3132 xpt_done(pccb);
3133 return;
3134 }
3135 pccb->ccb_h.status |= CAM_REQ_CMP;
3136 switch (scsiio_cdb_ptr(&pccb->csio)[0]) {
3137 case INQUIRY: {
3138 unsigned char inqdata[36];
3139 char *buffer = pccb->csio.data_ptr;
3140
3141 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */
3142 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */
3143 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */
3144 inqdata[3] = 0;
3145 inqdata[4] = 31; /* length of additional data */
3146 inqdata[5] = 0;
3147 inqdata[6] = 0;
3148 inqdata[7] = 0;
3149 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */
3150 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */
3151 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
3152 memcpy(buffer, inqdata, sizeof(inqdata));
3153 xpt_done(pccb);
3154 }
3155 break;
3156 case WRITE_BUFFER:
3157 case READ_BUFFER: {
3158 if (arcmsr_iop_message_xfer(acb, pccb)) {
3159 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
3160 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
3161 }
3162 xpt_done(pccb);
3163 }
3164 break;
3165 default:
3166 xpt_done(pccb);
3167 }
3168 }
3169 /*
3170 *********************************************************************
3171 *********************************************************************
3172 */
arcmsr_action(struct cam_sim * psim,union ccb * pccb)3173 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
3174 {
3175 struct AdapterControlBlock *acb;
3176
3177 acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
3178 if(acb == NULL) {
3179 pccb->ccb_h.status |= CAM_REQ_INVALID;
3180 xpt_done(pccb);
3181 return;
3182 }
3183 switch (pccb->ccb_h.func_code) {
3184 case XPT_SCSI_IO: {
3185 struct CommandControlBlock *srb;
3186 int target = pccb->ccb_h.target_id;
3187 int error;
3188
3189 if (pccb->ccb_h.flags & CAM_CDB_PHYS) {
3190 pccb->ccb_h.status = CAM_REQ_INVALID;
3191 xpt_done(pccb);
3192 return;
3193 }
3194
3195 if(target == 16) {
3196 /* virtual device for iop message transfer */
3197 arcmsr_handle_virtual_command(acb, pccb);
3198 return;
3199 }
3200 if((srb = arcmsr_get_freesrb(acb)) == NULL) {
3201 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
3202 xpt_done(pccb);
3203 return;
3204 }
3205 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
3206 pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
3207 srb->pccb = pccb;
3208 error = bus_dmamap_load_ccb(acb->dm_segs_dmat
3209 , srb->dm_segs_dmamap
3210 , pccb
3211 , arcmsr_execute_srb, srb, /*flags*/0);
3212 if(error == EINPROGRESS) {
3213 xpt_freeze_simq(acb->psim, 1);
3214 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
3215 }
3216 break;
3217 }
3218 case XPT_PATH_INQ: {
3219 struct ccb_pathinq *cpi = &pccb->cpi;
3220
3221 cpi->version_num = 1;
3222 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
3223 cpi->target_sprt = 0;
3224 cpi->hba_misc = 0;
3225 cpi->hba_eng_cnt = 0;
3226 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */
3227 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */
3228 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
3229 cpi->bus_id = cam_sim_bus(psim);
3230 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
3231 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
3232 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
3233 cpi->unit_number = cam_sim_unit(psim);
3234 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3235 cpi->base_transfer_speed = 1200000;
3236 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3237 cpi->base_transfer_speed = 600000;
3238 else
3239 cpi->base_transfer_speed = 300000;
3240 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3241 (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3242 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3243 (acb->vendor_device_id == PCIDevVenIDARC1214))
3244 {
3245 cpi->transport = XPORT_SAS;
3246 cpi->transport_version = 0;
3247 cpi->protocol_version = SCSI_REV_SPC2;
3248 }
3249 else
3250 {
3251 cpi->transport = XPORT_SPI;
3252 cpi->transport_version = 2;
3253 cpi->protocol_version = SCSI_REV_2;
3254 }
3255 cpi->protocol = PROTO_SCSI;
3256 cpi->ccb_h.status |= CAM_REQ_CMP;
3257 xpt_done(pccb);
3258 break;
3259 }
3260 case XPT_ABORT: {
3261 union ccb *pabort_ccb;
3262
3263 pabort_ccb = pccb->cab.abort_ccb;
3264 switch (pabort_ccb->ccb_h.func_code) {
3265 case XPT_ACCEPT_TARGET_IO:
3266 case XPT_CONT_TARGET_IO:
3267 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
3268 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
3269 xpt_done(pabort_ccb);
3270 pccb->ccb_h.status |= CAM_REQ_CMP;
3271 } else {
3272 xpt_print_path(pabort_ccb->ccb_h.path);
3273 printf("Not found\n");
3274 pccb->ccb_h.status |= CAM_PATH_INVALID;
3275 }
3276 break;
3277 case XPT_SCSI_IO:
3278 pccb->ccb_h.status |= CAM_UA_ABORT;
3279 break;
3280 default:
3281 pccb->ccb_h.status |= CAM_REQ_INVALID;
3282 break;
3283 }
3284 xpt_done(pccb);
3285 break;
3286 }
3287 case XPT_RESET_BUS:
3288 case XPT_RESET_DEV: {
3289 u_int32_t i;
3290
3291 arcmsr_bus_reset(acb);
3292 for (i=0; i < 500; i++) {
3293 DELAY(1000);
3294 }
3295 pccb->ccb_h.status |= CAM_REQ_CMP;
3296 xpt_done(pccb);
3297 break;
3298 }
3299 case XPT_TERM_IO: {
3300 pccb->ccb_h.status |= CAM_REQ_INVALID;
3301 xpt_done(pccb);
3302 break;
3303 }
3304 case XPT_GET_TRAN_SETTINGS: {
3305 struct ccb_trans_settings *cts;
3306
3307 if(pccb->ccb_h.target_id == 16) {
3308 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3309 xpt_done(pccb);
3310 break;
3311 }
3312 cts = &pccb->cts;
3313 {
3314 struct ccb_trans_settings_scsi *scsi;
3315 struct ccb_trans_settings_spi *spi;
3316 struct ccb_trans_settings_sas *sas;
3317
3318 scsi = &cts->proto_specific.scsi;
3319 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
3320 scsi->valid = CTS_SCSI_VALID_TQ;
3321 cts->protocol = PROTO_SCSI;
3322
3323 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3324 (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3325 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3326 (acb->vendor_device_id == PCIDevVenIDARC1214))
3327 {
3328 cts->protocol_version = SCSI_REV_SPC2;
3329 cts->transport_version = 0;
3330 cts->transport = XPORT_SAS;
3331 sas = &cts->xport_specific.sas;
3332 sas->valid = CTS_SAS_VALID_SPEED;
3333 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3334 sas->bitrate = 1200000;
3335 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3336 sas->bitrate = 600000;
3337 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G)
3338 sas->bitrate = 300000;
3339 }
3340 else
3341 {
3342 cts->protocol_version = SCSI_REV_2;
3343 cts->transport_version = 2;
3344 cts->transport = XPORT_SPI;
3345 spi = &cts->xport_specific.spi;
3346 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
3347 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3348 spi->sync_period = 1;
3349 else
3350 spi->sync_period = 2;
3351 spi->sync_offset = 32;
3352 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3353 spi->valid = CTS_SPI_VALID_DISC
3354 | CTS_SPI_VALID_SYNC_RATE
3355 | CTS_SPI_VALID_SYNC_OFFSET
3356 | CTS_SPI_VALID_BUS_WIDTH;
3357 }
3358 }
3359 pccb->ccb_h.status |= CAM_REQ_CMP;
3360 xpt_done(pccb);
3361 break;
3362 }
3363 case XPT_SET_TRAN_SETTINGS: {
3364 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3365 xpt_done(pccb);
3366 break;
3367 }
3368 case XPT_CALC_GEOMETRY:
3369 if(pccb->ccb_h.target_id == 16) {
3370 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3371 xpt_done(pccb);
3372 break;
3373 }
3374 cam_calc_geometry(&pccb->ccg, 1);
3375 xpt_done(pccb);
3376 break;
3377 default:
3378 pccb->ccb_h.status |= CAM_REQ_INVALID;
3379 xpt_done(pccb);
3380 break;
3381 }
3382 }
3383 /*
3384 **********************************************************************
3385 **********************************************************************
3386 */
arcmsr_start_hba_bgrb(struct AdapterControlBlock * acb)3387 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3388 {
3389 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3390 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3391 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3392 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3393 }
3394 }
3395 /*
3396 **********************************************************************
3397 **********************************************************************
3398 */
arcmsr_start_hbb_bgrb(struct AdapterControlBlock * acb)3399 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3400 {
3401 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3402 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3403 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
3404 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3405 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3406 }
3407 }
3408 /*
3409 **********************************************************************
3410 **********************************************************************
3411 */
arcmsr_start_hbc_bgrb(struct AdapterControlBlock * acb)3412 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3413 {
3414 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3415 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3416 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3417 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3418 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3419 }
3420 }
3421 /*
3422 **********************************************************************
3423 **********************************************************************
3424 */
arcmsr_start_hbd_bgrb(struct AdapterControlBlock * acb)3425 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3426 {
3427 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3428 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3429 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3430 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3431 }
3432 }
3433 /*
3434 **********************************************************************
3435 **********************************************************************
3436 */
arcmsr_start_hbe_bgrb(struct AdapterControlBlock * acb)3437 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb)
3438 {
3439 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3440 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3441 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3442 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3443 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3444 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3445 }
3446 }
3447 /*
3448 **********************************************************************
3449 **********************************************************************
3450 */
arcmsr_start_adapter_bgrb(struct AdapterControlBlock * acb)3451 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3452 {
3453 switch (acb->adapter_type) {
3454 case ACB_ADAPTER_TYPE_A:
3455 arcmsr_start_hba_bgrb(acb);
3456 break;
3457 case ACB_ADAPTER_TYPE_B:
3458 arcmsr_start_hbb_bgrb(acb);
3459 break;
3460 case ACB_ADAPTER_TYPE_C:
3461 arcmsr_start_hbc_bgrb(acb);
3462 break;
3463 case ACB_ADAPTER_TYPE_D:
3464 arcmsr_start_hbd_bgrb(acb);
3465 break;
3466 case ACB_ADAPTER_TYPE_E:
3467 case ACB_ADAPTER_TYPE_F:
3468 arcmsr_start_hbe_bgrb(acb);
3469 break;
3470 }
3471 }
3472 /*
3473 **********************************************************************
3474 **
3475 **********************************************************************
3476 */
arcmsr_polling_hba_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3477 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3478 {
3479 struct CommandControlBlock *srb;
3480 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3481 u_int16_t error;
3482
3483 polling_ccb_retry:
3484 poll_count++;
3485 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3486 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/
3487 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3488 while(1) {
3489 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3490 0, outbound_queueport)) == 0xFFFFFFFF) {
3491 if(poll_srb_done) {
3492 break;/*chip FIFO no ccb for completion already*/
3493 } else {
3494 UDELAY(25000);
3495 if ((poll_count > 100) && (poll_srb != NULL)) {
3496 break;
3497 }
3498 goto polling_ccb_retry;
3499 }
3500 }
3501 /* check if command done with no error*/
3502 srb = (struct CommandControlBlock *)
3503 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3504 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3505 poll_srb_done = (srb == poll_srb) ? 1:0;
3506 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3507 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3508 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3509 "poll command abort successfully \n"
3510 , acb->pci_unit
3511 , srb->pccb->ccb_h.target_id
3512 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3513 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3514 arcmsr_srb_complete(srb, 1);
3515 continue;
3516 }
3517 printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3518 "srboutstandingcount=%d \n"
3519 , acb->pci_unit
3520 , srb, acb->srboutstandingcount);
3521 continue;
3522 }
3523 arcmsr_report_srb_state(acb, srb, error);
3524 } /*drain reply FIFO*/
3525 }
3526 /*
3527 **********************************************************************
3528 **
3529 **********************************************************************
3530 */
arcmsr_polling_hbb_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3531 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3532 {
3533 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3534 struct CommandControlBlock *srb;
3535 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3536 int index;
3537 u_int16_t error;
3538
3539 polling_ccb_retry:
3540 poll_count++;
3541 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3542 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3543 while(1) {
3544 index = phbbmu->doneq_index;
3545 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3546 if(poll_srb_done) {
3547 break;/*chip FIFO no ccb for completion already*/
3548 } else {
3549 UDELAY(25000);
3550 if ((poll_count > 100) && (poll_srb != NULL)) {
3551 break;
3552 }
3553 goto polling_ccb_retry;
3554 }
3555 }
3556 phbbmu->done_qbuffer[index] = 0;
3557 index++;
3558 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
3559 phbbmu->doneq_index = index;
3560 /* check if command done with no error*/
3561 srb = (struct CommandControlBlock *)
3562 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3563 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3564 poll_srb_done = (srb == poll_srb) ? 1:0;
3565 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3566 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3567 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3568 "poll command abort successfully \n"
3569 , acb->pci_unit
3570 , srb->pccb->ccb_h.target_id
3571 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3572 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3573 arcmsr_srb_complete(srb, 1);
3574 continue;
3575 }
3576 printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3577 "srboutstandingcount=%d \n"
3578 , acb->pci_unit
3579 , srb, acb->srboutstandingcount);
3580 continue;
3581 }
3582 arcmsr_report_srb_state(acb, srb, error);
3583 } /*drain reply FIFO*/
3584 }
3585 /*
3586 **********************************************************************
3587 **
3588 **********************************************************************
3589 */
arcmsr_polling_hbc_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3590 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3591 {
3592 struct CommandControlBlock *srb;
3593 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3594 u_int16_t error;
3595
3596 polling_ccb_retry:
3597 poll_count++;
3598 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3599 while(1) {
3600 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3601 if(poll_srb_done) {
3602 break;/*chip FIFO no ccb for completion already*/
3603 } else {
3604 UDELAY(25000);
3605 if ((poll_count > 100) && (poll_srb != NULL)) {
3606 break;
3607 }
3608 if (acb->srboutstandingcount == 0) {
3609 break;
3610 }
3611 goto polling_ccb_retry;
3612 }
3613 }
3614 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3615 /* check if command done with no error*/
3616 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3617 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3618 if (poll_srb != NULL)
3619 poll_srb_done = (srb == poll_srb) ? 1:0;
3620 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3621 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3622 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3623 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3624 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3625 arcmsr_srb_complete(srb, 1);
3626 continue;
3627 }
3628 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3629 , acb->pci_unit, srb, acb->srboutstandingcount);
3630 continue;
3631 }
3632 arcmsr_report_srb_state(acb, srb, error);
3633 } /*drain reply FIFO*/
3634 }
3635 /*
3636 **********************************************************************
3637 **
3638 **********************************************************************
3639 */
arcmsr_polling_hbd_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3640 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3641 {
3642 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3643 struct CommandControlBlock *srb;
3644 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3645 u_int32_t outbound_write_pointer;
3646 u_int16_t error, doneq_index;
3647
3648 polling_ccb_retry:
3649 poll_count++;
3650 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3651 while(1) {
3652 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3653 doneq_index = phbdmu->doneq_index;
3654 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3655 if(poll_srb_done) {
3656 break;/*chip FIFO no ccb for completion already*/
3657 } else {
3658 UDELAY(25000);
3659 if ((poll_count > 100) && (poll_srb != NULL)) {
3660 break;
3661 }
3662 if (acb->srboutstandingcount == 0) {
3663 break;
3664 }
3665 goto polling_ccb_retry;
3666 }
3667 }
3668 doneq_index = arcmsr_get_doneq_index(phbdmu);
3669 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3670 /* check if command done with no error*/
3671 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3672 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3673 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3674 if (poll_srb != NULL)
3675 poll_srb_done = (srb == poll_srb) ? 1:0;
3676 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3677 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3678 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3679 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3680 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3681 arcmsr_srb_complete(srb, 1);
3682 continue;
3683 }
3684 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3685 , acb->pci_unit, srb, acb->srboutstandingcount);
3686 continue;
3687 }
3688 arcmsr_report_srb_state(acb, srb, error);
3689 } /*drain reply FIFO*/
3690 }
3691 /*
3692 **********************************************************************
3693 **
3694 **********************************************************************
3695 */
arcmsr_polling_hbe_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3696 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3697 {
3698 struct CommandControlBlock *srb;
3699 u_int32_t poll_srb_done=0, poll_count=0, doneq_index;
3700 u_int16_t error, cmdSMID;
3701
3702 polling_ccb_retry:
3703 poll_count++;
3704 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3705 while(1) {
3706 doneq_index = acb->doneq_index;
3707 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) {
3708 if(poll_srb_done) {
3709 break;/*chip FIFO no ccb for completion already*/
3710 } else {
3711 UDELAY(25000);
3712 if ((poll_count > 100) && (poll_srb != NULL)) {
3713 break;
3714 }
3715 if (acb->srboutstandingcount == 0) {
3716 break;
3717 }
3718 goto polling_ccb_retry;
3719 }
3720 }
3721 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3722 doneq_index++;
3723 if (doneq_index >= acb->completionQ_entry)
3724 doneq_index = 0;
3725 acb->doneq_index = doneq_index;
3726 srb = acb->psrb_pool[cmdSMID];
3727 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3728 if (poll_srb != NULL)
3729 poll_srb_done = (srb == poll_srb) ? 1:0;
3730 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3731 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3732 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3733 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3734 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3735 arcmsr_srb_complete(srb, 1);
3736 continue;
3737 }
3738 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3739 , acb->pci_unit, srb, acb->srboutstandingcount);
3740 continue;
3741 }
3742 arcmsr_report_srb_state(acb, srb, error);
3743 } /*drain reply FIFO*/
3744 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index);
3745 }
3746 /*
3747 **********************************************************************
3748 **********************************************************************
3749 */
arcmsr_polling_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3750 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3751 {
3752 switch (acb->adapter_type) {
3753 case ACB_ADAPTER_TYPE_A:
3754 arcmsr_polling_hba_srbdone(acb, poll_srb);
3755 break;
3756 case ACB_ADAPTER_TYPE_B:
3757 arcmsr_polling_hbb_srbdone(acb, poll_srb);
3758 break;
3759 case ACB_ADAPTER_TYPE_C:
3760 arcmsr_polling_hbc_srbdone(acb, poll_srb);
3761 break;
3762 case ACB_ADAPTER_TYPE_D:
3763 arcmsr_polling_hbd_srbdone(acb, poll_srb);
3764 break;
3765 case ACB_ADAPTER_TYPE_E:
3766 case ACB_ADAPTER_TYPE_F:
3767 arcmsr_polling_hbe_srbdone(acb, poll_srb);
3768 break;
3769 }
3770 }
3771 /*
3772 **********************************************************************
3773 **********************************************************************
3774 */
arcmsr_get_hba_config(struct AdapterControlBlock * acb)3775 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3776 {
3777 char *acb_firm_model = acb->firm_model;
3778 char *acb_firm_version = acb->firm_version;
3779 char *acb_device_map = acb->device_map;
3780 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3781 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3782 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3783 int i;
3784
3785 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3786 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3787 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3788 }
3789 i = 0;
3790 while(i < 8) {
3791 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3792 /* 8 bytes firm_model, 15, 60-67*/
3793 acb_firm_model++;
3794 i++;
3795 }
3796 i=0;
3797 while(i < 16) {
3798 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3799 /* 16 bytes firm_version, 17, 68-83*/
3800 acb_firm_version++;
3801 i++;
3802 }
3803 i=0;
3804 while(i < 16) {
3805 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3806 acb_device_map++;
3807 i++;
3808 }
3809 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3810 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3811 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3812 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3813 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3814 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3815 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3816 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3817 else
3818 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3819 }
3820 /*
3821 **********************************************************************
3822 **********************************************************************
3823 */
arcmsr_get_hbb_config(struct AdapterControlBlock * acb)3824 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3825 {
3826 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3827 char *acb_firm_model = acb->firm_model;
3828 char *acb_firm_version = acb->firm_version;
3829 char *acb_device_map = acb->device_map;
3830 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3831 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3832 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3833 int i;
3834
3835 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3836 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3837 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3838 }
3839 i = 0;
3840 while(i < 8) {
3841 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3842 /* 8 bytes firm_model, 15, 60-67*/
3843 acb_firm_model++;
3844 i++;
3845 }
3846 i = 0;
3847 while(i < 16) {
3848 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3849 /* 16 bytes firm_version, 17, 68-83*/
3850 acb_firm_version++;
3851 i++;
3852 }
3853 i = 0;
3854 while(i < 16) {
3855 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3856 acb_device_map++;
3857 i++;
3858 }
3859 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3860 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3861 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3862 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3863 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3864 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3865 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3866 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3867 else
3868 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3869 }
3870 /*
3871 **********************************************************************
3872 **********************************************************************
3873 */
arcmsr_get_hbc_config(struct AdapterControlBlock * acb)3874 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3875 {
3876 char *acb_firm_model = acb->firm_model;
3877 char *acb_firm_version = acb->firm_version;
3878 char *acb_device_map = acb->device_map;
3879 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3880 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3881 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3882 int i;
3883
3884 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3885 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3886 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3887 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3888 }
3889 i = 0;
3890 while(i < 8) {
3891 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3892 /* 8 bytes firm_model, 15, 60-67*/
3893 acb_firm_model++;
3894 i++;
3895 }
3896 i = 0;
3897 while(i < 16) {
3898 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3899 /* 16 bytes firm_version, 17, 68-83*/
3900 acb_firm_version++;
3901 i++;
3902 }
3903 i = 0;
3904 while(i < 16) {
3905 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3906 acb_device_map++;
3907 i++;
3908 }
3909 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3910 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3911 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3912 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3913 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3914 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3915 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3916 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3917 else
3918 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3919 }
3920 /*
3921 **********************************************************************
3922 **********************************************************************
3923 */
arcmsr_get_hbd_config(struct AdapterControlBlock * acb)3924 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3925 {
3926 char *acb_firm_model = acb->firm_model;
3927 char *acb_firm_version = acb->firm_version;
3928 char *acb_device_map = acb->device_map;
3929 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3930 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3931 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3932 int i;
3933
3934 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3935 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3936 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3937 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3938 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3939 }
3940 i = 0;
3941 while(i < 8) {
3942 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3943 /* 8 bytes firm_model, 15, 60-67*/
3944 acb_firm_model++;
3945 i++;
3946 }
3947 i = 0;
3948 while(i < 16) {
3949 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3950 /* 16 bytes firm_version, 17, 68-83*/
3951 acb_firm_version++;
3952 i++;
3953 }
3954 i = 0;
3955 while(i < 16) {
3956 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3957 acb_device_map++;
3958 i++;
3959 }
3960 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3961 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3962 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3963 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3964 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3965 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3966 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3967 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3968 else
3969 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3970 }
3971 /*
3972 **********************************************************************
3973 **********************************************************************
3974 */
arcmsr_get_hbe_config(struct AdapterControlBlock * acb)3975 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb)
3976 {
3977 char *acb_firm_model = acb->firm_model;
3978 char *acb_firm_version = acb->firm_version;
3979 char *acb_device_map = acb->device_map;
3980 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3981 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3982 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3983 int i;
3984
3985 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3986 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3987 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3988 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3989 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3990 }
3991
3992 i = 0;
3993 while(i < 8) {
3994 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3995 /* 8 bytes firm_model, 15, 60-67*/
3996 acb_firm_model++;
3997 i++;
3998 }
3999 i = 0;
4000 while(i < 16) {
4001 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
4002 /* 16 bytes firm_version, 17, 68-83*/
4003 acb_firm_version++;
4004 i++;
4005 }
4006 i = 0;
4007 while(i < 16) {
4008 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
4009 acb_device_map++;
4010 i++;
4011 }
4012 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
4013 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
4014 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
4015 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
4016 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
4017 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
4018 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
4019 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
4020 else
4021 acb->maxOutstanding = acb->firm_numbers_queue - 1;
4022 }
4023 /*
4024 **********************************************************************
4025 **********************************************************************
4026 */
arcmsr_get_hbf_config(struct AdapterControlBlock * acb)4027 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb)
4028 {
4029 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model;
4030 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version;
4031 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map;
4032 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/
4033 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/
4034 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET;
4035 int i;
4036
4037 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
4038 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4039 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4040 if(!arcmsr_hbe_wait_msgint_ready(acb))
4041 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
4042
4043 i = 0;
4044 while(i < 2) {
4045 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model];
4046 /* 8 bytes firm_model, 15, 60-67*/
4047 acb_firm_model++;
4048 iop_firm_model++;
4049 i++;
4050 }
4051 i = 0;
4052 while(i < 4) {
4053 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version];
4054 /* 16 bytes firm_version, 17, 68-83*/
4055 acb_firm_version++;
4056 iop_firm_version++;
4057 i++;
4058 }
4059 i = 0;
4060 while(i < 4) {
4061 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map];
4062 acb_device_map++;
4063 iop_device_map++;
4064 i++;
4065 }
4066 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
4067 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/
4068 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/
4069 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/
4070 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/
4071 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/
4072 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
4073 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
4074 else
4075 acb->maxOutstanding = acb->firm_numbers_queue - 1;
4076 }
4077 /*
4078 **********************************************************************
4079 **********************************************************************
4080 */
arcmsr_get_firmware_spec(struct AdapterControlBlock * acb)4081 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
4082 {
4083 switch (acb->adapter_type) {
4084 case ACB_ADAPTER_TYPE_A:
4085 arcmsr_get_hba_config(acb);
4086 break;
4087 case ACB_ADAPTER_TYPE_B:
4088 arcmsr_get_hbb_config(acb);
4089 break;
4090 case ACB_ADAPTER_TYPE_C:
4091 arcmsr_get_hbc_config(acb);
4092 break;
4093 case ACB_ADAPTER_TYPE_D:
4094 arcmsr_get_hbd_config(acb);
4095 break;
4096 case ACB_ADAPTER_TYPE_E:
4097 arcmsr_get_hbe_config(acb);
4098 break;
4099 case ACB_ADAPTER_TYPE_F:
4100 arcmsr_get_hbf_config(acb);
4101 break;
4102 }
4103 }
4104 /*
4105 **********************************************************************
4106 **********************************************************************
4107 */
arcmsr_wait_firmware_ready(struct AdapterControlBlock * acb)4108 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
4109 {
4110 int timeout=0;
4111
4112 switch (acb->adapter_type) {
4113 case ACB_ADAPTER_TYPE_A: {
4114 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
4115 {
4116 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4117 {
4118 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
4119 return;
4120 }
4121 UDELAY(15000); /* wait 15 milli-seconds */
4122 }
4123 }
4124 break;
4125 case ACB_ADAPTER_TYPE_B: {
4126 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4127 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
4128 {
4129 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4130 {
4131 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
4132 return;
4133 }
4134 UDELAY(15000); /* wait 15 milli-seconds */
4135 }
4136 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
4137 }
4138 break;
4139 case ACB_ADAPTER_TYPE_C: {
4140 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
4141 {
4142 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4143 {
4144 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4145 return;
4146 }
4147 UDELAY(15000); /* wait 15 milli-seconds */
4148 }
4149 }
4150 break;
4151 case ACB_ADAPTER_TYPE_D: {
4152 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
4153 {
4154 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4155 {
4156 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4157 return;
4158 }
4159 UDELAY(15000); /* wait 15 milli-seconds */
4160 }
4161 }
4162 break;
4163 case ACB_ADAPTER_TYPE_E:
4164 case ACB_ADAPTER_TYPE_F: {
4165 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
4166 {
4167 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
4168 {
4169 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4170 return;
4171 }
4172 UDELAY(15000); /* wait 15 milli-seconds */
4173 }
4174 }
4175 break;
4176 }
4177 }
4178 /*
4179 **********************************************************************
4180 **********************************************************************
4181 */
arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock * acb)4182 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
4183 {
4184 u_int32_t outbound_doorbell;
4185
4186 switch (acb->adapter_type) {
4187 case ACB_ADAPTER_TYPE_A: {
4188 /* empty doorbell Qbuffer if door bell ringed */
4189 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
4190 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
4191 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
4192 }
4193 break;
4194 case ACB_ADAPTER_TYPE_B: {
4195 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4196 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
4197 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
4198 /* let IOP know data has been read */
4199 }
4200 break;
4201 case ACB_ADAPTER_TYPE_C: {
4202 /* empty doorbell Qbuffer if door bell ringed */
4203 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
4204 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */
4205 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
4206 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
4207 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
4208 }
4209 break;
4210 case ACB_ADAPTER_TYPE_D: {
4211 /* empty doorbell Qbuffer if door bell ringed */
4212 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
4213 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
4214 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
4215 }
4216 break;
4217 case ACB_ADAPTER_TYPE_E:
4218 case ACB_ADAPTER_TYPE_F: {
4219 /* empty doorbell Qbuffer if door bell ringed */
4220 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
4221 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */
4222 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4223 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4224 }
4225 break;
4226 }
4227 }
4228 /*
4229 ************************************************************************
4230 ************************************************************************
4231 */
arcmsr_iop_confirm(struct AdapterControlBlock * acb)4232 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
4233 {
4234 unsigned long srb_phyaddr;
4235 u_int32_t srb_phyaddr_hi32;
4236 u_int32_t srb_phyaddr_lo32;
4237
4238 /*
4239 ********************************************************************
4240 ** here we need to tell iop 331 our freesrb.HighPart
4241 ** if freesrb.HighPart is not zero
4242 ********************************************************************
4243 */
4244 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
4245 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
4246 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
4247 switch (acb->adapter_type) {
4248 case ACB_ADAPTER_TYPE_A: {
4249 if(srb_phyaddr_hi32 != 0) {
4250 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4251 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4252 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4253 if(!arcmsr_hba_wait_msgint_ready(acb)) {
4254 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4255 return FALSE;
4256 }
4257 }
4258 }
4259 break;
4260 /*
4261 ***********************************************************************
4262 ** if adapter type B, set window of "post command Q"
4263 ***********************************************************************
4264 */
4265 case ACB_ADAPTER_TYPE_B: {
4266 u_int32_t post_queue_phyaddr;
4267 struct HBB_MessageUnit *phbbmu;
4268
4269 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4270 phbbmu->postq_index = 0;
4271 phbbmu->doneq_index = 0;
4272 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
4273 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4274 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
4275 return FALSE;
4276 }
4277 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
4278 + offsetof(struct HBB_MessageUnit, post_qbuffer);
4279 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4280 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
4281 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
4282 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
4283 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
4284 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
4285 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4286 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
4287 return FALSE;
4288 }
4289 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
4290 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4291 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
4292 return FALSE;
4293 }
4294 }
4295 break;
4296 case ACB_ADAPTER_TYPE_C: {
4297 if(srb_phyaddr_hi32 != 0) {
4298 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4299 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4300 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4301 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
4302 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
4303 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4304 return FALSE;
4305 }
4306 }
4307 }
4308 break;
4309 case ACB_ADAPTER_TYPE_D: {
4310 u_int32_t post_queue_phyaddr, done_queue_phyaddr;
4311 struct HBD_MessageUnit0 *phbdmu;
4312
4313 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4314 phbdmu->postq_index = 0;
4315 phbdmu->doneq_index = 0x40FF;
4316 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4317 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
4318 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4319 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
4320 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4321 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4322 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
4323 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
4324 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
4325 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4326 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
4327 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4328 return FALSE;
4329 }
4330 }
4331 break;
4332 case ACB_ADAPTER_TYPE_E: {
4333 u_int32_t cdb_phyaddr_lo32;
4334 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4335 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4336 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884);
4337 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32);
4338 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32);
4339 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE);
4340 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4341 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32);
4342 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32);
4343 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE);
4344 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4345 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4346 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4347 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4348 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4349 return FALSE;
4350 }
4351 }
4352 break;
4353 case ACB_ADAPTER_TYPE_F: {
4354 u_int32_t cdb_phyaddr_lo32;
4355 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4356 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
4357 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
4358 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32;
4359 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32;
4360 acb->msgcode_rwbuffer[4] = SRB_SIZE;
4361 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4362 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32;
4363 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32;
4364 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE;
4365 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4366 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4367 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4368 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4369 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4370 return FALSE;
4371 }
4372 }
4373 break;
4374 }
4375 return (TRUE);
4376 }
4377 /*
4378 ************************************************************************
4379 ************************************************************************
4380 */
arcmsr_enable_eoi_mode(struct AdapterControlBlock * acb)4381 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4382 {
4383 if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
4384 {
4385 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4386 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
4387 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4388 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
4389 return;
4390 }
4391 }
4392 }
4393 /*
4394 **********************************************************************
4395 **********************************************************************
4396 */
arcmsr_iop_init(struct AdapterControlBlock * acb)4397 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4398 {
4399 u_int32_t intmask_org;
4400
4401 /* disable all outbound interrupt */
4402 intmask_org = arcmsr_disable_allintr(acb);
4403 arcmsr_wait_firmware_ready(acb);
4404 arcmsr_iop_confirm(acb);
4405 arcmsr_get_firmware_spec(acb);
4406 /*start background rebuild*/
4407 arcmsr_start_adapter_bgrb(acb);
4408 /* empty doorbell Qbuffer if door bell ringed */
4409 arcmsr_clear_doorbell_queue_buffer(acb);
4410 arcmsr_enable_eoi_mode(acb);
4411 /* enable outbound Post Queue, outbound doorbell Interrupt */
4412 arcmsr_enable_allintr(acb, intmask_org);
4413 acb->acb_flags |= ACB_F_IOP_INITED;
4414 }
4415 /*
4416 **********************************************************************
4417 **********************************************************************
4418 */
arcmsr_map_free_srb(void * arg,bus_dma_segment_t * segs,int nseg,int error)4419 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4420 {
4421 struct AdapterControlBlock *acb = arg;
4422 struct CommandControlBlock *srb_tmp;
4423 u_int32_t i;
4424 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
4425
4426 acb->srb_phyaddr.phyaddr = srb_phyaddr;
4427 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
4428 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4429 if(bus_dmamap_create(acb->dm_segs_dmat,
4430 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
4431 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
4432 printf("arcmsr%d:"
4433 " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
4434 return;
4435 }
4436 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
4437 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F))
4438 {
4439 srb_tmp->cdb_phyaddr_low = srb_phyaddr;
4440 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
4441 }
4442 else
4443 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
4444 srb_tmp->acb = acb;
4445 srb_tmp->smid = i << 16;
4446 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
4447 srb_phyaddr = srb_phyaddr + SRB_SIZE;
4448 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
4449 }
4450 if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
4451 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4452 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) {
4453 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4454 acb->completeQ_phys = srb_phyaddr;
4455 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE);
4456 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE);
4457 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100);
4458 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200);
4459 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
4460 }
4461 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
4462 }
4463 /*
4464 ************************************************************************
4465 ************************************************************************
4466 */
arcmsr_free_resource(struct AdapterControlBlock * acb)4467 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
4468 {
4469 /* remove the control device */
4470 if(acb->ioctl_dev != NULL) {
4471 destroy_dev(acb->ioctl_dev);
4472 }
4473 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
4474 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
4475 bus_dma_tag_destroy(acb->srb_dmat);
4476 bus_dma_tag_destroy(acb->dm_segs_dmat);
4477 bus_dma_tag_destroy(acb->parent_dmat);
4478 }
4479 /*
4480 ************************************************************************
4481 ************************************************************************
4482 */
arcmsr_mutex_init(struct AdapterControlBlock * acb)4483 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
4484 {
4485 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
4486 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
4487 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
4488 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
4489 }
4490 /*
4491 ************************************************************************
4492 ************************************************************************
4493 */
arcmsr_mutex_destroy(struct AdapterControlBlock * acb)4494 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
4495 {
4496 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
4497 ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
4498 ARCMSR_LOCK_DESTROY(&acb->srb_lock);
4499 ARCMSR_LOCK_DESTROY(&acb->isr_lock);
4500 }
4501 /*
4502 ************************************************************************
4503 ************************************************************************
4504 */
arcmsr_initialize(device_t dev)4505 static u_int32_t arcmsr_initialize(device_t dev)
4506 {
4507 struct AdapterControlBlock *acb = device_get_softc(dev);
4508 u_int16_t pci_command;
4509 int i, j,max_coherent_size;
4510 u_int32_t vendor_dev_id;
4511
4512 vendor_dev_id = pci_get_devid(dev);
4513 acb->vendor_device_id = vendor_dev_id;
4514 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4515 switch (vendor_dev_id) {
4516 case PCIDevVenIDARC1880:
4517 case PCIDevVenIDARC1882:
4518 case PCIDevVenIDARC1213:
4519 case PCIDevVenIDARC1223: {
4520 acb->adapter_type = ACB_ADAPTER_TYPE_C;
4521 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) ||
4522 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) ||
4523 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226))
4524 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4525 else
4526 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4527 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4528 }
4529 break;
4530 case PCIDevVenIDARC1884:
4531 acb->adapter_type = ACB_ADAPTER_TYPE_E;
4532 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4533 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
4534 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4535 break;
4536 case PCIDevVenIDARC1886_:
4537 case PCIDevVenIDARC1886:
4538 acb->adapter_type = ACB_ADAPTER_TYPE_F;
4539 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4540 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE;
4541 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4542 break;
4543 case PCIDevVenIDARC1214: {
4544 acb->adapter_type = ACB_ADAPTER_TYPE_D;
4545 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4546 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
4547 }
4548 break;
4549 case PCIDevVenIDARC1200:
4550 case PCIDevVenIDARC1201: {
4551 acb->adapter_type = ACB_ADAPTER_TYPE_B;
4552 acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4553 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4554 }
4555 break;
4556 case PCIDevVenIDARC1203: {
4557 acb->adapter_type = ACB_ADAPTER_TYPE_B;
4558 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4559 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4560 }
4561 break;
4562 case PCIDevVenIDARC1110:
4563 case PCIDevVenIDARC1120:
4564 case PCIDevVenIDARC1130:
4565 case PCIDevVenIDARC1160:
4566 case PCIDevVenIDARC1170:
4567 case PCIDevVenIDARC1210:
4568 case PCIDevVenIDARC1220:
4569 case PCIDevVenIDARC1230:
4570 case PCIDevVenIDARC1231:
4571 case PCIDevVenIDARC1260:
4572 case PCIDevVenIDARC1261:
4573 case PCIDevVenIDARC1270:
4574 case PCIDevVenIDARC1280:
4575 case PCIDevVenIDARC1212:
4576 case PCIDevVenIDARC1222:
4577 case PCIDevVenIDARC1380:
4578 case PCIDevVenIDARC1381:
4579 case PCIDevVenIDARC1680:
4580 case PCIDevVenIDARC1681: {
4581 acb->adapter_type = ACB_ADAPTER_TYPE_A;
4582 acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4583 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4584 }
4585 break;
4586 default: {
4587 printf("arcmsr%d:"
4588 " unknown RAID adapter type \n", device_get_unit(dev));
4589 return ENOMEM;
4590 }
4591 }
4592 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev),
4593 /*alignemnt*/ 1,
4594 /*boundary*/ 0,
4595 /*lowaddr*/ BUS_SPACE_MAXADDR,
4596 /*highaddr*/ BUS_SPACE_MAXADDR,
4597 /*filter*/ NULL,
4598 /*filterarg*/ NULL,
4599 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT,
4600 /*nsegments*/ BUS_SPACE_UNRESTRICTED,
4601 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4602 /*flags*/ 0,
4603 /*lockfunc*/ NULL,
4604 /*lockarg*/ NULL,
4605 &acb->parent_dmat) != 0)
4606 {
4607 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4608 return ENOMEM;
4609 }
4610
4611 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4612 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
4613 /*alignment*/ 1,
4614 /*boundary*/ 0,
4615 #ifdef PAE
4616 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
4617 #else
4618 /*lowaddr*/ BUS_SPACE_MAXADDR,
4619 #endif
4620 /*highaddr*/ BUS_SPACE_MAXADDR,
4621 /*filter*/ NULL,
4622 /*filterarg*/ NULL,
4623 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4624 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES,
4625 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4626 /*flags*/ 0,
4627 /*lockfunc*/ busdma_lock_mutex,
4628 /*lockarg*/ &acb->isr_lock,
4629 &acb->dm_segs_dmat) != 0)
4630 {
4631 bus_dma_tag_destroy(acb->parent_dmat);
4632 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4633 return ENOMEM;
4634 }
4635
4636 /* DMA tag for our srb structures.... Allocate the freesrb memory */
4637 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
4638 /*alignment*/ 0x20,
4639 /*boundary*/ 0,
4640 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
4641 /*highaddr*/ BUS_SPACE_MAXADDR,
4642 /*filter*/ NULL,
4643 /*filterarg*/ NULL,
4644 /*maxsize*/ max_coherent_size,
4645 /*nsegments*/ 1,
4646 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4647 /*flags*/ 0,
4648 /*lockfunc*/ NULL,
4649 /*lockarg*/ NULL,
4650 &acb->srb_dmat) != 0)
4651 {
4652 bus_dma_tag_destroy(acb->dm_segs_dmat);
4653 bus_dma_tag_destroy(acb->parent_dmat);
4654 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4655 return ENXIO;
4656 }
4657 /* Allocation for our srbs */
4658 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4659 bus_dma_tag_destroy(acb->srb_dmat);
4660 bus_dma_tag_destroy(acb->dm_segs_dmat);
4661 bus_dma_tag_destroy(acb->parent_dmat);
4662 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4663 return ENXIO;
4664 }
4665 /* And permanently map them */
4666 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4667 bus_dma_tag_destroy(acb->srb_dmat);
4668 bus_dma_tag_destroy(acb->dm_segs_dmat);
4669 bus_dma_tag_destroy(acb->parent_dmat);
4670 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4671 return ENXIO;
4672 }
4673 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4674 pci_command |= PCIM_CMD_BUSMASTEREN;
4675 pci_command |= PCIM_CMD_PERRESPEN;
4676 pci_command |= PCIM_CMD_MWRICEN;
4677 /* Enable Busmaster */
4678 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4679 switch(acb->adapter_type) {
4680 case ACB_ADAPTER_TYPE_A: {
4681 u_int32_t rid0 = PCIR_BAR(0);
4682 vm_offset_t mem_base0;
4683
4684 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4685 if(acb->sys_res_arcmsr[0] == NULL) {
4686 arcmsr_free_resource(acb);
4687 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4688 return ENOMEM;
4689 }
4690 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4691 arcmsr_free_resource(acb);
4692 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4693 return ENXIO;
4694 }
4695 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4696 if(mem_base0 == 0) {
4697 arcmsr_free_resource(acb);
4698 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4699 return ENXIO;
4700 }
4701 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4702 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4703 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4704 acb->rid[0] = rid0;
4705 }
4706 break;
4707 case ACB_ADAPTER_TYPE_B: {
4708 struct HBB_MessageUnit *phbbmu;
4709 struct CommandControlBlock *freesrb;
4710 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4711 vm_offset_t mem_base[]={0,0};
4712 for(i=0; i < 2; i++) {
4713 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE);
4714 if(acb->sys_res_arcmsr[i] == NULL) {
4715 arcmsr_free_resource(acb);
4716 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4717 return ENOMEM;
4718 }
4719 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4720 arcmsr_free_resource(acb);
4721 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4722 return ENXIO;
4723 }
4724 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4725 if(mem_base[i] == 0) {
4726 arcmsr_free_resource(acb);
4727 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4728 return ENXIO;
4729 }
4730 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4731 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4732 }
4733 freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4734 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4735 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4736 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4737 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4738 if (vendor_dev_id == PCIDevVenIDARC1203) {
4739 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell);
4740 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask);
4741 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell);
4742 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask);
4743 } else {
4744 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell);
4745 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask);
4746 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell);
4747 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask);
4748 }
4749 acb->rid[0] = rid[0];
4750 acb->rid[1] = rid[1];
4751 }
4752 break;
4753 case ACB_ADAPTER_TYPE_C: {
4754 u_int32_t rid0 = PCIR_BAR(1);
4755 vm_offset_t mem_base0;
4756
4757 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4758 if(acb->sys_res_arcmsr[0] == NULL) {
4759 arcmsr_free_resource(acb);
4760 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4761 return ENOMEM;
4762 }
4763 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4764 arcmsr_free_resource(acb);
4765 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4766 return ENXIO;
4767 }
4768 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4769 if(mem_base0 == 0) {
4770 arcmsr_free_resource(acb);
4771 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4772 return ENXIO;
4773 }
4774 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4775 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4776 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4777 acb->rid[0] = rid0;
4778 }
4779 break;
4780 case ACB_ADAPTER_TYPE_D: {
4781 struct HBD_MessageUnit0 *phbdmu;
4782 u_int32_t rid0 = PCIR_BAR(0);
4783 vm_offset_t mem_base0;
4784
4785 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4786 if(acb->sys_res_arcmsr[0] == NULL) {
4787 arcmsr_free_resource(acb);
4788 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4789 return ENOMEM;
4790 }
4791 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4792 arcmsr_free_resource(acb);
4793 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4794 return ENXIO;
4795 }
4796 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4797 if(mem_base0 == 0) {
4798 arcmsr_free_resource(acb);
4799 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4800 return ENXIO;
4801 }
4802 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4803 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4804 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4805 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4806 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4807 acb->rid[0] = rid0;
4808 }
4809 break;
4810 case ACB_ADAPTER_TYPE_E: {
4811 u_int32_t rid0 = PCIR_BAR(1);
4812 vm_offset_t mem_base0;
4813
4814 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4815 if(acb->sys_res_arcmsr[0] == NULL) {
4816 arcmsr_free_resource(acb);
4817 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4818 return ENOMEM;
4819 }
4820 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4821 arcmsr_free_resource(acb);
4822 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4823 return ENXIO;
4824 }
4825 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4826 if(mem_base0 == 0) {
4827 arcmsr_free_resource(acb);
4828 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4829 return ENXIO;
4830 }
4831 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4832 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4833 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4834 acb->doneq_index = 0;
4835 acb->in_doorbell = 0;
4836 acb->out_doorbell = 0;
4837 acb->rid[0] = rid0;
4838 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4839 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4840 }
4841 break;
4842 case ACB_ADAPTER_TYPE_F: {
4843 u_int32_t rid0 = PCIR_BAR(0);
4844 vm_offset_t mem_base0;
4845 unsigned long host_buffer_dma;
4846
4847 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4848 if(acb->sys_res_arcmsr[0] == NULL) {
4849 arcmsr_free_resource(acb);
4850 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4851 return ENOMEM;
4852 }
4853 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4854 arcmsr_free_resource(acb);
4855 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4856 return ENXIO;
4857 }
4858 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4859 if(mem_base0 == 0) {
4860 arcmsr_free_resource(acb);
4861 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4862 return ENXIO;
4863 }
4864 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4865 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4866 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4867 acb->doneq_index = 0;
4868 acb->in_doorbell = 0;
4869 acb->out_doorbell = 0;
4870 acb->rid[0] = rid0;
4871 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4872 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4873 arcmsr_wait_firmware_ready(acb);
4874 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE;
4875 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */
4876 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */
4877 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */
4878 }
4879 break;
4880 }
4881 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4882 arcmsr_free_resource(acb);
4883 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4884 return ENXIO;
4885 }
4886 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4887 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4888 /*
4889 ********************************************************************
4890 ** init raid volume state
4891 ********************************************************************
4892 */
4893 for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4894 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4895 acb->devstate[i][j] = ARECA_RAID_GONE;
4896 }
4897 }
4898 arcmsr_iop_init(acb);
4899 return(0);
4900 }
4901
arcmsr_setup_msix(struct AdapterControlBlock * acb)4902 static int arcmsr_setup_msix(struct AdapterControlBlock *acb)
4903 {
4904 int i;
4905
4906 for (i = 0; i < acb->msix_vectors; i++) {
4907 acb->irq_id[i] = 1 + i;
4908 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev,
4909 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE);
4910 if (acb->irqres[i] == NULL) {
4911 printf("arcmsr: Can't allocate MSI-X resource\n");
4912 goto irq_alloc_failed;
4913 }
4914 if (bus_setup_intr(acb->pci_dev, acb->irqres[i],
4915 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler,
4916 acb, &acb->ih[i])) {
4917 printf("arcmsr: Cannot set up MSI-X interrupt handler\n");
4918 goto irq_alloc_failed;
4919 }
4920 }
4921 printf("arcmsr: MSI-X INT enabled\n");
4922 acb->acb_flags |= ACB_F_MSIX_ENABLED;
4923 return TRUE;
4924
4925 irq_alloc_failed:
4926 arcmsr_teardown_intr(acb->pci_dev, acb);
4927 return FALSE;
4928 }
4929
4930 /*
4931 ************************************************************************
4932 ************************************************************************
4933 */
arcmsr_attach(device_t dev)4934 static int arcmsr_attach(device_t dev)
4935 {
4936 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4937 u_int32_t unit=device_get_unit(dev);
4938 struct ccb_setasync csa;
4939 struct cam_devq *devq; /* Device Queue to use for this SIM */
4940 struct resource *irqres;
4941
4942 if(acb == NULL) {
4943 printf("arcmsr%d: cannot allocate softc\n", unit);
4944 return (ENOMEM);
4945 }
4946 arcmsr_mutex_init(acb);
4947 acb->pci_dev = dev;
4948 acb->pci_unit = unit;
4949 if(arcmsr_initialize(dev)) {
4950 printf("arcmsr%d: initialize failure!\n", unit);
4951 goto initialize_failed;
4952 }
4953 /* After setting up the adapter, map our interrupt */
4954 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS;
4955 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) {
4956 if (arcmsr_setup_msix(acb) == TRUE)
4957 goto irqx;
4958 }
4959 acb->irq_id[0] = 0;
4960 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE);
4961 if(irqres == NULL ||
4962 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) {
4963 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4964 goto setup_intr_failed;
4965 }
4966 acb->irqres[0] = irqres;
4967 irqx:
4968 /*
4969 * Now let the CAM generic SCSI layer find the SCSI devices on
4970 * the bus * start queue to reset to the idle loop. *
4971 * Create device queue of SIM(s) * (MAX_START_JOB - 1) :
4972 * max_sim_transactions
4973 */
4974 devq = cam_simq_alloc(acb->maxOutstanding);
4975 if(devq == NULL) {
4976 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4977 goto simq_alloc_failed;
4978 }
4979 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4980 if(acb->psim == NULL) {
4981 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4982 goto sim_alloc_failed;
4983 }
4984 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4985 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4986 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4987 goto xpt_bus_failed;
4988 }
4989 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4990 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4991 goto xpt_path_failed;
4992 }
4993 /*
4994 ****************************************************
4995 */
4996 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4997 csa.ccb_h.func_code = XPT_SASYNC_CB;
4998 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4999 csa.callback = arcmsr_async;
5000 csa.callback_arg = acb->psim;
5001 xpt_action((union ccb *)&csa);
5002 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5003 /* Create the control device. */
5004 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
5005
5006 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
5007 arcmsr_callout_init(&acb->devmap_callout);
5008 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
5009 return (0);
5010 xpt_path_failed:
5011 xpt_bus_deregister(cam_sim_path(acb->psim));
5012 xpt_bus_failed:
5013 cam_sim_free(acb->psim, /* free_simq */ TRUE);
5014 sim_alloc_failed:
5015 cam_simq_free(devq);
5016 simq_alloc_failed:
5017 arcmsr_teardown_intr(dev, acb);
5018 setup_intr_failed:
5019 arcmsr_free_resource(acb);
5020 initialize_failed:
5021 arcmsr_mutex_destroy(acb);
5022 return ENXIO;
5023 }
5024
5025 /*
5026 ************************************************************************
5027 ************************************************************************
5028 */
arcmsr_probe(device_t dev)5029 static int arcmsr_probe(device_t dev)
5030 {
5031 u_int32_t id;
5032 u_int16_t sub_device_id;
5033 static char buf[256];
5034 char x_type[]={"unknown"};
5035 char *type;
5036 int raid6 = 1;
5037
5038 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
5039 return (ENXIO);
5040 }
5041 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
5042 switch(id = pci_get_devid(dev)) {
5043 case PCIDevVenIDARC1110:
5044 case PCIDevVenIDARC1200:
5045 case PCIDevVenIDARC1201:
5046 case PCIDevVenIDARC1210:
5047 raid6 = 0;
5048 /*FALLTHRU*/
5049 case PCIDevVenIDARC1120:
5050 case PCIDevVenIDARC1130:
5051 case PCIDevVenIDARC1160:
5052 case PCIDevVenIDARC1170:
5053 case PCIDevVenIDARC1220:
5054 case PCIDevVenIDARC1230:
5055 case PCIDevVenIDARC1231:
5056 case PCIDevVenIDARC1260:
5057 case PCIDevVenIDARC1261:
5058 case PCIDevVenIDARC1270:
5059 case PCIDevVenIDARC1280:
5060 type = "SATA 3G";
5061 break;
5062 case PCIDevVenIDARC1212:
5063 case PCIDevVenIDARC1222:
5064 case PCIDevVenIDARC1380:
5065 case PCIDevVenIDARC1381:
5066 case PCIDevVenIDARC1680:
5067 case PCIDevVenIDARC1681:
5068 type = "SAS 3G";
5069 break;
5070 case PCIDevVenIDARC1880:
5071 case PCIDevVenIDARC1882:
5072 case PCIDevVenIDARC1213:
5073 case PCIDevVenIDARC1223:
5074 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) ||
5075 (sub_device_id == ARECA_SUB_DEV_ID_1216) ||
5076 (sub_device_id == ARECA_SUB_DEV_ID_1226))
5077 type = "SAS 12G";
5078 else
5079 type = "SAS 6G";
5080 break;
5081 case PCIDevVenIDARC1884:
5082 type = "SAS 12G";
5083 break;
5084 case PCIDevVenIDARC1886_:
5085 case PCIDevVenIDARC1886:
5086 type = "NVME,SAS-12G,SATA-6G";
5087 break;
5088 case PCIDevVenIDARC1214:
5089 case PCIDevVenIDARC1203:
5090 type = "SATA 6G";
5091 break;
5092 default:
5093 type = x_type;
5094 raid6 = 0;
5095 break;
5096 }
5097 if(type == x_type)
5098 return(ENXIO);
5099 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
5100 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
5101 device_set_desc_copy(dev, buf);
5102 return (BUS_PROBE_DEFAULT);
5103 }
5104 /*
5105 ************************************************************************
5106 ************************************************************************
5107 */
arcmsr_shutdown(device_t dev)5108 static int arcmsr_shutdown(device_t dev)
5109 {
5110 u_int32_t i;
5111 u_int32_t intmask_org;
5112 struct CommandControlBlock *srb;
5113 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
5114
5115 /* stop adapter background rebuild */
5116 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
5117 /* disable all outbound interrupt */
5118 intmask_org = arcmsr_disable_allintr(acb);
5119 arcmsr_stop_adapter_bgrb(acb);
5120 arcmsr_flush_adapter_cache(acb);
5121 /* abort all outstanding command */
5122 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
5123 acb->acb_flags &= ~ACB_F_IOP_INITED;
5124 if(acb->srboutstandingcount != 0) {
5125 /*clear and abort all outbound posted Q*/
5126 arcmsr_done4abort_postqueue(acb);
5127 /* talk to iop 331 outstanding command aborted*/
5128 arcmsr_abort_allcmd(acb);
5129 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
5130 srb = acb->psrb_pool[i];
5131 if(srb->srb_state == ARCMSR_SRB_START) {
5132 srb->srb_state = ARCMSR_SRB_ABORTED;
5133 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
5134 arcmsr_srb_complete(srb, 1);
5135 }
5136 }
5137 }
5138 acb->srboutstandingcount = 0;
5139 acb->workingsrb_doneindex = 0;
5140 acb->workingsrb_startindex = 0;
5141 acb->pktRequestCount = 0;
5142 acb->pktReturnCount = 0;
5143 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5144 return (0);
5145 }
5146 /*
5147 ************************************************************************
5148 ************************************************************************
5149 */
arcmsr_teardown_intr(device_t dev,struct AdapterControlBlock * acb)5150 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb)
5151 {
5152 int i;
5153
5154 if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
5155 for (i = 0; i < acb->msix_vectors; i++) {
5156 if (acb->ih[i])
5157 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]);
5158 if (acb->irqres[i] != NULL)
5159 bus_release_resource(dev, SYS_RES_IRQ,
5160 acb->irq_id[i], acb->irqres[i]);
5161
5162 acb->ih[i] = NULL;
5163 }
5164 pci_release_msi(dev);
5165 } else {
5166 if (acb->ih[0])
5167 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]);
5168 if (acb->irqres[0] != NULL)
5169 bus_release_resource(dev, SYS_RES_IRQ,
5170 acb->irq_id[0], acb->irqres[0]);
5171 acb->ih[0] = NULL;
5172 }
5173
5174 }
5175 /*
5176 ************************************************************************
5177 ************************************************************************
5178 */
arcmsr_detach(device_t dev)5179 static int arcmsr_detach(device_t dev)
5180 {
5181 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
5182 int i;
5183
5184 callout_stop(&acb->devmap_callout);
5185 arcmsr_teardown_intr(dev, acb);
5186 arcmsr_shutdown(dev);
5187 arcmsr_free_resource(acb);
5188 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
5189 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]);
5190 }
5191 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
5192 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
5193 xpt_free_path(acb->ppath);
5194 xpt_bus_deregister(cam_sim_path(acb->psim));
5195 cam_sim_free(acb->psim, TRUE);
5196 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5197 arcmsr_mutex_destroy(acb);
5198 return (0);
5199 }
5200
5201 #ifdef ARCMSR_DEBUG1
arcmsr_dump_data(struct AdapterControlBlock * acb)5202 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
5203 {
5204 if((acb->pktRequestCount - acb->pktReturnCount) == 0)
5205 return;
5206 printf("Command Request Count =0x%x\n",acb->pktRequestCount);
5207 printf("Command Return Count =0x%x\n",acb->pktReturnCount);
5208 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
5209 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount);
5210 }
5211 #endif
5212