1 /*-
2 * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: stable/12/sys/arm/ti/usb/omap_host.c 332310 2018-04-08 22:59:34Z gonzo $");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/rman.h>
36 #include <sys/module.h>
37
38 #include <dev/fdt/simplebus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
40
41 #include <machine/bus.h>
42
43 #include <arm/ti/ti_prcm.h>
44 #include <arm/ti/usb/omap_usb.h>
45
46 /*
47 * USB Host Module
48 */
49
50 /* UHH */
51 #define OMAP_USBHOST_UHH_REVISION 0x0000
52 #define OMAP_USBHOST_UHH_SYSCONFIG 0x0010
53 #define OMAP_USBHOST_UHH_SYSSTATUS 0x0014
54 #define OMAP_USBHOST_UHH_HOSTCONFIG 0x0040
55 #define OMAP_USBHOST_UHH_DEBUG_CSR 0x0044
56
57 /* UHH Register Set */
58 #define UHH_SYSCONFIG_MIDLEMODE_MASK (3UL << 12)
59 #define UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY (2UL << 12)
60 #define UHH_SYSCONFIG_MIDLEMODE_NOSTANDBY (1UL << 12)
61 #define UHH_SYSCONFIG_MIDLEMODE_FORCESTANDBY (0UL << 12)
62 #define UHH_SYSCONFIG_CLOCKACTIVITY (1UL << 8)
63 #define UHH_SYSCONFIG_SIDLEMODE_MASK (3UL << 3)
64 #define UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE (2UL << 3)
65 #define UHH_SYSCONFIG_SIDLEMODE_NOIDLE (1UL << 3)
66 #define UHH_SYSCONFIG_SIDLEMODE_FORCEIDLE (0UL << 3)
67 #define UHH_SYSCONFIG_ENAWAKEUP (1UL << 2)
68 #define UHH_SYSCONFIG_SOFTRESET (1UL << 1)
69 #define UHH_SYSCONFIG_AUTOIDLE (1UL << 0)
70
71 #define UHH_HOSTCONFIG_APP_START_CLK (1UL << 31)
72 #define UHH_HOSTCONFIG_P3_CONNECT_STATUS (1UL << 10)
73 #define UHH_HOSTCONFIG_P2_CONNECT_STATUS (1UL << 9)
74 #define UHH_HOSTCONFIG_P1_CONNECT_STATUS (1UL << 8)
75 #define UHH_HOSTCONFIG_ENA_INCR_ALIGN (1UL << 5)
76 #define UHH_HOSTCONFIG_ENA_INCR16 (1UL << 4)
77 #define UHH_HOSTCONFIG_ENA_INCR8 (1UL << 3)
78 #define UHH_HOSTCONFIG_ENA_INCR4 (1UL << 2)
79 #define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN (1UL << 1)
80 #define UHH_HOSTCONFIG_P1_ULPI_BYPASS (1UL << 0)
81
82 /* The following are on rev2 (OMAP44xx) of the EHCI only */
83 #define UHH_SYSCONFIG_IDLEMODE_MASK (3UL << 2)
84 #define UHH_SYSCONFIG_IDLEMODE_NOIDLE (1UL << 2)
85 #define UHH_SYSCONFIG_STANDBYMODE_MASK (3UL << 4)
86 #define UHH_SYSCONFIG_STANDBYMODE_NOSTDBY (1UL << 4)
87
88 #define UHH_HOSTCONFIG_P1_MODE_MASK (3UL << 16)
89 #define UHH_HOSTCONFIG_P1_MODE_ULPI_PHY (0UL << 16)
90 #define UHH_HOSTCONFIG_P1_MODE_UTMI_PHY (1UL << 16)
91 #define UHH_HOSTCONFIG_P1_MODE_HSIC (3UL << 16)
92 #define UHH_HOSTCONFIG_P2_MODE_MASK (3UL << 18)
93 #define UHH_HOSTCONFIG_P2_MODE_ULPI_PHY (0UL << 18)
94 #define UHH_HOSTCONFIG_P2_MODE_UTMI_PHY (1UL << 18)
95 #define UHH_HOSTCONFIG_P2_MODE_HSIC (3UL << 18)
96
97 /*
98 * Values of UHH_REVISION - Note: these are not given in the TRM but taken
99 * from the linux OMAP EHCI driver (thanks guys). It has been verified on
100 * a Panda and Beagle board.
101 */
102 #define OMAP_UHH_REV1 0x00000010 /* OMAP3 */
103 #define OMAP_UHH_REV2 0x50700100 /* OMAP4 */
104
105 struct omap_uhh_softc {
106 struct simplebus_softc simplebus_sc;
107 device_t sc_dev;
108
109 /* UHH register set */
110 struct resource* uhh_mem_res;
111
112 /* The revision of the HS USB HOST read from UHH_REVISION */
113 uint32_t uhh_rev;
114
115 /* The following details are provided by conf hints */
116 int port_mode[3];
117 };
118
119 static device_attach_t omap_uhh_attach;
120 static device_detach_t omap_uhh_detach;
121
122 static inline uint32_t
omap_uhh_read_4(struct omap_uhh_softc * sc,bus_size_t off)123 omap_uhh_read_4(struct omap_uhh_softc *sc, bus_size_t off)
124 {
125 return bus_read_4(sc->uhh_mem_res, off);
126 }
127
128 static inline void
omap_uhh_write_4(struct omap_uhh_softc * sc,bus_size_t off,uint32_t val)129 omap_uhh_write_4(struct omap_uhh_softc *sc, bus_size_t off, uint32_t val)
130 {
131 bus_write_4(sc->uhh_mem_res, off, val);
132 }
133
134 static int
omap_uhh_init(struct omap_uhh_softc * isc)135 omap_uhh_init(struct omap_uhh_softc *isc)
136 {
137 uint8_t tll_ch_mask;
138 uint32_t reg;
139 int i;
140
141 /* Enable Clocks for high speed USBHOST */
142 ti_prcm_clk_enable(USBHSHOST_CLK);
143
144 /* Read the UHH revision */
145 isc->uhh_rev = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_REVISION);
146 device_printf(isc->sc_dev, "UHH revision 0x%08x\n", isc->uhh_rev);
147
148 if (isc->uhh_rev == OMAP_UHH_REV2) {
149 /* For OMAP44xx devices you have to enable the per-port clocks:
150 * PHY_MODE - External ULPI clock
151 * TTL_MODE - Internal UTMI clock
152 * HSIC_MODE - Internal 480Mhz and 60Mhz clocks
153 */
154 switch(isc->port_mode[0]) {
155 case EHCI_HCD_OMAP_MODE_UNKNOWN:
156 break;
157 case EHCI_HCD_OMAP_MODE_PHY:
158 if (ti_prcm_clk_set_source(USBP1_PHY_CLK, EXT_CLK))
159 device_printf(isc->sc_dev,
160 "failed to set clock source for port 0\n");
161 if (ti_prcm_clk_enable(USBP1_PHY_CLK))
162 device_printf(isc->sc_dev,
163 "failed to set clock USBP1_PHY_CLK source for port 0\n");
164 break;
165 case EHCI_HCD_OMAP_MODE_TLL:
166 if (ti_prcm_clk_enable(USBP1_UTMI_CLK))
167 device_printf(isc->sc_dev,
168 "failed to set clock USBP1_PHY_CLK source for port 0\n");
169 break;
170 case EHCI_HCD_OMAP_MODE_HSIC:
171 if (ti_prcm_clk_enable(USBP1_HSIC_CLK))
172 device_printf(isc->sc_dev,
173 "failed to set clock USBP1_PHY_CLK source for port 0\n");
174 break;
175 default:
176 device_printf(isc->sc_dev, "unknown port mode %d for port 0\n", isc->port_mode[0]);
177 }
178 switch(isc->port_mode[1]) {
179 case EHCI_HCD_OMAP_MODE_UNKNOWN:
180 break;
181 case EHCI_HCD_OMAP_MODE_PHY:
182 if (ti_prcm_clk_set_source(USBP2_PHY_CLK, EXT_CLK))
183 device_printf(isc->sc_dev,
184 "failed to set clock source for port 0\n");
185 if (ti_prcm_clk_enable(USBP2_PHY_CLK))
186 device_printf(isc->sc_dev,
187 "failed to set clock USBP2_PHY_CLK source for port 1\n");
188 break;
189 case EHCI_HCD_OMAP_MODE_TLL:
190 if (ti_prcm_clk_enable(USBP2_UTMI_CLK))
191 device_printf(isc->sc_dev,
192 "failed to set clock USBP2_UTMI_CLK source for port 1\n");
193 break;
194 case EHCI_HCD_OMAP_MODE_HSIC:
195 if (ti_prcm_clk_enable(USBP2_HSIC_CLK))
196 device_printf(isc->sc_dev,
197 "failed to set clock USBP2_HSIC_CLK source for port 1\n");
198 break;
199 default:
200 device_printf(isc->sc_dev, "unknown port mode %d for port 1\n", isc->port_mode[1]);
201 }
202 }
203
204 /* Put UHH in SmartIdle/SmartStandby mode */
205 reg = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_SYSCONFIG);
206 if (isc->uhh_rev == OMAP_UHH_REV1) {
207 reg &= ~(UHH_SYSCONFIG_SIDLEMODE_MASK |
208 UHH_SYSCONFIG_MIDLEMODE_MASK);
209 reg |= (UHH_SYSCONFIG_ENAWAKEUP |
210 UHH_SYSCONFIG_AUTOIDLE |
211 UHH_SYSCONFIG_CLOCKACTIVITY |
212 UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE |
213 UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY);
214 } else if (isc->uhh_rev == OMAP_UHH_REV2) {
215 reg &= ~UHH_SYSCONFIG_IDLEMODE_MASK;
216 reg |= UHH_SYSCONFIG_IDLEMODE_NOIDLE;
217 reg &= ~UHH_SYSCONFIG_STANDBYMODE_MASK;
218 reg |= UHH_SYSCONFIG_STANDBYMODE_NOSTDBY;
219 }
220 omap_uhh_write_4(isc, OMAP_USBHOST_UHH_SYSCONFIG, reg);
221 device_printf(isc->sc_dev, "OMAP_UHH_SYSCONFIG: 0x%08x\n", reg);
222
223 reg = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_HOSTCONFIG);
224
225 /* Setup ULPI bypass and burst configurations */
226 reg |= (UHH_HOSTCONFIG_ENA_INCR4 |
227 UHH_HOSTCONFIG_ENA_INCR8 |
228 UHH_HOSTCONFIG_ENA_INCR16);
229 reg &= ~UHH_HOSTCONFIG_ENA_INCR_ALIGN;
230
231 if (isc->uhh_rev == OMAP_UHH_REV1) {
232 if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
233 reg &= ~UHH_HOSTCONFIG_P1_CONNECT_STATUS;
234 if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
235 reg &= ~UHH_HOSTCONFIG_P2_CONNECT_STATUS;
236 if (isc->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
237 reg &= ~UHH_HOSTCONFIG_P3_CONNECT_STATUS;
238
239 /* Bypass the TLL module for PHY mode operation */
240 if ((isc->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
241 (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
242 (isc->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
243 reg &= ~UHH_HOSTCONFIG_P1_ULPI_BYPASS;
244 else
245 reg |= UHH_HOSTCONFIG_P1_ULPI_BYPASS;
246
247 } else if (isc->uhh_rev == OMAP_UHH_REV2) {
248 reg |= UHH_HOSTCONFIG_APP_START_CLK;
249
250 /* Clear port mode fields for PHY mode*/
251 reg &= ~UHH_HOSTCONFIG_P1_MODE_MASK;
252 reg &= ~UHH_HOSTCONFIG_P2_MODE_MASK;
253
254 if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
255 reg |= UHH_HOSTCONFIG_P1_MODE_UTMI_PHY;
256 else if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_HSIC)
257 reg |= UHH_HOSTCONFIG_P1_MODE_HSIC;
258
259 if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
260 reg |= UHH_HOSTCONFIG_P2_MODE_UTMI_PHY;
261 else if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_HSIC)
262 reg |= UHH_HOSTCONFIG_P2_MODE_HSIC;
263 }
264
265 omap_uhh_write_4(isc, OMAP_USBHOST_UHH_HOSTCONFIG, reg);
266 device_printf(isc->sc_dev, "UHH setup done, uhh_hostconfig=0x%08x\n", reg);
267
268
269 /* I found the code and comments in the Linux EHCI driver - thanks guys :)
270 *
271 * "An undocumented "feature" in the OMAP3 EHCI controller, causes suspended
272 * ports to be taken out of suspend when the USBCMD.Run/Stop bit is cleared
273 * (for example when we do omap_uhh_bus_suspend). This breaks suspend-resume if
274 * the root-hub is allowed to suspend. Writing 1 to this undocumented
275 * register bit disables this feature and restores normal behavior."
276 */
277 #if 0
278 omap_uhh_write_4(isc, OMAP_USBHOST_INSNREG04,
279 OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND);
280 #endif
281 tll_ch_mask = 0;
282 for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
283 if (isc->port_mode[i] == EHCI_HCD_OMAP_MODE_TLL)
284 tll_ch_mask |= (1 << i);
285 }
286 if (tll_ch_mask)
287 omap_tll_utmi_enable(tll_ch_mask);
288
289 return(0);
290 }
291
292 /**
293 * omap_uhh_fini - shutdown the EHCI controller
294 * @isc: omap ehci device context
295 *
296 *
297 *
298 * LOCKING:
299 * none
300 *
301 * RETURNS:
302 * 0 on success, a negative error code on failure.
303 */
304 static void
omap_uhh_fini(struct omap_uhh_softc * isc)305 omap_uhh_fini(struct omap_uhh_softc *isc)
306 {
307 unsigned long timeout;
308
309 device_printf(isc->sc_dev, "Stopping TI EHCI USB Controller\n");
310
311 /* Set the timeout */
312 if (hz < 10)
313 timeout = 1;
314 else
315 timeout = (100 * hz) / 1000;
316
317 /* Reset the UHH, OHCI and EHCI modules */
318 omap_uhh_write_4(isc, OMAP_USBHOST_UHH_SYSCONFIG, 0x0002);
319 while ((omap_uhh_read_4(isc, OMAP_USBHOST_UHH_SYSSTATUS) & 0x07) == 0x00) {
320 /* Sleep for a tick */
321 pause("USBRESET", 1);
322
323 if (timeout-- == 0) {
324 device_printf(isc->sc_dev, "operation timed out\n");
325 break;
326 }
327 }
328
329 /* Disable functional and interface clocks for the TLL and HOST modules */
330 ti_prcm_clk_disable(USBHSHOST_CLK);
331
332 device_printf(isc->sc_dev, "Clock to USB host has been disabled\n");
333 }
334
335 int
omap_usb_port_mode(device_t dev,int port)336 omap_usb_port_mode(device_t dev, int port)
337 {
338 struct omap_uhh_softc *isc;
339
340 isc = device_get_softc(dev);
341 if ((port < 0) || (port >= OMAP_HS_USB_PORTS))
342 return (-1);
343
344 return isc->port_mode[port];
345 }
346
347 static int
omap_uhh_probe(device_t dev)348 omap_uhh_probe(device_t dev)
349 {
350
351 if (!ofw_bus_status_okay(dev))
352 return (ENXIO);
353
354 if (!ofw_bus_is_compatible(dev, "ti,usbhs-host"))
355 return (ENXIO);
356
357 device_set_desc(dev, "TI OMAP USB 2.0 Host module");
358
359 return (BUS_PROBE_DEFAULT);
360 }
361
362 static int
omap_uhh_attach(device_t dev)363 omap_uhh_attach(device_t dev)
364 {
365 struct omap_uhh_softc *isc = device_get_softc(dev);
366 int err;
367 int rid;
368 int i;
369 phandle_t node;
370 char propname[16];
371 char *mode;
372
373 /* save the device */
374 isc->sc_dev = dev;
375
376 /* Allocate resource for the UHH register set */
377 rid = 0;
378 isc->uhh_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
379 if (!isc->uhh_mem_res) {
380 device_printf(dev, "Error: Could not map UHH memory\n");
381 goto error;
382 }
383
384 node = ofw_bus_get_node(dev);
385
386 if (node == -1)
387 goto error;
388
389 /* Get port modes from FDT */
390 for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
391 isc->port_mode[i] = EHCI_HCD_OMAP_MODE_UNKNOWN;
392 snprintf(propname, sizeof(propname),
393 "port%d-mode", i+1);
394
395 if (OF_getprop_alloc(node, propname, (void**)&mode) <= 0)
396 continue;
397 if (strcmp(mode, "ehci-phy") == 0)
398 isc->port_mode[i] = EHCI_HCD_OMAP_MODE_PHY;
399 else if (strcmp(mode, "ehci-tll") == 0)
400 isc->port_mode[i] = EHCI_HCD_OMAP_MODE_TLL;
401 else if (strcmp(mode, "ehci-hsic") == 0)
402 isc->port_mode[i] = EHCI_HCD_OMAP_MODE_HSIC;
403 }
404
405 /* Initialise the ECHI registers */
406 err = omap_uhh_init(isc);
407 if (err) {
408 device_printf(dev, "Error: could not setup OMAP EHCI, %d\n", err);
409 goto error;
410 }
411
412 simplebus_init(dev, node);
413
414 /*
415 * Allow devices to identify.
416 */
417 bus_generic_probe(dev);
418
419 /*
420 * Now walk the OFW tree and attach top-level devices.
421 */
422 for (node = OF_child(node); node > 0; node = OF_peer(node))
423 simplebus_add_device(dev, node, 0, NULL, -1, NULL);
424 return (bus_generic_attach(dev));
425
426 error:
427 omap_uhh_detach(dev);
428 return (ENXIO);
429 }
430
431 static int
omap_uhh_detach(device_t dev)432 omap_uhh_detach(device_t dev)
433 {
434 struct omap_uhh_softc *isc = device_get_softc(dev);
435
436 /* during module unload there are lots of children leftover */
437 device_delete_children(dev);
438
439 if (isc->uhh_mem_res) {
440 bus_release_resource(dev, SYS_RES_MEMORY, 0, isc->uhh_mem_res);
441 isc->uhh_mem_res = NULL;
442 }
443
444 omap_uhh_fini(isc);
445
446 return (0);
447 }
448
449 static device_method_t omap_uhh_methods[] = {
450 /* Device interface */
451 DEVMETHOD(device_probe, omap_uhh_probe),
452 DEVMETHOD(device_attach, omap_uhh_attach),
453 DEVMETHOD(device_detach, omap_uhh_detach),
454
455 DEVMETHOD(device_suspend, bus_generic_suspend),
456 DEVMETHOD(device_resume, bus_generic_resume),
457 DEVMETHOD(device_shutdown, bus_generic_shutdown),
458
459 DEVMETHOD_END
460 };
461
462 DEFINE_CLASS_1(omap_uhh, omap_uhh_driver, omap_uhh_methods,
463 sizeof(struct omap_uhh_softc), simplebus_driver);
464 static devclass_t omap_uhh_devclass;
465 DRIVER_MODULE(omap_uhh, simplebus, omap_uhh_driver, omap_uhh_devclass, 0, 0);
466