1 /*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2009, Luiz Otavio O Souza.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * GPIO driver for AR71xx
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/rman.h>
43 #include <sys/lock.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
46 #include <sys/gpio.h>
47
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <mips/atheros/ar71xxreg.h>
51 #include <mips/atheros/ar71xx_setup.h>
52 #include <mips/atheros/ar71xx_cpudef.h>
53 #include <mips/atheros/ar71xx_gpiovar.h>
54 #include <dev/gpio/gpiobusvar.h>
55 #include <mips/atheros/ar933xreg.h>
56 #include <mips/atheros/ar934xreg.h>
57 #include <mips/atheros/qca953xreg.h>
58 #include <mips/atheros/qca955xreg.h>
59
60 #include "gpio_if.h"
61
62 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
63
64 /*
65 * Helpers
66 */
67 static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc,
68 uint32_t mask);
69 static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc,
70 uint32_t mask);
71 static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc,
72 struct gpio_pin *pin, uint32_t flags);
73
74 /*
75 * Driver stuff
76 */
77 static int ar71xx_gpio_probe(device_t dev);
78 static int ar71xx_gpio_attach(device_t dev);
79 static int ar71xx_gpio_detach(device_t dev);
80 static int ar71xx_gpio_filter(void *arg);
81 static void ar71xx_gpio_intr(void *arg);
82
83 /*
84 * GPIO interface
85 */
86 static device_t ar71xx_gpio_get_bus(device_t);
87 static int ar71xx_gpio_pin_max(device_t dev, int *maxpin);
88 static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
89 static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
90 *flags);
91 static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
92 static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
93 static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
94 static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
95 static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin);
96
97 /*
98 * Enable/disable the GPIO function control space.
99 *
100 * This is primarily for the AR71xx, which has SPI CS1/CS2, UART, SLIC, I2S
101 * as GPIO pin options.
102 */
103 static void
ar71xx_gpio_function_enable(struct ar71xx_gpio_softc * sc,uint32_t mask)104 ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
105 {
106
107 /*
108 * XXX TODO: refactor this out into a per-chipset method.
109 */
110 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
111 ar71xx_soc == AR71XX_SOC_AR9342 ||
112 ar71xx_soc == AR71XX_SOC_AR9344 ||
113 ar71xx_soc == AR71XX_SOC_QCA9533 ||
114 ar71xx_soc == AR71XX_SOC_QCA9533_V2 ||
115 ar71xx_soc == AR71XX_SOC_QCA9556 ||
116 ar71xx_soc == AR71XX_SOC_QCA9558)
117 GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
118 else
119 GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
120 }
121
122 static void
ar71xx_gpio_function_disable(struct ar71xx_gpio_softc * sc,uint32_t mask)123 ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask)
124 {
125
126 /*
127 * XXX TODO: refactor this out into a per-chipset method.
128 */
129 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
130 ar71xx_soc == AR71XX_SOC_AR9342 ||
131 ar71xx_soc == AR71XX_SOC_AR9344 ||
132 ar71xx_soc == AR71XX_SOC_QCA9533 ||
133 ar71xx_soc == AR71XX_SOC_QCA9533_V2 ||
134 ar71xx_soc == AR71XX_SOC_QCA9556 ||
135 ar71xx_soc == AR71XX_SOC_QCA9558)
136 GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
137 else
138 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
139 }
140
141 static void
ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc * sc,struct gpio_pin * pin,unsigned int flags)142 ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
143 unsigned int flags)
144 {
145 uint32_t mask;
146
147 mask = 1 << pin->gp_pin;
148
149 /*
150 * Manage input/output
151 */
152 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
153 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
154 if (flags & GPIO_PIN_OUTPUT) {
155 pin->gp_flags |= GPIO_PIN_OUTPUT;
156 GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
157 }
158 else {
159 pin->gp_flags |= GPIO_PIN_INPUT;
160 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
161 }
162 }
163 }
164
165 static device_t
ar71xx_gpio_get_bus(device_t dev)166 ar71xx_gpio_get_bus(device_t dev)
167 {
168 struct ar71xx_gpio_softc *sc;
169
170 sc = device_get_softc(dev);
171
172 return (sc->busdev);
173 }
174
175 static int
ar71xx_gpio_pin_max(device_t dev,int * maxpin)176 ar71xx_gpio_pin_max(device_t dev, int *maxpin)
177 {
178
179 switch (ar71xx_soc) {
180 case AR71XX_SOC_AR9130:
181 case AR71XX_SOC_AR9132:
182 *maxpin = AR91XX_GPIO_PINS - 1;
183 break;
184 case AR71XX_SOC_AR7240:
185 case AR71XX_SOC_AR7241:
186 case AR71XX_SOC_AR7242:
187 *maxpin = AR724X_GPIO_PINS - 1;
188 break;
189 case AR71XX_SOC_AR9330:
190 case AR71XX_SOC_AR9331:
191 *maxpin = AR933X_GPIO_COUNT - 1;
192 break;
193 case AR71XX_SOC_AR9341:
194 case AR71XX_SOC_AR9342:
195 case AR71XX_SOC_AR9344:
196 *maxpin = AR934X_GPIO_COUNT - 1;
197 break;
198 case AR71XX_SOC_QCA9533:
199 case AR71XX_SOC_QCA9533_V2:
200 *maxpin = QCA953X_GPIO_COUNT - 1;
201 break;
202 case AR71XX_SOC_QCA9556:
203 case AR71XX_SOC_QCA9558:
204 *maxpin = QCA955X_GPIO_COUNT - 1;
205 break;
206 default:
207 *maxpin = AR71XX_GPIO_PINS - 1;
208 }
209 return (0);
210 }
211
212 static int
ar71xx_gpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)213 ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
214 {
215 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
216 int i;
217
218 for (i = 0; i < sc->gpio_npins; i++) {
219 if (sc->gpio_pins[i].gp_pin == pin)
220 break;
221 }
222
223 if (i >= sc->gpio_npins)
224 return (EINVAL);
225
226 GPIO_LOCK(sc);
227 *caps = sc->gpio_pins[i].gp_caps;
228 GPIO_UNLOCK(sc);
229
230 return (0);
231 }
232
233 static int
ar71xx_gpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)234 ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
235 {
236 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
237 int i;
238
239 for (i = 0; i < sc->gpio_npins; i++) {
240 if (sc->gpio_pins[i].gp_pin == pin)
241 break;
242 }
243
244 if (i >= sc->gpio_npins)
245 return (EINVAL);
246
247 GPIO_LOCK(sc);
248 *flags = sc->gpio_pins[i].gp_flags;
249 GPIO_UNLOCK(sc);
250
251 return (0);
252 }
253
254 static int
ar71xx_gpio_pin_getname(device_t dev,uint32_t pin,char * name)255 ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
256 {
257 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
258 int i;
259
260 for (i = 0; i < sc->gpio_npins; i++) {
261 if (sc->gpio_pins[i].gp_pin == pin)
262 break;
263 }
264
265 if (i >= sc->gpio_npins)
266 return (EINVAL);
267
268 GPIO_LOCK(sc);
269 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
270 GPIO_UNLOCK(sc);
271
272 return (0);
273 }
274
275 static int
ar71xx_gpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)276 ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
277 {
278 int i;
279 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
280
281 for (i = 0; i < sc->gpio_npins; i++) {
282 if (sc->gpio_pins[i].gp_pin == pin)
283 break;
284 }
285
286 if (i >= sc->gpio_npins)
287 return (EINVAL);
288
289 ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
290
291 return (0);
292 }
293
294 static int
ar71xx_gpio_pin_set(device_t dev,uint32_t pin,unsigned int value)295 ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
296 {
297 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
298 int i;
299
300 for (i = 0; i < sc->gpio_npins; i++) {
301 if (sc->gpio_pins[i].gp_pin == pin)
302 break;
303 }
304
305 if (i >= sc->gpio_npins)
306 return (EINVAL);
307
308 if (value)
309 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
310 else
311 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
312
313 return (0);
314 }
315
316 static int
ar71xx_gpio_pin_get(device_t dev,uint32_t pin,unsigned int * val)317 ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
318 {
319 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
320 int i;
321
322 for (i = 0; i < sc->gpio_npins; i++) {
323 if (sc->gpio_pins[i].gp_pin == pin)
324 break;
325 }
326
327 if (i >= sc->gpio_npins)
328 return (EINVAL);
329
330 *val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
331
332 return (0);
333 }
334
335 static int
ar71xx_gpio_pin_toggle(device_t dev,uint32_t pin)336 ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
337 {
338 int res, i;
339 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
340
341 for (i = 0; i < sc->gpio_npins; i++) {
342 if (sc->gpio_pins[i].gp_pin == pin)
343 break;
344 }
345
346 if (i >= sc->gpio_npins)
347 return (EINVAL);
348
349 res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
350 if (res)
351 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
352 else
353 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
354
355 return (0);
356 }
357
358 static int
ar71xx_gpio_filter(void * arg)359 ar71xx_gpio_filter(void *arg)
360 {
361
362 /* TODO: something useful */
363 return (FILTER_STRAY);
364 }
365
366
367
368 static void
ar71xx_gpio_intr(void * arg)369 ar71xx_gpio_intr(void *arg)
370 {
371 struct ar71xx_gpio_softc *sc = arg;
372 GPIO_LOCK(sc);
373 /* TODO: something useful */
374 GPIO_UNLOCK(sc);
375 }
376
377 static int
ar71xx_gpio_probe(device_t dev)378 ar71xx_gpio_probe(device_t dev)
379 {
380
381 device_set_desc(dev, "Atheros AR71XX GPIO driver");
382 return (0);
383 }
384
385 static int
ar71xx_gpio_attach(device_t dev)386 ar71xx_gpio_attach(device_t dev)
387 {
388 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
389 int i, j, maxpin;
390 int mask, pinon;
391 uint32_t oe;
392
393 KASSERT((device_get_unit(dev) == 0),
394 ("ar71xx_gpio: Only one gpio module supported"));
395
396 mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
397
398 /* Map control/status registers. */
399 sc->gpio_mem_rid = 0;
400 sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
401 &sc->gpio_mem_rid, RF_ACTIVE);
402
403 if (sc->gpio_mem_res == NULL) {
404 device_printf(dev, "couldn't map memory\n");
405 ar71xx_gpio_detach(dev);
406 return (ENXIO);
407 }
408
409 if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
410 &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
411 device_printf(dev, "unable to allocate IRQ resource\n");
412 ar71xx_gpio_detach(dev);
413 return (ENXIO);
414 }
415
416 if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
417 ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
418 device_printf(dev,
419 "WARNING: unable to register interrupt handler\n");
420 ar71xx_gpio_detach(dev);
421 return (ENXIO);
422 }
423
424 sc->dev = dev;
425
426 /* Enable function bits that are required */
427 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
428 "function_set", &mask) == 0) {
429 device_printf(dev, "function_set: 0x%x\n", mask);
430 ar71xx_gpio_function_enable(sc, mask);
431 }
432 /* Disable function bits that are required */
433 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
434 "function_clear", &mask) == 0) {
435 device_printf(dev, "function_clear: 0x%x\n", mask);
436 ar71xx_gpio_function_disable(sc, mask);
437 }
438
439 /* Disable interrupts for all pins. */
440 GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
441
442 /* Initialise all pins specified in the mask, up to the pin count */
443 (void) ar71xx_gpio_pin_max(dev, &maxpin);
444 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
445 "pinmask", &mask) != 0)
446 mask = 0;
447 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
448 "pinon", &pinon) != 0)
449 pinon = 0;
450 device_printf(dev, "gpio pinmask=0x%x\n", mask);
451 for (j = 0; j <= maxpin; j++) {
452 if ((mask & (1 << j)) == 0)
453 continue;
454 sc->gpio_npins++;
455 }
456 /* Iniatilize the GPIO pins, keep the loader settings. */
457 oe = GPIO_READ(sc, AR71XX_GPIO_OE);
458 sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins,
459 M_DEVBUF, M_WAITOK | M_ZERO);
460 for (i = 0, j = 0; j <= maxpin; j++) {
461 if ((mask & (1 << j)) == 0)
462 continue;
463 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
464 "pin %d", j);
465 sc->gpio_pins[i].gp_pin = j;
466 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
467 if (oe & (1 << j))
468 sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT;
469 else
470 sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT;
471 i++;
472 }
473
474 /* Turn on the hinted pins. */
475 for (i = 0; i < sc->gpio_npins; i++) {
476 j = sc->gpio_pins[i].gp_pin;
477 if ((pinon & (1 << j)) != 0) {
478 ar71xx_gpio_pin_setflags(dev, j, GPIO_PIN_OUTPUT);
479 ar71xx_gpio_pin_set(dev, j, 1);
480 }
481 }
482
483 /*
484 * Search through the function hints, in case there's some
485 * overrides such as LNA control.
486 *
487 * hint.gpio.X.func.<pin>.gpiofunc=<func value>
488 * hint.gpio.X.func.<pin>.gpiomode=1 (for output, default low)
489 */
490 for (i = 0; i <= maxpin; i++) {
491 char buf[32];
492 int gpiofunc, gpiomode;
493
494 snprintf(buf, 32, "func.%d.gpiofunc", i);
495 if (resource_int_value(device_get_name(dev),
496 device_get_unit(dev),
497 buf,
498 &gpiofunc) != 0)
499 continue;
500 /* Get the mode too */
501 snprintf(buf, 32, "func.%d.gpiomode", i);
502 if (resource_int_value(device_get_name(dev),
503 device_get_unit(dev),
504 buf,
505 &gpiomode) != 0)
506 continue;
507
508 /* We only handle mode=1 for now */
509 if (gpiomode != 1)
510 continue;
511
512 device_printf(dev, "%s: GPIO %d: func=%d, mode=%d\n",
513 __func__,
514 i,
515 gpiofunc,
516 gpiomode);
517
518 /* Set output (bit == 0) */
519 oe = GPIO_READ(sc, AR71XX_GPIO_OE);
520 oe &= ~ (1 << i);
521 GPIO_WRITE(sc, AR71XX_GPIO_OE, oe);
522
523 /* Set pin value = 0, so it stays low by default */
524 oe = GPIO_READ(sc, AR71XX_GPIO_OUT);
525 oe &= ~ (1 << i);
526 GPIO_WRITE(sc, AR71XX_GPIO_OUT, oe);
527
528 /* Finally: Set the output config */
529 ar71xx_gpio_ouput_configure(i, gpiofunc);
530 }
531
532 sc->busdev = gpiobus_attach_bus(dev);
533 if (sc->busdev == NULL) {
534 ar71xx_gpio_detach(dev);
535 return (ENXIO);
536 }
537
538 return (0);
539 }
540
541 static int
ar71xx_gpio_detach(device_t dev)542 ar71xx_gpio_detach(device_t dev)
543 {
544 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
545
546 KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
547
548 gpiobus_detach_bus(dev);
549 if (sc->gpio_ih)
550 bus_teardown_intr(dev, sc->gpio_irq_res, sc->gpio_ih);
551 if (sc->gpio_irq_res)
552 bus_release_resource(dev, SYS_RES_IRQ, sc->gpio_irq_rid,
553 sc->gpio_irq_res);
554 if (sc->gpio_mem_res)
555 bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
556 sc->gpio_mem_res);
557 if (sc->gpio_pins)
558 free(sc->gpio_pins, M_DEVBUF);
559 mtx_destroy(&sc->gpio_mtx);
560
561 return(0);
562 }
563
564 static device_method_t ar71xx_gpio_methods[] = {
565 DEVMETHOD(device_probe, ar71xx_gpio_probe),
566 DEVMETHOD(device_attach, ar71xx_gpio_attach),
567 DEVMETHOD(device_detach, ar71xx_gpio_detach),
568
569 /* GPIO protocol */
570 DEVMETHOD(gpio_get_bus, ar71xx_gpio_get_bus),
571 DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max),
572 DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname),
573 DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags),
574 DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps),
575 DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags),
576 DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get),
577 DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set),
578 DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle),
579 {0, 0},
580 };
581
582 static driver_t ar71xx_gpio_driver = {
583 "gpio",
584 ar71xx_gpio_methods,
585 sizeof(struct ar71xx_gpio_softc),
586 };
587 static devclass_t ar71xx_gpio_devclass;
588
589 DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0);
590