1 /*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * 3Com 3c90x Etherlink XL PCI NIC driver
38 *
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
41 * the following:
42 *
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
72 *
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
76 */
77 /*
78 * The 3c90x series chips use a bus-master DMA interface for transferring
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
86 *
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
91 *
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
99 */
100
101 #ifdef HAVE_KERNEL_OPTION_HEADERS
102 #include "opt_device_polling.h"
103 #endif
104
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/kernel.h>
110 #include <sys/malloc.h>
111 #include <sys/mbuf.h>
112 #include <sys/module.h>
113 #include <sys/socket.h>
114 #include <sys/taskqueue.h>
115
116 #include <net/if.h>
117 #include <net/if_var.h>
118 #include <net/if_arp.h>
119 #include <net/ethernet.h>
120 #include <net/if_dl.h>
121 #include <net/if_media.h>
122 #include <net/if_types.h>
123
124 #include <net/bpf.h>
125
126 #include <machine/bus.h>
127 #include <machine/resource.h>
128 #include <sys/bus.h>
129 #include <sys/rman.h>
130
131 #include <dev/mii/mii.h>
132 #include <dev/mii/mii_bitbang.h>
133 #include <dev/mii/miivar.h>
134
135 #include <dev/pci/pcireg.h>
136 #include <dev/pci/pcivar.h>
137
138 MODULE_DEPEND(xl, pci, 1, 1, 1);
139 MODULE_DEPEND(xl, ether, 1, 1, 1);
140 MODULE_DEPEND(xl, miibus, 1, 1, 1);
141
142 /* "device miibus" required. See GENERIC if you get errors here. */
143 #include "miibus_if.h"
144
145 #include <dev/xl/if_xlreg.h>
146
147 /*
148 * TX Checksumming is disabled by default for two reasons:
149 * - TX Checksumming will occasionally produce corrupt packets
150 * - TX Checksumming seems to reduce performance
151 *
152 * Only 905B/C cards were reported to have this problem, it is possible
153 * that later chips _may_ be immune.
154 */
155 #define XL905B_TXCSUM_BROKEN 1
156
157 #ifdef XL905B_TXCSUM_BROKEN
158 #define XL905B_CSUM_FEATURES 0
159 #else
160 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 #endif
162
163 /*
164 * Various supported device vendors/types and their names.
165 */
166 static const struct xl_type xl_devs[] = {
167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
168 "3Com 3c900-TPO Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
170 "3Com 3c900-COMBO Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
172 "3Com 3c905-TX Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
174 "3Com 3c905-T4 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
176 "3Com 3c900B-TPO Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
178 "3Com 3c900B-COMBO Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
180 "3Com 3c900B-TPC Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
182 "3Com 3c900B-FL Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
184 "3Com 3c905B-TX Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
186 "3Com 3c905B-T4 Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
188 "3Com 3c905B-FX/SC Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
190 "3Com 3c905B-COMBO Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
192 "3Com 3c905C-TX Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
194 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
196 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
198 "3Com 3c980 Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
200 "3Com 3c980C Fast Etherlink XL" },
201 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
202 "3Com 3cSOHO100-TX OfficeConnect" },
203 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
204 "3Com 3c450-TX HomeConnect" },
205 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
206 "3Com 3c555 Fast Etherlink XL" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
208 "3Com 3c556 Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
210 "3Com 3c556B Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
212 "3Com 3c575TX Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
214 "3Com 3c575B Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
216 "3Com 3c575C Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
218 "3Com 3c656 Fast Etherlink XL" },
219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
220 "3Com 3c656B Fast Etherlink XL" },
221 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
222 "3Com 3c656C Fast Etherlink XL" },
223 { 0, 0, NULL }
224 };
225
226 static int xl_probe(device_t);
227 static int xl_attach(device_t);
228 static int xl_detach(device_t);
229
230 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
231 static void xl_tick(void *);
232 static void xl_stats_update(struct xl_softc *);
233 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
234 static int xl_rxeof(struct xl_softc *);
235 static void xl_rxeof_task(void *, int);
236 static int xl_rx_resync(struct xl_softc *);
237 static void xl_txeof(struct xl_softc *);
238 static void xl_txeof_90xB(struct xl_softc *);
239 static void xl_txeoc(struct xl_softc *);
240 static void xl_intr(void *);
241 static void xl_start(struct ifnet *);
242 static void xl_start_locked(struct ifnet *);
243 static void xl_start_90xB_locked(struct ifnet *);
244 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
245 static void xl_init(void *);
246 static void xl_init_locked(struct xl_softc *);
247 static void xl_stop(struct xl_softc *);
248 static int xl_watchdog(struct xl_softc *);
249 static int xl_shutdown(device_t);
250 static int xl_suspend(device_t);
251 static int xl_resume(device_t);
252 static void xl_setwol(struct xl_softc *);
253
254 #ifdef DEVICE_POLLING
255 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
256 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
257 #endif
258
259 static int xl_ifmedia_upd(struct ifnet *);
260 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
261
262 static int xl_eeprom_wait(struct xl_softc *);
263 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
264
265 static void xl_rxfilter(struct xl_softc *);
266 static void xl_rxfilter_90x(struct xl_softc *);
267 static void xl_rxfilter_90xB(struct xl_softc *);
268 static void xl_setcfg(struct xl_softc *);
269 static void xl_setmode(struct xl_softc *, int);
270 static void xl_reset(struct xl_softc *);
271 static int xl_list_rx_init(struct xl_softc *);
272 static int xl_list_tx_init(struct xl_softc *);
273 static int xl_list_tx_init_90xB(struct xl_softc *);
274 static void xl_wait(struct xl_softc *);
275 static void xl_mediacheck(struct xl_softc *);
276 static void xl_choose_media(struct xl_softc *sc, int *media);
277 static void xl_choose_xcvr(struct xl_softc *, int);
278 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
279 #ifdef notdef
280 static void xl_testpacket(struct xl_softc *);
281 #endif
282
283 static int xl_miibus_readreg(device_t, int, int);
284 static int xl_miibus_writereg(device_t, int, int, int);
285 static void xl_miibus_statchg(device_t);
286 static void xl_miibus_mediainit(device_t);
287
288 /*
289 * MII bit-bang glue
290 */
291 static uint32_t xl_mii_bitbang_read(device_t);
292 static void xl_mii_bitbang_write(device_t, uint32_t);
293
294 static const struct mii_bitbang_ops xl_mii_bitbang_ops = {
295 xl_mii_bitbang_read,
296 xl_mii_bitbang_write,
297 {
298 XL_MII_DATA, /* MII_BIT_MDO */
299 XL_MII_DATA, /* MII_BIT_MDI */
300 XL_MII_CLK, /* MII_BIT_MDC */
301 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
302 0, /* MII_BIT_DIR_PHY_HOST */
303 }
304 };
305
306 static device_method_t xl_methods[] = {
307 /* Device interface */
308 DEVMETHOD(device_probe, xl_probe),
309 DEVMETHOD(device_attach, xl_attach),
310 DEVMETHOD(device_detach, xl_detach),
311 DEVMETHOD(device_shutdown, xl_shutdown),
312 DEVMETHOD(device_suspend, xl_suspend),
313 DEVMETHOD(device_resume, xl_resume),
314
315 /* MII interface */
316 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
317 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
318 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
319 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
320
321 DEVMETHOD_END
322 };
323
324 static driver_t xl_driver = {
325 "xl",
326 xl_methods,
327 sizeof(struct xl_softc)
328 };
329
330 static devclass_t xl_devclass;
331
332 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, xl_devclass, NULL, NULL,
333 SI_ORDER_ANY);
334 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL);
335
336 static void
xl_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)337 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
338 {
339 u_int32_t *paddr;
340
341 paddr = arg;
342 *paddr = segs->ds_addr;
343 }
344
345 /*
346 * Murphy's law says that it's possible the chip can wedge and
347 * the 'command in progress' bit may never clear. Hence, we wait
348 * only a finite amount of time to avoid getting caught in an
349 * infinite loop. Normally this delay routine would be a macro,
350 * but it isn't called during normal operation so we can afford
351 * to make it a function. Suppress warning when card gone.
352 */
353 static void
xl_wait(struct xl_softc * sc)354 xl_wait(struct xl_softc *sc)
355 {
356 int i;
357
358 for (i = 0; i < XL_TIMEOUT; i++) {
359 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
360 break;
361 }
362
363 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
364 device_printf(sc->xl_dev, "command never completed!\n");
365 }
366
367 /*
368 * MII access routines are provided for adapters with external
369 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
370 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
371 * Note: if you don't perform the MDIO operations just right,
372 * it's possible to end up with code that works correctly with
373 * some chips/CPUs/processor speeds/bus speeds/etc but not
374 * with others.
375 */
376
377 /*
378 * Read the MII serial port for the MII bit-bang module.
379 */
380 static uint32_t
xl_mii_bitbang_read(device_t dev)381 xl_mii_bitbang_read(device_t dev)
382 {
383 struct xl_softc *sc;
384 uint32_t val;
385
386 sc = device_get_softc(dev);
387
388 /* We're already in window 4. */
389 val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
390 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
391 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
392
393 return (val);
394 }
395
396 /*
397 * Write the MII serial port for the MII bit-bang module.
398 */
399 static void
xl_mii_bitbang_write(device_t dev,uint32_t val)400 xl_mii_bitbang_write(device_t dev, uint32_t val)
401 {
402 struct xl_softc *sc;
403
404 sc = device_get_softc(dev);
405
406 /* We're already in window 4. */
407 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
408 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
409 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
410 }
411
412 static int
xl_miibus_readreg(device_t dev,int phy,int reg)413 xl_miibus_readreg(device_t dev, int phy, int reg)
414 {
415 struct xl_softc *sc;
416
417 sc = device_get_softc(dev);
418
419 /* Select the window 4. */
420 XL_SEL_WIN(4);
421
422 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));
423 }
424
425 static int
xl_miibus_writereg(device_t dev,int phy,int reg,int data)426 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
427 {
428 struct xl_softc *sc;
429
430 sc = device_get_softc(dev);
431
432 /* Select the window 4. */
433 XL_SEL_WIN(4);
434
435 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);
436
437 return (0);
438 }
439
440 static void
xl_miibus_statchg(device_t dev)441 xl_miibus_statchg(device_t dev)
442 {
443 struct xl_softc *sc;
444 struct mii_data *mii;
445 uint8_t macctl;
446
447 sc = device_get_softc(dev);
448 mii = device_get_softc(sc->xl_miibus);
449
450 xl_setcfg(sc);
451
452 /* Set ASIC's duplex mode to match the PHY. */
453 XL_SEL_WIN(3);
454 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
455 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
456 macctl |= XL_MACCTRL_DUPLEX;
457 if (sc->xl_type == XL_TYPE_905B) {
458 if ((IFM_OPTIONS(mii->mii_media_active) &
459 IFM_ETH_RXPAUSE) != 0)
460 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB;
461 else
462 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
463 }
464 } else {
465 macctl &= ~XL_MACCTRL_DUPLEX;
466 if (sc->xl_type == XL_TYPE_905B)
467 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
468 }
469 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
470 }
471
472 /*
473 * Special support for the 3c905B-COMBO. This card has 10/100 support
474 * plus BNC and AUI ports. This means we will have both an miibus attached
475 * plus some non-MII media settings. In order to allow this, we have to
476 * add the extra media to the miibus's ifmedia struct, but we can't do
477 * that during xl_attach() because the miibus hasn't been attached yet.
478 * So instead, we wait until the miibus probe/attach is done, at which
479 * point we will get a callback telling is that it's safe to add our
480 * extra media.
481 */
482 static void
xl_miibus_mediainit(device_t dev)483 xl_miibus_mediainit(device_t dev)
484 {
485 struct xl_softc *sc;
486 struct mii_data *mii;
487 struct ifmedia *ifm;
488
489 sc = device_get_softc(dev);
490 mii = device_get_softc(sc->xl_miibus);
491 ifm = &mii->mii_media;
492
493 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
494 /*
495 * Check for a 10baseFL board in disguise.
496 */
497 if (sc->xl_type == XL_TYPE_905B &&
498 sc->xl_media == XL_MEDIAOPT_10FL) {
499 if (bootverbose)
500 device_printf(sc->xl_dev, "found 10baseFL\n");
501 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
502 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
503 NULL);
504 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
505 ifmedia_add(ifm,
506 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
507 } else {
508 if (bootverbose)
509 device_printf(sc->xl_dev, "found AUI\n");
510 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
511 }
512 }
513
514 if (sc->xl_media & XL_MEDIAOPT_BNC) {
515 if (bootverbose)
516 device_printf(sc->xl_dev, "found BNC\n");
517 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
518 }
519 }
520
521 /*
522 * The EEPROM is slow: give it time to come ready after issuing
523 * it a command.
524 */
525 static int
xl_eeprom_wait(struct xl_softc * sc)526 xl_eeprom_wait(struct xl_softc *sc)
527 {
528 int i;
529
530 for (i = 0; i < 100; i++) {
531 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
532 DELAY(162);
533 else
534 break;
535 }
536
537 if (i == 100) {
538 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
539 return (1);
540 }
541
542 return (0);
543 }
544
545 /*
546 * Read a sequence of words from the EEPROM. Note that ethernet address
547 * data is stored in the EEPROM in network byte order.
548 */
549 static int
xl_read_eeprom(struct xl_softc * sc,caddr_t dest,int off,int cnt,int swap)550 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
551 {
552 int err = 0, i;
553 u_int16_t word = 0, *ptr;
554
555 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
556 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
557 /*
558 * XXX: WARNING! DANGER!
559 * It's easy to accidentally overwrite the rom content!
560 * Note: the 3c575 uses 8bit EEPROM offsets.
561 */
562 XL_SEL_WIN(0);
563
564 if (xl_eeprom_wait(sc))
565 return (1);
566
567 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
568 off += 0x30;
569
570 for (i = 0; i < cnt; i++) {
571 if (sc->xl_flags & XL_FLAG_8BITROM)
572 CSR_WRITE_2(sc, XL_W0_EE_CMD,
573 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
574 else
575 CSR_WRITE_2(sc, XL_W0_EE_CMD,
576 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
577 err = xl_eeprom_wait(sc);
578 if (err)
579 break;
580 word = CSR_READ_2(sc, XL_W0_EE_DATA);
581 ptr = (u_int16_t *)(dest + (i * 2));
582 if (swap)
583 *ptr = ntohs(word);
584 else
585 *ptr = word;
586 }
587
588 return (err ? 1 : 0);
589 }
590
591 static void
xl_rxfilter(struct xl_softc * sc)592 xl_rxfilter(struct xl_softc *sc)
593 {
594
595 if (sc->xl_type == XL_TYPE_905B)
596 xl_rxfilter_90xB(sc);
597 else
598 xl_rxfilter_90x(sc);
599 }
600
601 /*
602 * NICs older than the 3c905B have only one multicast option, which
603 * is to enable reception of all multicast frames.
604 */
605 static void
xl_rxfilter_90x(struct xl_softc * sc)606 xl_rxfilter_90x(struct xl_softc *sc)
607 {
608 struct ifnet *ifp;
609 struct ifmultiaddr *ifma;
610 u_int8_t rxfilt;
611
612 XL_LOCK_ASSERT(sc);
613
614 ifp = sc->xl_ifp;
615
616 XL_SEL_WIN(5);
617 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
618 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
619 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL);
620
621 /* Set the individual bit to receive frames for this host only. */
622 rxfilt |= XL_RXFILTER_INDIVIDUAL;
623 /* Set capture broadcast bit to capture broadcast frames. */
624 if (ifp->if_flags & IFF_BROADCAST)
625 rxfilt |= XL_RXFILTER_BROADCAST;
626
627 /* If we want promiscuous mode, set the allframes bit. */
628 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
629 if (ifp->if_flags & IFF_PROMISC)
630 rxfilt |= XL_RXFILTER_ALLFRAMES;
631 if (ifp->if_flags & IFF_ALLMULTI)
632 rxfilt |= XL_RXFILTER_ALLMULTI;
633 } else {
634 if_maddr_rlock(ifp);
635 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
636 if (ifma->ifma_addr->sa_family != AF_LINK)
637 continue;
638 rxfilt |= XL_RXFILTER_ALLMULTI;
639 break;
640 }
641 if_maddr_runlock(ifp);
642 }
643
644 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
645 XL_SEL_WIN(7);
646 }
647
648 /*
649 * 3c905B adapters have a hash filter that we can program.
650 */
651 static void
xl_rxfilter_90xB(struct xl_softc * sc)652 xl_rxfilter_90xB(struct xl_softc *sc)
653 {
654 struct ifnet *ifp;
655 struct ifmultiaddr *ifma;
656 int i, mcnt;
657 u_int16_t h;
658 u_int8_t rxfilt;
659
660 XL_LOCK_ASSERT(sc);
661
662 ifp = sc->xl_ifp;
663
664 XL_SEL_WIN(5);
665 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
666 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
667 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL |
668 XL_RXFILTER_MULTIHASH);
669
670 /* Set the individual bit to receive frames for this host only. */
671 rxfilt |= XL_RXFILTER_INDIVIDUAL;
672 /* Set capture broadcast bit to capture broadcast frames. */
673 if (ifp->if_flags & IFF_BROADCAST)
674 rxfilt |= XL_RXFILTER_BROADCAST;
675
676 /* If we want promiscuous mode, set the allframes bit. */
677 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
678 if (ifp->if_flags & IFF_PROMISC)
679 rxfilt |= XL_RXFILTER_ALLFRAMES;
680 if (ifp->if_flags & IFF_ALLMULTI)
681 rxfilt |= XL_RXFILTER_ALLMULTI;
682 } else {
683 /* First, zot all the existing hash bits. */
684 for (i = 0; i < XL_HASHFILT_SIZE; i++)
685 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
686
687 /* Now program new ones. */
688 mcnt = 0;
689 if_maddr_rlock(ifp);
690 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
691 if (ifma->ifma_addr->sa_family != AF_LINK)
692 continue;
693 /*
694 * Note: the 3c905B currently only supports a 64-bit
695 * hash table, which means we really only need 6 bits,
696 * but the manual indicates that future chip revisions
697 * will have a 256-bit hash table, hence the routine
698 * is set up to calculate 8 bits of position info in
699 * case we need it some day.
700 * Note II, The Sequel: _CURRENT_ versions of the
701 * 3c905B have a 256 bit hash table. This means we have
702 * to use all 8 bits regardless. On older cards, the
703 * upper 2 bits will be ignored. Grrrr....
704 */
705 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
706 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
707 CSR_WRITE_2(sc, XL_COMMAND,
708 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
709 mcnt++;
710 }
711 if_maddr_runlock(ifp);
712 if (mcnt > 0)
713 rxfilt |= XL_RXFILTER_MULTIHASH;
714 }
715
716 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
717 XL_SEL_WIN(7);
718 }
719
720 static void
xl_setcfg(struct xl_softc * sc)721 xl_setcfg(struct xl_softc *sc)
722 {
723 u_int32_t icfg;
724
725 /*XL_LOCK_ASSERT(sc);*/
726
727 XL_SEL_WIN(3);
728 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
729 icfg &= ~XL_ICFG_CONNECTOR_MASK;
730 if (sc->xl_media & XL_MEDIAOPT_MII ||
731 sc->xl_media & XL_MEDIAOPT_BT4)
732 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
733 if (sc->xl_media & XL_MEDIAOPT_BTX)
734 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
735
736 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
737 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
738 }
739
740 static void
xl_setmode(struct xl_softc * sc,int media)741 xl_setmode(struct xl_softc *sc, int media)
742 {
743 u_int32_t icfg;
744 u_int16_t mediastat;
745 char *pmsg = "", *dmsg = "";
746
747 XL_LOCK_ASSERT(sc);
748
749 XL_SEL_WIN(4);
750 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
751 XL_SEL_WIN(3);
752 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
753
754 if (sc->xl_media & XL_MEDIAOPT_BT) {
755 if (IFM_SUBTYPE(media) == IFM_10_T) {
756 pmsg = "10baseT transceiver";
757 sc->xl_xcvr = XL_XCVR_10BT;
758 icfg &= ~XL_ICFG_CONNECTOR_MASK;
759 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
760 mediastat |= XL_MEDIASTAT_LINKBEAT |
761 XL_MEDIASTAT_JABGUARD;
762 mediastat &= ~XL_MEDIASTAT_SQEENB;
763 }
764 }
765
766 if (sc->xl_media & XL_MEDIAOPT_BFX) {
767 if (IFM_SUBTYPE(media) == IFM_100_FX) {
768 pmsg = "100baseFX port";
769 sc->xl_xcvr = XL_XCVR_100BFX;
770 icfg &= ~XL_ICFG_CONNECTOR_MASK;
771 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
772 mediastat |= XL_MEDIASTAT_LINKBEAT;
773 mediastat &= ~XL_MEDIASTAT_SQEENB;
774 }
775 }
776
777 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
778 if (IFM_SUBTYPE(media) == IFM_10_5) {
779 pmsg = "AUI port";
780 sc->xl_xcvr = XL_XCVR_AUI;
781 icfg &= ~XL_ICFG_CONNECTOR_MASK;
782 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
783 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
784 XL_MEDIASTAT_JABGUARD);
785 mediastat |= ~XL_MEDIASTAT_SQEENB;
786 }
787 if (IFM_SUBTYPE(media) == IFM_10_FL) {
788 pmsg = "10baseFL transceiver";
789 sc->xl_xcvr = XL_XCVR_AUI;
790 icfg &= ~XL_ICFG_CONNECTOR_MASK;
791 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
792 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
793 XL_MEDIASTAT_JABGUARD);
794 mediastat |= ~XL_MEDIASTAT_SQEENB;
795 }
796 }
797
798 if (sc->xl_media & XL_MEDIAOPT_BNC) {
799 if (IFM_SUBTYPE(media) == IFM_10_2) {
800 pmsg = "AUI port";
801 sc->xl_xcvr = XL_XCVR_COAX;
802 icfg &= ~XL_ICFG_CONNECTOR_MASK;
803 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
804 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
805 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
806 }
807 }
808
809 if ((media & IFM_GMASK) == IFM_FDX ||
810 IFM_SUBTYPE(media) == IFM_100_FX) {
811 dmsg = "full";
812 XL_SEL_WIN(3);
813 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
814 } else {
815 dmsg = "half";
816 XL_SEL_WIN(3);
817 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
818 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
819 }
820
821 if (IFM_SUBTYPE(media) == IFM_10_2)
822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
823 else
824 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
825
826 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
827 XL_SEL_WIN(4);
828 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
829
830 DELAY(800);
831 XL_SEL_WIN(7);
832
833 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
834 }
835
836 static void
xl_reset(struct xl_softc * sc)837 xl_reset(struct xl_softc *sc)
838 {
839 int i;
840
841 XL_LOCK_ASSERT(sc);
842
843 XL_SEL_WIN(0);
844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
845 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
846 XL_RESETOPT_DISADVFD:0));
847
848 /*
849 * If we're using memory mapped register mode, pause briefly
850 * after issuing the reset command before trying to access any
851 * other registers. With my 3c575C CardBus card, failing to do
852 * this results in the system locking up while trying to poll
853 * the command busy bit in the status register.
854 */
855 if (sc->xl_flags & XL_FLAG_USE_MMIO)
856 DELAY(100000);
857
858 for (i = 0; i < XL_TIMEOUT; i++) {
859 DELAY(10);
860 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
861 break;
862 }
863
864 if (i == XL_TIMEOUT)
865 device_printf(sc->xl_dev, "reset didn't complete\n");
866
867 /* Reset TX and RX. */
868 /* Note: the RX reset takes an absurd amount of time
869 * on newer versions of the Tornado chips such as those
870 * on the 3c905CX and newer 3c908C cards. We wait an
871 * extra amount of time so that xl_wait() doesn't complain
872 * and annoy the users.
873 */
874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
875 DELAY(100000);
876 xl_wait(sc);
877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
878 xl_wait(sc);
879
880 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
881 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
882 XL_SEL_WIN(2);
883 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
884 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
885 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
886 XL_RESETOPT_INVERT_LED : 0) |
887 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
888 XL_RESETOPT_INVERT_MII : 0));
889 }
890
891 /* Wait a little while for the chip to get its brains in order. */
892 DELAY(100000);
893 }
894
895 /*
896 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
897 * IDs against our list and return a device name if we find a match.
898 */
899 static int
xl_probe(device_t dev)900 xl_probe(device_t dev)
901 {
902 const struct xl_type *t;
903
904 t = xl_devs;
905
906 while (t->xl_name != NULL) {
907 if ((pci_get_vendor(dev) == t->xl_vid) &&
908 (pci_get_device(dev) == t->xl_did)) {
909 device_set_desc(dev, t->xl_name);
910 return (BUS_PROBE_DEFAULT);
911 }
912 t++;
913 }
914
915 return (ENXIO);
916 }
917
918 /*
919 * This routine is a kludge to work around possible hardware faults
920 * or manufacturing defects that can cause the media options register
921 * (or reset options register, as it's called for the first generation
922 * 3c90x adapters) to return an incorrect result. I have encountered
923 * one Dell Latitude laptop docking station with an integrated 3c905-TX
924 * which doesn't have any of the 'mediaopt' bits set. This screws up
925 * the attach routine pretty badly because it doesn't know what media
926 * to look for. If we find ourselves in this predicament, this routine
927 * will try to guess the media options values and warn the user of a
928 * possible manufacturing defect with his adapter/system/whatever.
929 */
930 static void
xl_mediacheck(struct xl_softc * sc)931 xl_mediacheck(struct xl_softc *sc)
932 {
933
934 /*
935 * If some of the media options bits are set, assume they are
936 * correct. If not, try to figure it out down below.
937 * XXX I should check for 10baseFL, but I don't have an adapter
938 * to test with.
939 */
940 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
941 /*
942 * Check the XCVR value. If it's not in the normal range
943 * of values, we need to fake it up here.
944 */
945 if (sc->xl_xcvr <= XL_XCVR_AUTO)
946 return;
947 else {
948 device_printf(sc->xl_dev,
949 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
950 device_printf(sc->xl_dev,
951 "choosing new default based on card type\n");
952 }
953 } else {
954 if (sc->xl_type == XL_TYPE_905B &&
955 sc->xl_media & XL_MEDIAOPT_10FL)
956 return;
957 device_printf(sc->xl_dev,
958 "WARNING: no media options bits set in the media options register!!\n");
959 device_printf(sc->xl_dev,
960 "this could be a manufacturing defect in your adapter or system\n");
961 device_printf(sc->xl_dev,
962 "attempting to guess media type; you should probably consult your vendor\n");
963 }
964
965 xl_choose_xcvr(sc, 1);
966 }
967
968 static void
xl_choose_xcvr(struct xl_softc * sc,int verbose)969 xl_choose_xcvr(struct xl_softc *sc, int verbose)
970 {
971 u_int16_t devid;
972
973 /*
974 * Read the device ID from the EEPROM.
975 * This is what's loaded into the PCI device ID register, so it has
976 * to be correct otherwise we wouldn't have gotten this far.
977 */
978 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
979
980 switch (devid) {
981 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
982 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
983 sc->xl_media = XL_MEDIAOPT_BT;
984 sc->xl_xcvr = XL_XCVR_10BT;
985 if (verbose)
986 device_printf(sc->xl_dev,
987 "guessing 10BaseT transceiver\n");
988 break;
989 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
990 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
991 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
992 sc->xl_xcvr = XL_XCVR_10BT;
993 if (verbose)
994 device_printf(sc->xl_dev,
995 "guessing COMBO (AUI/BNC/TP)\n");
996 break;
997 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
998 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
999 sc->xl_xcvr = XL_XCVR_10BT;
1000 if (verbose)
1001 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1002 break;
1003 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1004 sc->xl_media = XL_MEDIAOPT_10FL;
1005 sc->xl_xcvr = XL_XCVR_AUI;
1006 if (verbose)
1007 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1008 break;
1009 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1010 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1011 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1012 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1013 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1014 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1015 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1016 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1017 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1018 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1019 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1020 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1021 sc->xl_media = XL_MEDIAOPT_MII;
1022 sc->xl_xcvr = XL_XCVR_MII;
1023 if (verbose)
1024 device_printf(sc->xl_dev, "guessing MII\n");
1025 break;
1026 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1027 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1028 sc->xl_media = XL_MEDIAOPT_BT4;
1029 sc->xl_xcvr = XL_XCVR_MII;
1030 if (verbose)
1031 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1032 break;
1033 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1034 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1035 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1036 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1037 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1038 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1039 sc->xl_media = XL_MEDIAOPT_BTX;
1040 sc->xl_xcvr = XL_XCVR_AUTO;
1041 if (verbose)
1042 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1043 break;
1044 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1045 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1046 sc->xl_xcvr = XL_XCVR_AUTO;
1047 if (verbose)
1048 device_printf(sc->xl_dev,
1049 "guessing 10/100 plus BNC/AUI\n");
1050 break;
1051 default:
1052 device_printf(sc->xl_dev,
1053 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1054 sc->xl_media = XL_MEDIAOPT_BT;
1055 break;
1056 }
1057 }
1058
1059 /*
1060 * Attach the interface. Allocate softc structures, do ifmedia
1061 * setup and ethernet/BPF attach.
1062 */
1063 static int
xl_attach(device_t dev)1064 xl_attach(device_t dev)
1065 {
1066 u_char eaddr[ETHER_ADDR_LEN];
1067 u_int16_t sinfo2, xcvr[2];
1068 struct xl_softc *sc;
1069 struct ifnet *ifp;
1070 int media, pmcap;
1071 int error = 0, phy, rid, res, unit;
1072 uint16_t did;
1073
1074 sc = device_get_softc(dev);
1075 sc->xl_dev = dev;
1076
1077 unit = device_get_unit(dev);
1078
1079 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1080 MTX_DEF);
1081 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1082
1083 did = pci_get_device(dev);
1084
1085 sc->xl_flags = 0;
1086 if (did == TC_DEVICEID_HURRICANE_555)
1087 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1088 if (did == TC_DEVICEID_HURRICANE_556 ||
1089 did == TC_DEVICEID_HURRICANE_556B)
1090 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1091 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1092 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1093 if (did == TC_DEVICEID_HURRICANE_555 ||
1094 did == TC_DEVICEID_HURRICANE_556)
1095 sc->xl_flags |= XL_FLAG_8BITROM;
1096 if (did == TC_DEVICEID_HURRICANE_556B)
1097 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1098
1099 if (did == TC_DEVICEID_HURRICANE_575B ||
1100 did == TC_DEVICEID_HURRICANE_575C ||
1101 did == TC_DEVICEID_HURRICANE_656B ||
1102 did == TC_DEVICEID_TORNADO_656C)
1103 sc->xl_flags |= XL_FLAG_FUNCREG;
1104 if (did == TC_DEVICEID_HURRICANE_575A ||
1105 did == TC_DEVICEID_HURRICANE_575B ||
1106 did == TC_DEVICEID_HURRICANE_575C ||
1107 did == TC_DEVICEID_HURRICANE_656B ||
1108 did == TC_DEVICEID_TORNADO_656C)
1109 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1110 XL_FLAG_8BITROM;
1111 if (did == TC_DEVICEID_HURRICANE_656)
1112 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1113 if (did == TC_DEVICEID_HURRICANE_575B)
1114 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1115 if (did == TC_DEVICEID_HURRICANE_575C)
1116 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1117 if (did == TC_DEVICEID_TORNADO_656C)
1118 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1119 if (did == TC_DEVICEID_HURRICANE_656 ||
1120 did == TC_DEVICEID_HURRICANE_656B)
1121 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1122 XL_FLAG_INVERT_LED_PWR;
1123 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1124 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1125 sc->xl_flags |= XL_FLAG_PHYOK;
1126
1127 switch (did) {
1128 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1129 case TC_DEVICEID_HURRICANE_575A:
1130 case TC_DEVICEID_HURRICANE_575B:
1131 case TC_DEVICEID_HURRICANE_575C:
1132 sc->xl_flags |= XL_FLAG_NO_MMIO;
1133 break;
1134 default:
1135 break;
1136 }
1137
1138 /*
1139 * Map control/status registers.
1140 */
1141 pci_enable_busmaster(dev);
1142
1143 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1144 rid = XL_PCI_LOMEM;
1145 res = SYS_RES_MEMORY;
1146
1147 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1148 }
1149
1150 if (sc->xl_res != NULL) {
1151 sc->xl_flags |= XL_FLAG_USE_MMIO;
1152 if (bootverbose)
1153 device_printf(dev, "using memory mapped I/O\n");
1154 } else {
1155 rid = XL_PCI_LOIO;
1156 res = SYS_RES_IOPORT;
1157 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1158 if (sc->xl_res == NULL) {
1159 device_printf(dev, "couldn't map ports/memory\n");
1160 error = ENXIO;
1161 goto fail;
1162 }
1163 if (bootverbose)
1164 device_printf(dev, "using port I/O\n");
1165 }
1166
1167 sc->xl_btag = rman_get_bustag(sc->xl_res);
1168 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1169
1170 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1171 rid = XL_PCI_FUNCMEM;
1172 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1173 RF_ACTIVE);
1174
1175 if (sc->xl_fres == NULL) {
1176 device_printf(dev, "couldn't map funcreg memory\n");
1177 error = ENXIO;
1178 goto fail;
1179 }
1180
1181 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1182 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1183 }
1184
1185 /* Allocate interrupt */
1186 rid = 0;
1187 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1188 RF_SHAREABLE | RF_ACTIVE);
1189 if (sc->xl_irq == NULL) {
1190 device_printf(dev, "couldn't map interrupt\n");
1191 error = ENXIO;
1192 goto fail;
1193 }
1194
1195 /* Initialize interface name. */
1196 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1197 if (ifp == NULL) {
1198 device_printf(dev, "can not if_alloc()\n");
1199 error = ENOSPC;
1200 goto fail;
1201 }
1202 ifp->if_softc = sc;
1203 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1204
1205 /* Reset the adapter. */
1206 XL_LOCK(sc);
1207 xl_reset(sc);
1208 XL_UNLOCK(sc);
1209
1210 /*
1211 * Get station address from the EEPROM.
1212 */
1213 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1214 device_printf(dev, "failed to read station address\n");
1215 error = ENXIO;
1216 goto fail;
1217 }
1218
1219 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1220 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1221
1222 /*
1223 * Now allocate a tag for the DMA descriptor lists and a chunk
1224 * of DMA-able memory based on the tag. Also obtain the DMA
1225 * addresses of the RX and TX ring, which we'll need later.
1226 * All of our lists are allocated as a contiguous block
1227 * of memory.
1228 */
1229 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1230 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1231 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1232 &sc->xl_ldata.xl_rx_tag);
1233 if (error) {
1234 device_printf(dev, "failed to allocate rx dma tag\n");
1235 goto fail;
1236 }
1237
1238 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1239 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1240 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1241 if (error) {
1242 device_printf(dev, "no memory for rx list buffers!\n");
1243 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1244 sc->xl_ldata.xl_rx_tag = NULL;
1245 goto fail;
1246 }
1247
1248 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1249 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1250 XL_RX_LIST_SZ, xl_dma_map_addr,
1251 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1252 if (error) {
1253 device_printf(dev, "cannot get dma address of the rx ring!\n");
1254 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1255 sc->xl_ldata.xl_rx_dmamap);
1256 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1257 sc->xl_ldata.xl_rx_tag = NULL;
1258 goto fail;
1259 }
1260
1261 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1262 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1263 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1264 &sc->xl_ldata.xl_tx_tag);
1265 if (error) {
1266 device_printf(dev, "failed to allocate tx dma tag\n");
1267 goto fail;
1268 }
1269
1270 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1271 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1272 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1273 if (error) {
1274 device_printf(dev, "no memory for list buffers!\n");
1275 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1276 sc->xl_ldata.xl_tx_tag = NULL;
1277 goto fail;
1278 }
1279
1280 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1281 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1282 XL_TX_LIST_SZ, xl_dma_map_addr,
1283 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1284 if (error) {
1285 device_printf(dev, "cannot get dma address of the tx ring!\n");
1286 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1287 sc->xl_ldata.xl_tx_dmamap);
1288 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1289 sc->xl_ldata.xl_tx_tag = NULL;
1290 goto fail;
1291 }
1292
1293 /*
1294 * Allocate a DMA tag for the mapping of mbufs.
1295 */
1296 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1297 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1298 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1299 NULL, &sc->xl_mtag);
1300 if (error) {
1301 device_printf(dev, "failed to allocate mbuf dma tag\n");
1302 goto fail;
1303 }
1304
1305 /* We need a spare DMA map for the RX ring. */
1306 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1307 if (error)
1308 goto fail;
1309
1310 /*
1311 * Figure out the card type. 3c905B adapters have the
1312 * 'supportsNoTxLength' bit set in the capabilities
1313 * word in the EEPROM.
1314 * Note: my 3c575C CardBus card lies. It returns a value
1315 * of 0x1578 for its capabilities word, which is somewhat
1316 * nonsensical. Another way to distinguish a 3c90x chip
1317 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1318 * bit. This will only be set for 3c90x boomerage chips.
1319 */
1320 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1321 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1322 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1323 sc->xl_type = XL_TYPE_905B;
1324 else
1325 sc->xl_type = XL_TYPE_90X;
1326
1327 /* Check availability of WOL. */
1328 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1329 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
1330 sc->xl_pmcap = pmcap;
1331 sc->xl_flags |= XL_FLAG_WOL;
1332 sinfo2 = 0;
1333 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1334 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1335 device_printf(dev,
1336 "No auxiliary remote wakeup connector!\n");
1337 }
1338
1339 /* Set the TX start threshold for best performance. */
1340 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1341
1342 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1343 ifp->if_ioctl = xl_ioctl;
1344 ifp->if_capabilities = IFCAP_VLAN_MTU;
1345 if (sc->xl_type == XL_TYPE_905B) {
1346 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1347 #ifdef XL905B_TXCSUM_BROKEN
1348 ifp->if_capabilities |= IFCAP_RXCSUM;
1349 #else
1350 ifp->if_capabilities |= IFCAP_HWCSUM;
1351 #endif
1352 }
1353 if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1354 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1355 ifp->if_capenable = ifp->if_capabilities;
1356 #ifdef DEVICE_POLLING
1357 ifp->if_capabilities |= IFCAP_POLLING;
1358 #endif
1359 ifp->if_start = xl_start;
1360 ifp->if_init = xl_init;
1361 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1362 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1363 IFQ_SET_READY(&ifp->if_snd);
1364
1365 /*
1366 * Now we have to see what sort of media we have.
1367 * This includes probing for an MII interace and a
1368 * possible PHY.
1369 */
1370 XL_SEL_WIN(3);
1371 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1372 if (bootverbose)
1373 device_printf(dev, "media options word: %x\n", sc->xl_media);
1374
1375 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1376 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1377 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1378 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1379
1380 xl_mediacheck(sc);
1381
1382 if (sc->xl_media & XL_MEDIAOPT_MII ||
1383 sc->xl_media & XL_MEDIAOPT_BTX ||
1384 sc->xl_media & XL_MEDIAOPT_BT4) {
1385 if (bootverbose)
1386 device_printf(dev, "found MII/AUTO\n");
1387 xl_setcfg(sc);
1388 /*
1389 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK.
1390 * This is to guard against problems with certain 3Com ASIC
1391 * revisions that incorrectly map the internal transceiver
1392 * control registers at all MII addresses.
1393 */
1394 phy = MII_PHY_ANY;
1395 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1396 phy = 24;
1397 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1398 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
1399 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1400 if (error != 0) {
1401 device_printf(dev, "attaching PHYs failed\n");
1402 goto fail;
1403 }
1404 goto done;
1405 }
1406
1407 /*
1408 * Sanity check. If the user has selected "auto" and this isn't
1409 * a 10/100 card of some kind, we need to force the transceiver
1410 * type to something sane.
1411 */
1412 if (sc->xl_xcvr == XL_XCVR_AUTO)
1413 xl_choose_xcvr(sc, bootverbose);
1414
1415 /*
1416 * Do ifmedia setup.
1417 */
1418 if (sc->xl_media & XL_MEDIAOPT_BT) {
1419 if (bootverbose)
1420 device_printf(dev, "found 10baseT\n");
1421 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1422 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1423 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1424 ifmedia_add(&sc->ifmedia,
1425 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1426 }
1427
1428 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1429 /*
1430 * Check for a 10baseFL board in disguise.
1431 */
1432 if (sc->xl_type == XL_TYPE_905B &&
1433 sc->xl_media == XL_MEDIAOPT_10FL) {
1434 if (bootverbose)
1435 device_printf(dev, "found 10baseFL\n");
1436 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1437 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1438 0, NULL);
1439 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1440 ifmedia_add(&sc->ifmedia,
1441 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1442 } else {
1443 if (bootverbose)
1444 device_printf(dev, "found AUI\n");
1445 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1446 }
1447 }
1448
1449 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1450 if (bootverbose)
1451 device_printf(dev, "found BNC\n");
1452 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1453 }
1454
1455 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1456 if (bootverbose)
1457 device_printf(dev, "found 100baseFX\n");
1458 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1459 }
1460
1461 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1462 xl_choose_media(sc, &media);
1463
1464 if (sc->xl_miibus == NULL)
1465 ifmedia_set(&sc->ifmedia, media);
1466
1467 done:
1468 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1469 XL_SEL_WIN(0);
1470 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1471 }
1472
1473 /*
1474 * Call MI attach routine.
1475 */
1476 ether_ifattach(ifp, eaddr);
1477
1478 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1479 NULL, xl_intr, sc, &sc->xl_intrhand);
1480 if (error) {
1481 device_printf(dev, "couldn't set up irq\n");
1482 ether_ifdetach(ifp);
1483 goto fail;
1484 }
1485
1486 fail:
1487 if (error)
1488 xl_detach(dev);
1489
1490 return (error);
1491 }
1492
1493 /*
1494 * Choose a default media.
1495 * XXX This is a leaf function only called by xl_attach() and
1496 * acquires/releases the non-recursible driver mutex to
1497 * satisfy lock assertions.
1498 */
1499 static void
xl_choose_media(struct xl_softc * sc,int * media)1500 xl_choose_media(struct xl_softc *sc, int *media)
1501 {
1502
1503 XL_LOCK(sc);
1504
1505 switch (sc->xl_xcvr) {
1506 case XL_XCVR_10BT:
1507 *media = IFM_ETHER|IFM_10_T;
1508 xl_setmode(sc, *media);
1509 break;
1510 case XL_XCVR_AUI:
1511 if (sc->xl_type == XL_TYPE_905B &&
1512 sc->xl_media == XL_MEDIAOPT_10FL) {
1513 *media = IFM_ETHER|IFM_10_FL;
1514 xl_setmode(sc, *media);
1515 } else {
1516 *media = IFM_ETHER|IFM_10_5;
1517 xl_setmode(sc, *media);
1518 }
1519 break;
1520 case XL_XCVR_COAX:
1521 *media = IFM_ETHER|IFM_10_2;
1522 xl_setmode(sc, *media);
1523 break;
1524 case XL_XCVR_AUTO:
1525 case XL_XCVR_100BTX:
1526 case XL_XCVR_MII:
1527 /* Chosen by miibus */
1528 break;
1529 case XL_XCVR_100BFX:
1530 *media = IFM_ETHER|IFM_100_FX;
1531 break;
1532 default:
1533 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1534 sc->xl_xcvr);
1535 /*
1536 * This will probably be wrong, but it prevents
1537 * the ifmedia code from panicking.
1538 */
1539 *media = IFM_ETHER|IFM_10_T;
1540 break;
1541 }
1542
1543 XL_UNLOCK(sc);
1544 }
1545
1546 /*
1547 * Shutdown hardware and free up resources. This can be called any
1548 * time after the mutex has been initialized. It is called in both
1549 * the error case in attach and the normal detach case so it needs
1550 * to be careful about only freeing resources that have actually been
1551 * allocated.
1552 */
1553 static int
xl_detach(device_t dev)1554 xl_detach(device_t dev)
1555 {
1556 struct xl_softc *sc;
1557 struct ifnet *ifp;
1558 int rid, res;
1559
1560 sc = device_get_softc(dev);
1561 ifp = sc->xl_ifp;
1562
1563 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1564
1565 #ifdef DEVICE_POLLING
1566 if (ifp && ifp->if_capenable & IFCAP_POLLING)
1567 ether_poll_deregister(ifp);
1568 #endif
1569
1570 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1571 rid = XL_PCI_LOMEM;
1572 res = SYS_RES_MEMORY;
1573 } else {
1574 rid = XL_PCI_LOIO;
1575 res = SYS_RES_IOPORT;
1576 }
1577
1578 /* These should only be active if attach succeeded */
1579 if (device_is_attached(dev)) {
1580 XL_LOCK(sc);
1581 xl_stop(sc);
1582 XL_UNLOCK(sc);
1583 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1584 callout_drain(&sc->xl_tick_callout);
1585 ether_ifdetach(ifp);
1586 }
1587 if (sc->xl_miibus)
1588 device_delete_child(dev, sc->xl_miibus);
1589 bus_generic_detach(dev);
1590 ifmedia_removeall(&sc->ifmedia);
1591
1592 if (sc->xl_intrhand)
1593 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1594 if (sc->xl_irq)
1595 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1596 if (sc->xl_fres != NULL)
1597 bus_release_resource(dev, SYS_RES_MEMORY,
1598 XL_PCI_FUNCMEM, sc->xl_fres);
1599 if (sc->xl_res)
1600 bus_release_resource(dev, res, rid, sc->xl_res);
1601
1602 if (ifp)
1603 if_free(ifp);
1604
1605 if (sc->xl_mtag) {
1606 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1607 bus_dma_tag_destroy(sc->xl_mtag);
1608 }
1609 if (sc->xl_ldata.xl_rx_tag) {
1610 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1611 sc->xl_ldata.xl_rx_dmamap);
1612 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1613 sc->xl_ldata.xl_rx_dmamap);
1614 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1615 }
1616 if (sc->xl_ldata.xl_tx_tag) {
1617 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1618 sc->xl_ldata.xl_tx_dmamap);
1619 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1620 sc->xl_ldata.xl_tx_dmamap);
1621 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1622 }
1623
1624 mtx_destroy(&sc->xl_mtx);
1625
1626 return (0);
1627 }
1628
1629 /*
1630 * Initialize the transmit descriptors.
1631 */
1632 static int
xl_list_tx_init(struct xl_softc * sc)1633 xl_list_tx_init(struct xl_softc *sc)
1634 {
1635 struct xl_chain_data *cd;
1636 struct xl_list_data *ld;
1637 int error, i;
1638
1639 XL_LOCK_ASSERT(sc);
1640
1641 cd = &sc->xl_cdata;
1642 ld = &sc->xl_ldata;
1643 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1644 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1645 error = bus_dmamap_create(sc->xl_mtag, 0,
1646 &cd->xl_tx_chain[i].xl_map);
1647 if (error)
1648 return (error);
1649 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1650 i * sizeof(struct xl_list);
1651 if (i == (XL_TX_LIST_CNT - 1))
1652 cd->xl_tx_chain[i].xl_next = NULL;
1653 else
1654 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1655 }
1656
1657 cd->xl_tx_free = &cd->xl_tx_chain[0];
1658 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1659
1660 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1661 return (0);
1662 }
1663
1664 /*
1665 * Initialize the transmit descriptors.
1666 */
1667 static int
xl_list_tx_init_90xB(struct xl_softc * sc)1668 xl_list_tx_init_90xB(struct xl_softc *sc)
1669 {
1670 struct xl_chain_data *cd;
1671 struct xl_list_data *ld;
1672 int error, i;
1673
1674 XL_LOCK_ASSERT(sc);
1675
1676 cd = &sc->xl_cdata;
1677 ld = &sc->xl_ldata;
1678 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1679 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1680 error = bus_dmamap_create(sc->xl_mtag, 0,
1681 &cd->xl_tx_chain[i].xl_map);
1682 if (error)
1683 return (error);
1684 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1685 i * sizeof(struct xl_list);
1686 if (i == (XL_TX_LIST_CNT - 1))
1687 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1688 else
1689 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1690 if (i == 0)
1691 cd->xl_tx_chain[i].xl_prev =
1692 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1693 else
1694 cd->xl_tx_chain[i].xl_prev =
1695 &cd->xl_tx_chain[i - 1];
1696 }
1697
1698 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1699 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1700
1701 cd->xl_tx_prod = 1;
1702 cd->xl_tx_cons = 1;
1703 cd->xl_tx_cnt = 0;
1704
1705 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1706 return (0);
1707 }
1708
1709 /*
1710 * Initialize the RX descriptors and allocate mbufs for them. Note that
1711 * we arrange the descriptors in a closed ring, so that the last descriptor
1712 * points back to the first.
1713 */
1714 static int
xl_list_rx_init(struct xl_softc * sc)1715 xl_list_rx_init(struct xl_softc *sc)
1716 {
1717 struct xl_chain_data *cd;
1718 struct xl_list_data *ld;
1719 int error, i, next;
1720 u_int32_t nextptr;
1721
1722 XL_LOCK_ASSERT(sc);
1723
1724 cd = &sc->xl_cdata;
1725 ld = &sc->xl_ldata;
1726
1727 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1728 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1729 error = bus_dmamap_create(sc->xl_mtag, 0,
1730 &cd->xl_rx_chain[i].xl_map);
1731 if (error)
1732 return (error);
1733 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1734 if (error)
1735 return (error);
1736 if (i == (XL_RX_LIST_CNT - 1))
1737 next = 0;
1738 else
1739 next = i + 1;
1740 nextptr = ld->xl_rx_dmaaddr +
1741 next * sizeof(struct xl_list_onefrag);
1742 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1743 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1744 }
1745
1746 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1747 cd->xl_rx_head = &cd->xl_rx_chain[0];
1748
1749 return (0);
1750 }
1751
1752 /*
1753 * Initialize an RX descriptor and attach an MBUF cluster.
1754 * If we fail to do so, we need to leave the old mbuf and
1755 * the old DMA map untouched so that it can be reused.
1756 */
1757 static int
xl_newbuf(struct xl_softc * sc,struct xl_chain_onefrag * c)1758 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1759 {
1760 struct mbuf *m_new = NULL;
1761 bus_dmamap_t map;
1762 bus_dma_segment_t segs[1];
1763 int error, nseg;
1764
1765 XL_LOCK_ASSERT(sc);
1766
1767 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1768 if (m_new == NULL)
1769 return (ENOBUFS);
1770
1771 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1772
1773 /* Force longword alignment for packet payload. */
1774 m_adj(m_new, ETHER_ALIGN);
1775
1776 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1777 segs, &nseg, BUS_DMA_NOWAIT);
1778 if (error) {
1779 m_freem(m_new);
1780 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1781 error);
1782 return (error);
1783 }
1784 KASSERT(nseg == 1,
1785 ("%s: too many DMA segments (%d)", __func__, nseg));
1786
1787 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1788 map = c->xl_map;
1789 c->xl_map = sc->xl_tmpmap;
1790 sc->xl_tmpmap = map;
1791 c->xl_mbuf = m_new;
1792 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1793 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1794 c->xl_ptr->xl_status = 0;
1795 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1796 return (0);
1797 }
1798
1799 static int
xl_rx_resync(struct xl_softc * sc)1800 xl_rx_resync(struct xl_softc *sc)
1801 {
1802 struct xl_chain_onefrag *pos;
1803 int i;
1804
1805 XL_LOCK_ASSERT(sc);
1806
1807 pos = sc->xl_cdata.xl_rx_head;
1808
1809 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1810 if (pos->xl_ptr->xl_status)
1811 break;
1812 pos = pos->xl_next;
1813 }
1814
1815 if (i == XL_RX_LIST_CNT)
1816 return (0);
1817
1818 sc->xl_cdata.xl_rx_head = pos;
1819
1820 return (EAGAIN);
1821 }
1822
1823 /*
1824 * A frame has been uploaded: pass the resulting mbuf chain up to
1825 * the higher level protocols.
1826 */
1827 static int
xl_rxeof(struct xl_softc * sc)1828 xl_rxeof(struct xl_softc *sc)
1829 {
1830 struct mbuf *m;
1831 struct ifnet *ifp = sc->xl_ifp;
1832 struct xl_chain_onefrag *cur_rx;
1833 int total_len;
1834 int rx_npkts = 0;
1835 u_int32_t rxstat;
1836
1837 XL_LOCK_ASSERT(sc);
1838 again:
1839 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1840 BUS_DMASYNC_POSTREAD);
1841 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1842 #ifdef DEVICE_POLLING
1843 if (ifp->if_capenable & IFCAP_POLLING) {
1844 if (sc->rxcycles <= 0)
1845 break;
1846 sc->rxcycles--;
1847 }
1848 #endif
1849 cur_rx = sc->xl_cdata.xl_rx_head;
1850 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1851 total_len = rxstat & XL_RXSTAT_LENMASK;
1852 rx_npkts++;
1853
1854 /*
1855 * Since we have told the chip to allow large frames,
1856 * we need to trap giant frame errors in software. We allow
1857 * a little more than the normal frame size to account for
1858 * frames with VLAN tags.
1859 */
1860 if (total_len > XL_MAX_FRAMELEN)
1861 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1862
1863 /*
1864 * If an error occurs, update stats, clear the
1865 * status word and leave the mbuf cluster in place:
1866 * it should simply get re-used next time this descriptor
1867 * comes up in the ring.
1868 */
1869 if (rxstat & XL_RXSTAT_UP_ERROR) {
1870 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1871 cur_rx->xl_ptr->xl_status = 0;
1872 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1873 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1874 continue;
1875 }
1876
1877 /*
1878 * If the error bit was not set, the upload complete
1879 * bit should be set which means we have a valid packet.
1880 * If not, something truly strange has happened.
1881 */
1882 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1883 device_printf(sc->xl_dev,
1884 "bad receive status -- packet dropped\n");
1885 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1886 cur_rx->xl_ptr->xl_status = 0;
1887 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1888 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1889 continue;
1890 }
1891
1892 /* No errors; receive the packet. */
1893 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1894 BUS_DMASYNC_POSTREAD);
1895 m = cur_rx->xl_mbuf;
1896
1897 /*
1898 * Try to conjure up a new mbuf cluster. If that
1899 * fails, it means we have an out of memory condition and
1900 * should leave the buffer in place and continue. This will
1901 * result in a lost packet, but there's little else we
1902 * can do in this situation.
1903 */
1904 if (xl_newbuf(sc, cur_rx)) {
1905 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1906 cur_rx->xl_ptr->xl_status = 0;
1907 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1908 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1909 continue;
1910 }
1911 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1912 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1913
1914 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1915 m->m_pkthdr.rcvif = ifp;
1916 m->m_pkthdr.len = m->m_len = total_len;
1917
1918 if (ifp->if_capenable & IFCAP_RXCSUM) {
1919 /* Do IP checksum checking. */
1920 if (rxstat & XL_RXSTAT_IPCKOK)
1921 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1922 if (!(rxstat & XL_RXSTAT_IPCKERR))
1923 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1924 if ((rxstat & XL_RXSTAT_TCPCOK &&
1925 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1926 (rxstat & XL_RXSTAT_UDPCKOK &&
1927 !(rxstat & XL_RXSTAT_UDPCKERR))) {
1928 m->m_pkthdr.csum_flags |=
1929 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1930 m->m_pkthdr.csum_data = 0xffff;
1931 }
1932 }
1933
1934 XL_UNLOCK(sc);
1935 (*ifp->if_input)(ifp, m);
1936 XL_LOCK(sc);
1937
1938 /*
1939 * If we are running from the taskqueue, the interface
1940 * might have been stopped while we were passing the last
1941 * packet up the network stack.
1942 */
1943 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1944 return (rx_npkts);
1945 }
1946
1947 /*
1948 * Handle the 'end of channel' condition. When the upload
1949 * engine hits the end of the RX ring, it will stall. This
1950 * is our cue to flush the RX ring, reload the uplist pointer
1951 * register and unstall the engine.
1952 * XXX This is actually a little goofy. With the ThunderLAN
1953 * chip, you get an interrupt when the receiver hits the end
1954 * of the receive ring, which tells you exactly when you
1955 * you need to reload the ring pointer. Here we have to
1956 * fake it. I'm mad at myself for not being clever enough
1957 * to avoid the use of a goto here.
1958 */
1959 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1960 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1962 xl_wait(sc);
1963 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1964 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1966 goto again;
1967 }
1968 return (rx_npkts);
1969 }
1970
1971 /*
1972 * Taskqueue wrapper for xl_rxeof().
1973 */
1974 static void
xl_rxeof_task(void * arg,int pending)1975 xl_rxeof_task(void *arg, int pending)
1976 {
1977 struct xl_softc *sc = (struct xl_softc *)arg;
1978
1979 XL_LOCK(sc);
1980 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
1981 xl_rxeof(sc);
1982 XL_UNLOCK(sc);
1983 }
1984
1985 /*
1986 * A frame was downloaded to the chip. It's safe for us to clean up
1987 * the list buffers.
1988 */
1989 static void
xl_txeof(struct xl_softc * sc)1990 xl_txeof(struct xl_softc *sc)
1991 {
1992 struct xl_chain *cur_tx;
1993 struct ifnet *ifp = sc->xl_ifp;
1994
1995 XL_LOCK_ASSERT(sc);
1996
1997 /*
1998 * Go through our tx list and free mbufs for those
1999 * frames that have been uploaded. Note: the 3c905B
2000 * sets a special bit in the status word to let us
2001 * know that a frame has been downloaded, but the
2002 * original 3c900/3c905 adapters don't do that.
2003 * Consequently, we have to use a different test if
2004 * xl_type != XL_TYPE_905B.
2005 */
2006 while (sc->xl_cdata.xl_tx_head != NULL) {
2007 cur_tx = sc->xl_cdata.xl_tx_head;
2008
2009 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2010 break;
2011
2012 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2013 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2014 BUS_DMASYNC_POSTWRITE);
2015 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2016 m_freem(cur_tx->xl_mbuf);
2017 cur_tx->xl_mbuf = NULL;
2018 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2019 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2020
2021 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2022 sc->xl_cdata.xl_tx_free = cur_tx;
2023 }
2024
2025 if (sc->xl_cdata.xl_tx_head == NULL) {
2026 sc->xl_wdog_timer = 0;
2027 sc->xl_cdata.xl_tx_tail = NULL;
2028 } else {
2029 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2030 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2031 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2032 sc->xl_cdata.xl_tx_head->xl_phys);
2033 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2034 }
2035 }
2036 }
2037
2038 static void
xl_txeof_90xB(struct xl_softc * sc)2039 xl_txeof_90xB(struct xl_softc *sc)
2040 {
2041 struct xl_chain *cur_tx = NULL;
2042 struct ifnet *ifp = sc->xl_ifp;
2043 int idx;
2044
2045 XL_LOCK_ASSERT(sc);
2046
2047 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2048 BUS_DMASYNC_POSTREAD);
2049 idx = sc->xl_cdata.xl_tx_cons;
2050 while (idx != sc->xl_cdata.xl_tx_prod) {
2051 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2052
2053 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2054 XL_TXSTAT_DL_COMPLETE))
2055 break;
2056
2057 if (cur_tx->xl_mbuf != NULL) {
2058 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2059 BUS_DMASYNC_POSTWRITE);
2060 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2061 m_freem(cur_tx->xl_mbuf);
2062 cur_tx->xl_mbuf = NULL;
2063 }
2064
2065 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2066
2067 sc->xl_cdata.xl_tx_cnt--;
2068 XL_INC(idx, XL_TX_LIST_CNT);
2069 }
2070
2071 if (sc->xl_cdata.xl_tx_cnt == 0)
2072 sc->xl_wdog_timer = 0;
2073 sc->xl_cdata.xl_tx_cons = idx;
2074
2075 if (cur_tx != NULL)
2076 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2077 }
2078
2079 /*
2080 * TX 'end of channel' interrupt handler. Actually, we should
2081 * only get a 'TX complete' interrupt if there's a transmit error,
2082 * so this is really TX error handler.
2083 */
2084 static void
xl_txeoc(struct xl_softc * sc)2085 xl_txeoc(struct xl_softc *sc)
2086 {
2087 u_int8_t txstat;
2088
2089 XL_LOCK_ASSERT(sc);
2090
2091 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2092 if (txstat & XL_TXSTATUS_UNDERRUN ||
2093 txstat & XL_TXSTATUS_JABBER ||
2094 txstat & XL_TXSTATUS_RECLAIM) {
2095 device_printf(sc->xl_dev,
2096 "transmission error: 0x%02x\n", txstat);
2097 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2098 xl_wait(sc);
2099 if (sc->xl_type == XL_TYPE_905B) {
2100 if (sc->xl_cdata.xl_tx_cnt) {
2101 int i;
2102 struct xl_chain *c;
2103
2104 i = sc->xl_cdata.xl_tx_cons;
2105 c = &sc->xl_cdata.xl_tx_chain[i];
2106 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2107 c->xl_phys);
2108 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2109 sc->xl_wdog_timer = 5;
2110 }
2111 } else {
2112 if (sc->xl_cdata.xl_tx_head != NULL) {
2113 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2114 sc->xl_cdata.xl_tx_head->xl_phys);
2115 sc->xl_wdog_timer = 5;
2116 }
2117 }
2118 /*
2119 * Remember to set this for the
2120 * first generation 3c90X chips.
2121 */
2122 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2123 if (txstat & XL_TXSTATUS_UNDERRUN &&
2124 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2125 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2126 device_printf(sc->xl_dev,
2127 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2128 }
2129 CSR_WRITE_2(sc, XL_COMMAND,
2130 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2131 if (sc->xl_type == XL_TYPE_905B) {
2132 CSR_WRITE_2(sc, XL_COMMAND,
2133 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2134 }
2135 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2136 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2137 } else {
2138 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2139 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2140 }
2141 /*
2142 * Write an arbitrary byte to the TX_STATUS register
2143 * to clear this interrupt/error and advance to the next.
2144 */
2145 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2146 }
2147 }
2148
2149 static void
xl_intr(void * arg)2150 xl_intr(void *arg)
2151 {
2152 struct xl_softc *sc = arg;
2153 struct ifnet *ifp = sc->xl_ifp;
2154 u_int16_t status;
2155
2156 XL_LOCK(sc);
2157
2158 #ifdef DEVICE_POLLING
2159 if (ifp->if_capenable & IFCAP_POLLING) {
2160 XL_UNLOCK(sc);
2161 return;
2162 }
2163 #endif
2164
2165 for (;;) {
2166 status = CSR_READ_2(sc, XL_STATUS);
2167 if ((status & XL_INTRS) == 0 || status == 0xFFFF)
2168 break;
2169 CSR_WRITE_2(sc, XL_COMMAND,
2170 XL_CMD_INTR_ACK|(status & XL_INTRS));
2171 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2172 break;
2173
2174 if (status & XL_STAT_UP_COMPLETE) {
2175 if (xl_rxeof(sc) == 0) {
2176 while (xl_rx_resync(sc))
2177 xl_rxeof(sc);
2178 }
2179 }
2180
2181 if (status & XL_STAT_DOWN_COMPLETE) {
2182 if (sc->xl_type == XL_TYPE_905B)
2183 xl_txeof_90xB(sc);
2184 else
2185 xl_txeof(sc);
2186 }
2187
2188 if (status & XL_STAT_TX_COMPLETE) {
2189 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2190 xl_txeoc(sc);
2191 }
2192
2193 if (status & XL_STAT_ADFAIL) {
2194 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2195 xl_init_locked(sc);
2196 break;
2197 }
2198
2199 if (status & XL_STAT_STATSOFLOW)
2200 xl_stats_update(sc);
2201 }
2202
2203 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2204 ifp->if_drv_flags & IFF_DRV_RUNNING) {
2205 if (sc->xl_type == XL_TYPE_905B)
2206 xl_start_90xB_locked(ifp);
2207 else
2208 xl_start_locked(ifp);
2209 }
2210
2211 XL_UNLOCK(sc);
2212 }
2213
2214 #ifdef DEVICE_POLLING
2215 static int
xl_poll(struct ifnet * ifp,enum poll_cmd cmd,int count)2216 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2217 {
2218 struct xl_softc *sc = ifp->if_softc;
2219 int rx_npkts = 0;
2220
2221 XL_LOCK(sc);
2222 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2223 rx_npkts = xl_poll_locked(ifp, cmd, count);
2224 XL_UNLOCK(sc);
2225 return (rx_npkts);
2226 }
2227
2228 static int
xl_poll_locked(struct ifnet * ifp,enum poll_cmd cmd,int count)2229 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2230 {
2231 struct xl_softc *sc = ifp->if_softc;
2232 int rx_npkts;
2233
2234 XL_LOCK_ASSERT(sc);
2235
2236 sc->rxcycles = count;
2237 rx_npkts = xl_rxeof(sc);
2238 if (sc->xl_type == XL_TYPE_905B)
2239 xl_txeof_90xB(sc);
2240 else
2241 xl_txeof(sc);
2242
2243 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2244 if (sc->xl_type == XL_TYPE_905B)
2245 xl_start_90xB_locked(ifp);
2246 else
2247 xl_start_locked(ifp);
2248 }
2249
2250 if (cmd == POLL_AND_CHECK_STATUS) {
2251 u_int16_t status;
2252
2253 status = CSR_READ_2(sc, XL_STATUS);
2254 if (status & XL_INTRS && status != 0xFFFF) {
2255 CSR_WRITE_2(sc, XL_COMMAND,
2256 XL_CMD_INTR_ACK|(status & XL_INTRS));
2257
2258 if (status & XL_STAT_TX_COMPLETE) {
2259 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2260 xl_txeoc(sc);
2261 }
2262
2263 if (status & XL_STAT_ADFAIL) {
2264 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2265 xl_init_locked(sc);
2266 }
2267
2268 if (status & XL_STAT_STATSOFLOW)
2269 xl_stats_update(sc);
2270 }
2271 }
2272 return (rx_npkts);
2273 }
2274 #endif /* DEVICE_POLLING */
2275
2276 static void
xl_tick(void * xsc)2277 xl_tick(void *xsc)
2278 {
2279 struct xl_softc *sc = xsc;
2280 struct mii_data *mii;
2281
2282 XL_LOCK_ASSERT(sc);
2283
2284 if (sc->xl_miibus != NULL) {
2285 mii = device_get_softc(sc->xl_miibus);
2286 mii_tick(mii);
2287 }
2288
2289 xl_stats_update(sc);
2290 if (xl_watchdog(sc) == EJUSTRETURN)
2291 return;
2292
2293 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2294 }
2295
2296 static void
xl_stats_update(struct xl_softc * sc)2297 xl_stats_update(struct xl_softc *sc)
2298 {
2299 struct ifnet *ifp = sc->xl_ifp;
2300 struct xl_stats xl_stats;
2301 u_int8_t *p;
2302 int i;
2303
2304 XL_LOCK_ASSERT(sc);
2305
2306 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2307
2308 p = (u_int8_t *)&xl_stats;
2309
2310 /* Read all the stats registers. */
2311 XL_SEL_WIN(6);
2312
2313 for (i = 0; i < 16; i++)
2314 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2315
2316 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun);
2317
2318 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2319 xl_stats.xl_tx_multi_collision +
2320 xl_stats.xl_tx_single_collision +
2321 xl_stats.xl_tx_late_collision);
2322
2323 /*
2324 * Boomerang and cyclone chips have an extra stats counter
2325 * in window 4 (BadSSD). We have to read this too in order
2326 * to clear out all the stats registers and avoid a statsoflow
2327 * interrupt.
2328 */
2329 XL_SEL_WIN(4);
2330 CSR_READ_1(sc, XL_W4_BADSSD);
2331 XL_SEL_WIN(7);
2332 }
2333
2334 /*
2335 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2336 * pointers to the fragment pointers.
2337 */
2338 static int
xl_encap(struct xl_softc * sc,struct xl_chain * c,struct mbuf ** m_head)2339 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2340 {
2341 struct mbuf *m_new;
2342 struct ifnet *ifp = sc->xl_ifp;
2343 int error, i, nseg, total_len;
2344 u_int32_t status;
2345
2346 XL_LOCK_ASSERT(sc);
2347
2348 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2349 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2350
2351 if (error && error != EFBIG) {
2352 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2353 return (error);
2354 }
2355
2356 /*
2357 * Handle special case: we used up all 63 fragments,
2358 * but we have more mbufs left in the chain. Copy the
2359 * data into an mbuf cluster. Note that we don't
2360 * bother clearing the values in the other fragment
2361 * pointers/counters; it wouldn't gain us anything,
2362 * and would waste cycles.
2363 */
2364 if (error) {
2365 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS);
2366 if (m_new == NULL) {
2367 m_freem(*m_head);
2368 *m_head = NULL;
2369 return (ENOBUFS);
2370 }
2371 *m_head = m_new;
2372
2373 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2374 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2375 if (error) {
2376 m_freem(*m_head);
2377 *m_head = NULL;
2378 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2379 return (error);
2380 }
2381 }
2382
2383 KASSERT(nseg <= XL_MAXFRAGS,
2384 ("%s: too many DMA segments (%d)", __func__, nseg));
2385 if (nseg == 0) {
2386 m_freem(*m_head);
2387 *m_head = NULL;
2388 return (EIO);
2389 }
2390 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2391
2392 total_len = 0;
2393 for (i = 0; i < nseg; i++) {
2394 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2395 ("segment size too large"));
2396 c->xl_ptr->xl_frag[i].xl_addr =
2397 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2398 c->xl_ptr->xl_frag[i].xl_len =
2399 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2400 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2401 }
2402 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG);
2403
2404 if (sc->xl_type == XL_TYPE_905B) {
2405 status = XL_TXSTAT_RND_DEFEAT;
2406
2407 #ifndef XL905B_TXCSUM_BROKEN
2408 if ((*m_head)->m_pkthdr.csum_flags) {
2409 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2410 status |= XL_TXSTAT_IPCKSUM;
2411 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2412 status |= XL_TXSTAT_TCPCKSUM;
2413 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2414 status |= XL_TXSTAT_UDPCKSUM;
2415 }
2416 #endif
2417 } else
2418 status = total_len;
2419 c->xl_ptr->xl_status = htole32(status);
2420 c->xl_ptr->xl_next = 0;
2421
2422 c->xl_mbuf = *m_head;
2423 return (0);
2424 }
2425
2426 /*
2427 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2428 * to the mbuf data regions directly in the transmit lists. We also save a
2429 * copy of the pointers since the transmit list fragment pointers are
2430 * physical addresses.
2431 */
2432
2433 static void
xl_start(struct ifnet * ifp)2434 xl_start(struct ifnet *ifp)
2435 {
2436 struct xl_softc *sc = ifp->if_softc;
2437
2438 XL_LOCK(sc);
2439
2440 if (sc->xl_type == XL_TYPE_905B)
2441 xl_start_90xB_locked(ifp);
2442 else
2443 xl_start_locked(ifp);
2444
2445 XL_UNLOCK(sc);
2446 }
2447
2448 static void
xl_start_locked(struct ifnet * ifp)2449 xl_start_locked(struct ifnet *ifp)
2450 {
2451 struct xl_softc *sc = ifp->if_softc;
2452 struct mbuf *m_head;
2453 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2454 struct xl_chain *prev_tx;
2455 int error;
2456
2457 XL_LOCK_ASSERT(sc);
2458
2459 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2460 IFF_DRV_RUNNING)
2461 return;
2462 /*
2463 * Check for an available queue slot. If there are none,
2464 * punt.
2465 */
2466 if (sc->xl_cdata.xl_tx_free == NULL) {
2467 xl_txeoc(sc);
2468 xl_txeof(sc);
2469 if (sc->xl_cdata.xl_tx_free == NULL) {
2470 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2471 return;
2472 }
2473 }
2474
2475 start_tx = sc->xl_cdata.xl_tx_free;
2476
2477 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2478 sc->xl_cdata.xl_tx_free != NULL;) {
2479 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2480 if (m_head == NULL)
2481 break;
2482
2483 /* Pick a descriptor off the free list. */
2484 prev_tx = cur_tx;
2485 cur_tx = sc->xl_cdata.xl_tx_free;
2486
2487 /* Pack the data into the descriptor. */
2488 error = xl_encap(sc, cur_tx, &m_head);
2489 if (error) {
2490 cur_tx = prev_tx;
2491 if (m_head == NULL)
2492 break;
2493 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2494 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2495 break;
2496 }
2497
2498 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2499 cur_tx->xl_next = NULL;
2500
2501 /* Chain it together. */
2502 if (prev != NULL) {
2503 prev->xl_next = cur_tx;
2504 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2505 }
2506 prev = cur_tx;
2507
2508 /*
2509 * If there's a BPF listener, bounce a copy of this frame
2510 * to him.
2511 */
2512 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2513 }
2514
2515 /*
2516 * If there are no packets queued, bail.
2517 */
2518 if (cur_tx == NULL)
2519 return;
2520
2521 /*
2522 * Place the request for the upload interrupt
2523 * in the last descriptor in the chain. This way, if
2524 * we're chaining several packets at once, we'll only
2525 * get an interrupt once for the whole chain rather than
2526 * once for each packet.
2527 */
2528 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2529
2530 /*
2531 * Queue the packets. If the TX channel is clear, update
2532 * the downlist pointer register.
2533 */
2534 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2535 xl_wait(sc);
2536
2537 if (sc->xl_cdata.xl_tx_head != NULL) {
2538 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2539 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2540 htole32(start_tx->xl_phys);
2541 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2542 htole32(~XL_TXSTAT_DL_INTR);
2543 sc->xl_cdata.xl_tx_tail = cur_tx;
2544 } else {
2545 sc->xl_cdata.xl_tx_head = start_tx;
2546 sc->xl_cdata.xl_tx_tail = cur_tx;
2547 }
2548 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2549 BUS_DMASYNC_PREWRITE);
2550 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2551 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2552
2553 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2554
2555 XL_SEL_WIN(7);
2556
2557 /*
2558 * Set a timeout in case the chip goes out to lunch.
2559 */
2560 sc->xl_wdog_timer = 5;
2561
2562 /*
2563 * XXX Under certain conditions, usually on slower machines
2564 * where interrupts may be dropped, it's possible for the
2565 * adapter to chew up all the buffers in the receive ring
2566 * and stall, without us being able to do anything about it.
2567 * To guard against this, we need to make a pass over the
2568 * RX queue to make sure there aren't any packets pending.
2569 * Doing it here means we can flush the receive ring at the
2570 * same time the chip is DMAing the transmit descriptors we
2571 * just gave it.
2572 *
2573 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2574 * nature of their chips in all their marketing literature;
2575 * we may as well take advantage of it. :)
2576 */
2577 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2578 }
2579
2580 static void
xl_start_90xB_locked(struct ifnet * ifp)2581 xl_start_90xB_locked(struct ifnet *ifp)
2582 {
2583 struct xl_softc *sc = ifp->if_softc;
2584 struct mbuf *m_head;
2585 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2586 struct xl_chain *prev_tx;
2587 int error, idx;
2588
2589 XL_LOCK_ASSERT(sc);
2590
2591 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2592 IFF_DRV_RUNNING)
2593 return;
2594
2595 idx = sc->xl_cdata.xl_tx_prod;
2596 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2597
2598 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2599 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2600 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2601 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2602 break;
2603 }
2604
2605 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2606 if (m_head == NULL)
2607 break;
2608
2609 prev_tx = cur_tx;
2610 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2611
2612 /* Pack the data into the descriptor. */
2613 error = xl_encap(sc, cur_tx, &m_head);
2614 if (error) {
2615 cur_tx = prev_tx;
2616 if (m_head == NULL)
2617 break;
2618 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2619 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2620 break;
2621 }
2622
2623 /* Chain it together. */
2624 if (prev != NULL)
2625 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2626 prev = cur_tx;
2627
2628 /*
2629 * If there's a BPF listener, bounce a copy of this frame
2630 * to him.
2631 */
2632 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2633
2634 XL_INC(idx, XL_TX_LIST_CNT);
2635 sc->xl_cdata.xl_tx_cnt++;
2636 }
2637
2638 /*
2639 * If there are no packets queued, bail.
2640 */
2641 if (cur_tx == NULL)
2642 return;
2643
2644 /*
2645 * Place the request for the upload interrupt
2646 * in the last descriptor in the chain. This way, if
2647 * we're chaining several packets at once, we'll only
2648 * get an interrupt once for the whole chain rather than
2649 * once for each packet.
2650 */
2651 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2652
2653 /* Start transmission */
2654 sc->xl_cdata.xl_tx_prod = idx;
2655 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2656 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2657 BUS_DMASYNC_PREWRITE);
2658
2659 /*
2660 * Set a timeout in case the chip goes out to lunch.
2661 */
2662 sc->xl_wdog_timer = 5;
2663 }
2664
2665 static void
xl_init(void * xsc)2666 xl_init(void *xsc)
2667 {
2668 struct xl_softc *sc = xsc;
2669
2670 XL_LOCK(sc);
2671 xl_init_locked(sc);
2672 XL_UNLOCK(sc);
2673 }
2674
2675 static void
xl_init_locked(struct xl_softc * sc)2676 xl_init_locked(struct xl_softc *sc)
2677 {
2678 struct ifnet *ifp = sc->xl_ifp;
2679 int error, i;
2680 struct mii_data *mii = NULL;
2681
2682 XL_LOCK_ASSERT(sc);
2683
2684 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2685 return;
2686 /*
2687 * Cancel pending I/O and free all RX/TX buffers.
2688 */
2689 xl_stop(sc);
2690
2691 /* Reset the chip to a known state. */
2692 xl_reset(sc);
2693
2694 if (sc->xl_miibus == NULL) {
2695 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2696 xl_wait(sc);
2697 }
2698 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2699 xl_wait(sc);
2700 DELAY(10000);
2701
2702 if (sc->xl_miibus != NULL)
2703 mii = device_get_softc(sc->xl_miibus);
2704
2705 /*
2706 * Clear WOL status and disable all WOL feature as WOL
2707 * would interfere Rx operation under normal environments.
2708 */
2709 if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2710 XL_SEL_WIN(7);
2711 CSR_READ_2(sc, XL_W7_BM_PME);
2712 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2713 }
2714 /* Init our MAC address */
2715 XL_SEL_WIN(2);
2716 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2717 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2718 IF_LLADDR(sc->xl_ifp)[i]);
2719 }
2720
2721 /* Clear the station mask. */
2722 for (i = 0; i < 3; i++)
2723 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2724 #ifdef notdef
2725 /* Reset TX and RX. */
2726 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2727 xl_wait(sc);
2728 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2729 xl_wait(sc);
2730 #endif
2731 /* Init circular RX list. */
2732 error = xl_list_rx_init(sc);
2733 if (error) {
2734 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2735 error);
2736 xl_stop(sc);
2737 return;
2738 }
2739
2740 /* Init TX descriptors. */
2741 if (sc->xl_type == XL_TYPE_905B)
2742 error = xl_list_tx_init_90xB(sc);
2743 else
2744 error = xl_list_tx_init(sc);
2745 if (error) {
2746 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2747 error);
2748 xl_stop(sc);
2749 return;
2750 }
2751
2752 /*
2753 * Set the TX freethresh value.
2754 * Note that this has no effect on 3c905B "cyclone"
2755 * cards but is required for 3c900/3c905 "boomerang"
2756 * cards in order to enable the download engine.
2757 */
2758 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2759
2760 /* Set the TX start threshold for best performance. */
2761 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2762
2763 /*
2764 * If this is a 3c905B, also set the tx reclaim threshold.
2765 * This helps cut down on the number of tx reclaim errors
2766 * that could happen on a busy network. The chip multiplies
2767 * the register value by 16 to obtain the actual threshold
2768 * in bytes, so we divide by 16 when setting the value here.
2769 * The existing threshold value can be examined by reading
2770 * the register at offset 9 in window 5.
2771 */
2772 if (sc->xl_type == XL_TYPE_905B) {
2773 CSR_WRITE_2(sc, XL_COMMAND,
2774 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2775 }
2776
2777 /* Set RX filter bits. */
2778 xl_rxfilter(sc);
2779
2780 /*
2781 * Load the address of the RX list. We have to
2782 * stall the upload engine before we can manipulate
2783 * the uplist pointer register, then unstall it when
2784 * we're finished. We also have to wait for the
2785 * stall command to complete before proceeding.
2786 * Note that we have to do this after any RX resets
2787 * have completed since the uplist register is cleared
2788 * by a reset.
2789 */
2790 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2791 xl_wait(sc);
2792 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2793 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2794 xl_wait(sc);
2795
2796 if (sc->xl_type == XL_TYPE_905B) {
2797 /* Set polling interval */
2798 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2799 /* Load the address of the TX list */
2800 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2801 xl_wait(sc);
2802 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2803 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2804 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2805 xl_wait(sc);
2806 }
2807
2808 /*
2809 * If the coax transceiver is on, make sure to enable
2810 * the DC-DC converter.
2811 */
2812 XL_SEL_WIN(3);
2813 if (sc->xl_xcvr == XL_XCVR_COAX)
2814 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2815 else
2816 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2817
2818 /*
2819 * increase packet size to allow reception of 802.1q or ISL packets.
2820 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2821 * control register. For 3c90xB/C chips, use the RX packet size
2822 * register.
2823 */
2824
2825 if (sc->xl_type == XL_TYPE_905B)
2826 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2827 else {
2828 u_int8_t macctl;
2829 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2830 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2831 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2832 }
2833
2834 /* Clear out the stats counters. */
2835 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2836 xl_stats_update(sc);
2837 XL_SEL_WIN(4);
2838 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2840
2841 /*
2842 * Enable interrupts.
2843 */
2844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2846 #ifdef DEVICE_POLLING
2847 /* Disable interrupts if we are polling. */
2848 if (ifp->if_capenable & IFCAP_POLLING)
2849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2850 else
2851 #endif
2852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2853 if (sc->xl_flags & XL_FLAG_FUNCREG)
2854 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2855
2856 /* Set the RX early threshold */
2857 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2858 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2859
2860 /* Enable receiver and transmitter. */
2861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2862 xl_wait(sc);
2863 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2864 xl_wait(sc);
2865
2866 /* XXX Downcall to miibus. */
2867 if (mii != NULL)
2868 mii_mediachg(mii);
2869
2870 /* Select window 7 for normal operations. */
2871 XL_SEL_WIN(7);
2872
2873 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2874 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2875
2876 sc->xl_wdog_timer = 0;
2877 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2878 }
2879
2880 /*
2881 * Set media options.
2882 */
2883 static int
xl_ifmedia_upd(struct ifnet * ifp)2884 xl_ifmedia_upd(struct ifnet *ifp)
2885 {
2886 struct xl_softc *sc = ifp->if_softc;
2887 struct ifmedia *ifm = NULL;
2888 struct mii_data *mii = NULL;
2889
2890 XL_LOCK(sc);
2891
2892 if (sc->xl_miibus != NULL)
2893 mii = device_get_softc(sc->xl_miibus);
2894 if (mii == NULL)
2895 ifm = &sc->ifmedia;
2896 else
2897 ifm = &mii->mii_media;
2898
2899 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2900 case IFM_100_FX:
2901 case IFM_10_FL:
2902 case IFM_10_2:
2903 case IFM_10_5:
2904 xl_setmode(sc, ifm->ifm_media);
2905 XL_UNLOCK(sc);
2906 return (0);
2907 }
2908
2909 if (sc->xl_media & XL_MEDIAOPT_MII ||
2910 sc->xl_media & XL_MEDIAOPT_BTX ||
2911 sc->xl_media & XL_MEDIAOPT_BT4) {
2912 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2913 xl_init_locked(sc);
2914 } else {
2915 xl_setmode(sc, ifm->ifm_media);
2916 }
2917
2918 XL_UNLOCK(sc);
2919
2920 return (0);
2921 }
2922
2923 /*
2924 * Report current media status.
2925 */
2926 static void
xl_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)2927 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2928 {
2929 struct xl_softc *sc = ifp->if_softc;
2930 u_int32_t icfg;
2931 u_int16_t status = 0;
2932 struct mii_data *mii = NULL;
2933
2934 XL_LOCK(sc);
2935
2936 if (sc->xl_miibus != NULL)
2937 mii = device_get_softc(sc->xl_miibus);
2938
2939 XL_SEL_WIN(4);
2940 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2941
2942 XL_SEL_WIN(3);
2943 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2944 icfg >>= XL_ICFG_CONNECTOR_BITS;
2945
2946 ifmr->ifm_active = IFM_ETHER;
2947 ifmr->ifm_status = IFM_AVALID;
2948
2949 if ((status & XL_MEDIASTAT_CARRIER) == 0)
2950 ifmr->ifm_status |= IFM_ACTIVE;
2951
2952 switch (icfg) {
2953 case XL_XCVR_10BT:
2954 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2955 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2956 ifmr->ifm_active |= IFM_FDX;
2957 else
2958 ifmr->ifm_active |= IFM_HDX;
2959 break;
2960 case XL_XCVR_AUI:
2961 if (sc->xl_type == XL_TYPE_905B &&
2962 sc->xl_media == XL_MEDIAOPT_10FL) {
2963 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2964 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2965 ifmr->ifm_active |= IFM_FDX;
2966 else
2967 ifmr->ifm_active |= IFM_HDX;
2968 } else
2969 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2970 break;
2971 case XL_XCVR_COAX:
2972 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2973 break;
2974 /*
2975 * XXX MII and BTX/AUTO should be separate cases.
2976 */
2977
2978 case XL_XCVR_100BTX:
2979 case XL_XCVR_AUTO:
2980 case XL_XCVR_MII:
2981 if (mii != NULL) {
2982 mii_pollstat(mii);
2983 ifmr->ifm_active = mii->mii_media_active;
2984 ifmr->ifm_status = mii->mii_media_status;
2985 }
2986 break;
2987 case XL_XCVR_100BFX:
2988 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2989 break;
2990 default:
2991 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
2992 break;
2993 }
2994
2995 XL_UNLOCK(sc);
2996 }
2997
2998 static int
xl_ioctl(struct ifnet * ifp,u_long command,caddr_t data)2999 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3000 {
3001 struct xl_softc *sc = ifp->if_softc;
3002 struct ifreq *ifr = (struct ifreq *) data;
3003 int error = 0, mask;
3004 struct mii_data *mii = NULL;
3005
3006 switch (command) {
3007 case SIOCSIFFLAGS:
3008 XL_LOCK(sc);
3009 if (ifp->if_flags & IFF_UP) {
3010 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3011 (ifp->if_flags ^ sc->xl_if_flags) &
3012 (IFF_PROMISC | IFF_ALLMULTI))
3013 xl_rxfilter(sc);
3014 else
3015 xl_init_locked(sc);
3016 } else {
3017 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3018 xl_stop(sc);
3019 }
3020 sc->xl_if_flags = ifp->if_flags;
3021 XL_UNLOCK(sc);
3022 break;
3023 case SIOCADDMULTI:
3024 case SIOCDELMULTI:
3025 /* XXX Downcall from if_addmulti() possibly with locks held. */
3026 XL_LOCK(sc);
3027 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3028 xl_rxfilter(sc);
3029 XL_UNLOCK(sc);
3030 break;
3031 case SIOCGIFMEDIA:
3032 case SIOCSIFMEDIA:
3033 if (sc->xl_miibus != NULL)
3034 mii = device_get_softc(sc->xl_miibus);
3035 if (mii == NULL)
3036 error = ifmedia_ioctl(ifp, ifr,
3037 &sc->ifmedia, command);
3038 else
3039 error = ifmedia_ioctl(ifp, ifr,
3040 &mii->mii_media, command);
3041 break;
3042 case SIOCSIFCAP:
3043 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3044 #ifdef DEVICE_POLLING
3045 if ((mask & IFCAP_POLLING) != 0 &&
3046 (ifp->if_capabilities & IFCAP_POLLING) != 0) {
3047 ifp->if_capenable ^= IFCAP_POLLING;
3048 if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
3049 error = ether_poll_register(xl_poll, ifp);
3050 if (error)
3051 break;
3052 XL_LOCK(sc);
3053 /* Disable interrupts */
3054 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3055 ifp->if_capenable |= IFCAP_POLLING;
3056 XL_UNLOCK(sc);
3057 } else {
3058 error = ether_poll_deregister(ifp);
3059 /* Enable interrupts. */
3060 XL_LOCK(sc);
3061 CSR_WRITE_2(sc, XL_COMMAND,
3062 XL_CMD_INTR_ACK | 0xFF);
3063 CSR_WRITE_2(sc, XL_COMMAND,
3064 XL_CMD_INTR_ENB | XL_INTRS);
3065 if (sc->xl_flags & XL_FLAG_FUNCREG)
3066 bus_space_write_4(sc->xl_ftag,
3067 sc->xl_fhandle, 4, 0x8000);
3068 XL_UNLOCK(sc);
3069 }
3070 }
3071 #endif /* DEVICE_POLLING */
3072 XL_LOCK(sc);
3073 if ((mask & IFCAP_TXCSUM) != 0 &&
3074 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3075 ifp->if_capenable ^= IFCAP_TXCSUM;
3076 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3077 ifp->if_hwassist |= XL905B_CSUM_FEATURES;
3078 else
3079 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES;
3080 }
3081 if ((mask & IFCAP_RXCSUM) != 0 &&
3082 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3083 ifp->if_capenable ^= IFCAP_RXCSUM;
3084 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3085 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3086 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3087 XL_UNLOCK(sc);
3088 break;
3089 default:
3090 error = ether_ioctl(ifp, command, data);
3091 break;
3092 }
3093
3094 return (error);
3095 }
3096
3097 static int
xl_watchdog(struct xl_softc * sc)3098 xl_watchdog(struct xl_softc *sc)
3099 {
3100 struct ifnet *ifp = sc->xl_ifp;
3101 u_int16_t status = 0;
3102 int misintr;
3103
3104 XL_LOCK_ASSERT(sc);
3105
3106 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3107 return (0);
3108
3109 xl_rxeof(sc);
3110 xl_txeoc(sc);
3111 misintr = 0;
3112 if (sc->xl_type == XL_TYPE_905B) {
3113 xl_txeof_90xB(sc);
3114 if (sc->xl_cdata.xl_tx_cnt == 0)
3115 misintr++;
3116 } else {
3117 xl_txeof(sc);
3118 if (sc->xl_cdata.xl_tx_head == NULL)
3119 misintr++;
3120 }
3121 if (misintr != 0) {
3122 device_printf(sc->xl_dev,
3123 "watchdog timeout (missed Tx interrupts) -- recovering\n");
3124 return (0);
3125 }
3126
3127 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3128 XL_SEL_WIN(4);
3129 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3130 device_printf(sc->xl_dev, "watchdog timeout\n");
3131
3132 if (status & XL_MEDIASTAT_CARRIER)
3133 device_printf(sc->xl_dev,
3134 "no carrier - transceiver cable problem?\n");
3135
3136 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3137 xl_init_locked(sc);
3138
3139 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3140 if (sc->xl_type == XL_TYPE_905B)
3141 xl_start_90xB_locked(ifp);
3142 else
3143 xl_start_locked(ifp);
3144 }
3145
3146 return (EJUSTRETURN);
3147 }
3148
3149 /*
3150 * Stop the adapter and free any mbufs allocated to the
3151 * RX and TX lists.
3152 */
3153 static void
xl_stop(struct xl_softc * sc)3154 xl_stop(struct xl_softc *sc)
3155 {
3156 int i;
3157 struct ifnet *ifp = sc->xl_ifp;
3158
3159 XL_LOCK_ASSERT(sc);
3160
3161 sc->xl_wdog_timer = 0;
3162
3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3166 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3167 xl_wait(sc);
3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3170 DELAY(800);
3171
3172 #ifdef foo
3173 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3174 xl_wait(sc);
3175 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3176 xl_wait(sc);
3177 #endif
3178
3179 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3181 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3182 if (sc->xl_flags & XL_FLAG_FUNCREG)
3183 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3184
3185 /* Stop the stats updater. */
3186 callout_stop(&sc->xl_tick_callout);
3187
3188 /*
3189 * Free data in the RX lists.
3190 */
3191 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3192 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3193 bus_dmamap_unload(sc->xl_mtag,
3194 sc->xl_cdata.xl_rx_chain[i].xl_map);
3195 bus_dmamap_destroy(sc->xl_mtag,
3196 sc->xl_cdata.xl_rx_chain[i].xl_map);
3197 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3198 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3199 }
3200 }
3201 if (sc->xl_ldata.xl_rx_list != NULL)
3202 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3203 /*
3204 * Free the TX list buffers.
3205 */
3206 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3207 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3208 bus_dmamap_unload(sc->xl_mtag,
3209 sc->xl_cdata.xl_tx_chain[i].xl_map);
3210 bus_dmamap_destroy(sc->xl_mtag,
3211 sc->xl_cdata.xl_tx_chain[i].xl_map);
3212 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3213 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3214 }
3215 }
3216 if (sc->xl_ldata.xl_tx_list != NULL)
3217 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3218
3219 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3220 }
3221
3222 /*
3223 * Stop all chip I/O so that the kernel's probe routines don't
3224 * get confused by errant DMAs when rebooting.
3225 */
3226 static int
xl_shutdown(device_t dev)3227 xl_shutdown(device_t dev)
3228 {
3229
3230 return (xl_suspend(dev));
3231 }
3232
3233 static int
xl_suspend(device_t dev)3234 xl_suspend(device_t dev)
3235 {
3236 struct xl_softc *sc;
3237
3238 sc = device_get_softc(dev);
3239
3240 XL_LOCK(sc);
3241 xl_stop(sc);
3242 xl_setwol(sc);
3243 XL_UNLOCK(sc);
3244
3245 return (0);
3246 }
3247
3248 static int
xl_resume(device_t dev)3249 xl_resume(device_t dev)
3250 {
3251 struct xl_softc *sc;
3252 struct ifnet *ifp;
3253
3254 sc = device_get_softc(dev);
3255 ifp = sc->xl_ifp;
3256
3257 XL_LOCK(sc);
3258
3259 if (ifp->if_flags & IFF_UP) {
3260 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3261 xl_init_locked(sc);
3262 }
3263
3264 XL_UNLOCK(sc);
3265
3266 return (0);
3267 }
3268
3269 static void
xl_setwol(struct xl_softc * sc)3270 xl_setwol(struct xl_softc *sc)
3271 {
3272 struct ifnet *ifp;
3273 u_int16_t cfg, pmstat;
3274
3275 if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3276 return;
3277
3278 ifp = sc->xl_ifp;
3279 XL_SEL_WIN(7);
3280 /* Clear any pending PME events. */
3281 CSR_READ_2(sc, XL_W7_BM_PME);
3282 cfg = 0;
3283 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3284 cfg |= XL_BM_PME_MAGIC;
3285 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3286 /* Enable RX. */
3287 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3288 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3289 /* Request PME. */
3290 pmstat = pci_read_config(sc->xl_dev,
3291 sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3292 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3293 pmstat |= PCIM_PSTAT_PMEENABLE;
3294 else
3295 pmstat &= ~PCIM_PSTAT_PMEENABLE;
3296 pci_write_config(sc->xl_dev,
3297 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);
3298 }
3299