1 /*- 2 * Copyright(c) 2002-2011 Exar Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification are permitted provided the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Exar Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef VXGE_HAL_MGMT_H 34 #define VXGE_HAL_MGMT_H 35 36 __EXTERN_BEGIN_DECLS 37 38 /* 39 * struct vxge_hal_mgmt_about_info_t - About info. 40 * @vendor: PCI Vendor ID. 41 * @device: PCI Device ID. 42 * @subsys_vendor: PCI Subsystem Vendor ID. 43 * @subsys_device: PCI Subsystem Device ID. 44 * @board_rev: PCI Board revision, e.g. 3 - for Xena 3. 45 * @vendor_name: Exar Corp. 46 * @chip_name: X3100. 47 * @media: Fiber, copper. 48 * @hal_major: HAL major version number. 49 * @hal_minor: HAL minor version number. 50 * @hal_fix: HAL fix number. 51 * @hal_build: HAL build number. 52 * @ll_major: Link-layer ULD major version number. 53 * @ll_minor: Link-layer ULD minor version number. 54 * @ll_fix: Link-layer ULD fix version number. 55 * @ll_build: Link-layer ULD build number. 56 */ 57 typedef struct vxge_hal_mgmt_about_info_t { 58 u16 vendor; 59 u16 device; 60 u16 subsys_vendor; 61 u16 subsys_device; 62 u8 board_rev; 63 char vendor_name[16]; 64 char chip_name[16]; 65 char media[16]; 66 char hal_major[4]; 67 char hal_minor[4]; 68 char hal_fix[4]; 69 char hal_build[16]; 70 char ll_major[4]; 71 char ll_minor[4]; 72 char ll_fix[4]; 73 char ll_build[16]; 74 } vxge_hal_mgmt_about_info_t; 75 76 77 /* 78 * vxge_hal_mgmt_about - Retrieve about info. 79 * @devh: HAL device handle. 80 * @about_info: Filled in by HAL. See vxge_hal_mgmt_about_info_t {}. 81 * @size: Pointer to buffer containing the Size of the @buffer_info. 82 * HAL will return an error if the size is smaller than 83 * sizeof(vxge_hal_mgmt_about_info_t) and returns required size in this field 84 * 85 * Retrieve information such as PCI device and vendor IDs, board 86 * revision number, HAL version number, etc. 87 * 88 * Returns: VXGE_HAL_OK - success; 89 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 90 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not matching. 91 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 92 * VXGE_HAL_FAIL - Failed to retrieve the information. 93 * 94 * See also: vxge_hal_mgmt_about_info_t {}. 95 */ 96 vxge_hal_status_e 97 vxge_hal_mgmt_about(vxge_hal_device_h devh, 98 vxge_hal_mgmt_about_info_t *about_info, 99 u32 *size); 100 101 /* 102 * vxge_hal_mgmt_pci_config - Retrieve PCI configuration. 103 * @devh: HAL device handle. 104 * @buffer: Buffer for PCI configuration space. 105 * @size: Pointer to buffer containing the Size of the @buffer. 106 * HAL will return an error if the size is smaller than 107 * sizeof(vxge_hal_pci_config_t) and returns required size in this field 108 * 109 * Get PCI configuration. Permits to retrieve at run-time configuration 110 * values that were used to configure the device at load-time. 111 * 112 * Returns: VXGE_HAL_OK - success. 113 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 114 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not matching. 115 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 116 * 117 */ 118 vxge_hal_status_e 119 vxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size); 120 121 /* 122 * struct vxge_hal_mgmt_pm_cap_t - Power Management Capabilities 123 * @pm_cap_ver: Version 124 * @pm_cap_pme_clock: PME clock required 125 * @pm_cap_aux_power: Auxiliary power support 126 * @pm_cap_dsi: Device specific initialization 127 * @pm_cap_aux_current: auxiliary current requirements 128 * @pm_cap_cap_d0: D1 power state support 129 * @pm_cap_cap_d1: D2 power state support 130 * @pm_cap_pme_d0: PME# can be asserted from D3hot 131 * @pm_cap_pme_d1: PME# can be asserted from D3hot 132 * @pm_cap_pme_d2: PME# can be asserted from D3hot 133 * @pm_cap_pme_d3_hot: PME# can be asserted from D3hot 134 * @pm_cap_pme_d3_cold: PME# can be asserted from D3cold 135 * @pm_ctrl_state: Current power state (D0 to D3) 136 * @pm_ctrl_no_soft_reset: Devices transitioning from D3hot to D0 137 * @pm_ctrl_pme_enable: PME pin enable 138 * @pm_ctrl_pme_data_sel: Data select 139 * @pm_ctrl_pme_data_scale: Data scale 140 * @pm_ctrl_pme_status: PME pin status 141 * @pm_ppb_ext_b2_b3: Stop clock when in D3hot 142 * @pm_ppb_ext_ecc_en: Bus power/clock control enable 143 * @pm_data_reg: state dependent data requested by pm_ctrl_pme_data_sel 144 * 145 * Power Management Capabilities structure 146 */ 147 typedef struct vxge_hal_mgmt_pm_cap_t { 148 u32 pm_cap_ver; 149 u32 pm_cap_pme_clock; 150 u32 pm_cap_aux_power; 151 u32 pm_cap_dsi; 152 u32 pm_cap_aux_current; 153 u32 pm_cap_cap_d0; 154 u32 pm_cap_cap_d1; 155 u32 pm_cap_pme_d0; 156 u32 pm_cap_pme_d1; 157 u32 pm_cap_pme_d2; 158 u32 pm_cap_pme_d3_hot; 159 u32 pm_cap_pme_d3_cold; 160 u32 pm_ctrl_state; 161 u32 pm_ctrl_no_soft_reset; 162 u32 pm_ctrl_pme_enable; 163 u32 pm_ctrl_pme_data_sel; 164 u32 pm_ctrl_pme_data_scale; 165 u32 pm_ctrl_pme_status; 166 u32 pm_ppb_ext_b2_b3; 167 u32 pm_ppb_ext_ecc_en; 168 u32 pm_data_reg; 169 } vxge_hal_mgmt_pm_cap_t; 170 171 /* 172 * vxge_hal_mgmt_pm_capabilities_get - Returns the pm capabilities 173 * @devh: HAL device handle. 174 * @pm_cap: Power Management Capabilities 175 * 176 * Return the pm capabilities 177 */ 178 vxge_hal_status_e 179 vxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh, 180 vxge_hal_mgmt_pm_cap_t *pm_cap); 181 182 /* 183 * struct vxge_hal_mgmt_sid_cap_t - Slot ID Capabilities 184 * @sid_number_of_slots: Number of solts 185 * @sid_first_in_chasis: First in chasis flag 186 * @sid_chasis_number: Chasis Number 187 * 188 * Slot ID Capabilities structure 189 */ 190 typedef struct vxge_hal_mgmt_sid_cap_t { 191 u32 sid_number_of_slots; 192 u32 sid_first_in_chasis; 193 u32 sid_chasis_number; 194 } vxge_hal_mgmt_sid_cap_t; 195 196 /* 197 * vxge_hal_mgmt_sid_capabilities_get - Returns the sid capabilities 198 * @devh: HAL device handle. 199 * @sid_cap: Slot Id Capabilities 200 * 201 * Return the pm capabilities 202 */ 203 vxge_hal_status_e 204 vxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh, 205 vxge_hal_mgmt_sid_cap_t *sid_cap); 206 207 /* 208 * struct vxge_hal_mgmt_msi_cap_t - MSI Capabilities 209 * @enable: 1 - MSI enabled, 0 - MSI not enabled 210 * @is_pvm_capable: 1 - PVM capable, 0 - Not PVM Capable (valid for get only) 211 * @is_64bit_addr_capable: 1 - 64 bit address capable, 0 - 32 bit address only 212 * (valid for get only) 213 * @vectors_allocated: Number of vectors allocated 214 * 000-1 vectors 215 * 001-2 vectors 216 * 010-4 vectors 217 * 011-8 vectors 218 * 100-16 vectors 219 * 101-32 vectors 220 * @max_vectors_capable: Maximum number of vectors that can be allocated 221 * (valid for get only) 222 * 000-1 vectors 223 * 001-2 vectors 224 * 010-4 vectors 225 * 011-8 vectors 226 * 100-16 vectors 227 * 101-32 vectors 228 * @address: MSI address 229 * @data: MSI Data 230 * @mask_bits: For each Mask bit that is set, the function is prohibited from 231 * sending the associated message 232 * @pending_bits: For each Pending bit that is set, the function has a 233 * pending associated message. 234 * 235 * MSI Capabilities structure 236 */ 237 typedef struct vxge_hal_mgmt_msi_cap_t { 238 u32 enable; 239 u32 is_pvm_capable; 240 u32 is_64bit_addr_capable; 241 u32 vectors_allocated; 242 u32 max_vectors_capable; 243 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_1 0 244 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_2 1 245 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_4 2 246 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_8 3 247 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_16 4 248 #define VXGE_HAL_MGMT_MSI_CAP_VECTORS_32 5 249 u64 address; 250 u16 data; 251 u32 mask_bits; 252 u32 pending_bits; 253 } vxge_hal_mgmt_msi_cap_t; 254 255 /* 256 * vxge_hal_mgmt_msi_capabilities_get - Returns the msi capabilities 257 * @devh: HAL device handle. 258 * @msi_cap: MSI Capabilities 259 * 260 * Return the msi capabilities 261 */ 262 vxge_hal_status_e 263 vxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh, 264 vxge_hal_mgmt_msi_cap_t *msi_cap); 265 266 /* 267 * vxge_hal_mgmt_msi_capabilities_set - Sets the msi capabilities 268 * @devh: HAL device handle. 269 * @msi_cap: MSI Capabilities 270 * 271 * Sets the msi capabilities 272 */ 273 vxge_hal_status_e 274 vxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh, 275 vxge_hal_mgmt_msi_cap_t *msi_cap); 276 277 /* 278 * struct vxge_hal_mgmt_msix_cap_t - MSIX Capabilities 279 * @enable: 1 - MSIX enabled, 0 - MSIX not enabled 280 * @mask_all_vect: 1 - Mask all vectors, 0 - Do not mask all vectors 281 * @table_size: MSIX Table Size-1 282 * @table_offset: Offset of the table from the table_bir 283 * @table_bir: Table Bar address register number 0-BAR0, 2-BAR1, 4-BAR2 284 * @pba_offset: Offset of the PBA from the pba_bir 285 * @pba_bir: PBA Bar address register number 0-BAR0, 2-BAR1, 4-BAR2 286 * 287 * MSIS Capabilities structure 288 */ 289 typedef struct vxge_hal_mgmt_msix_cap_t { 290 u32 enable; 291 u32 mask_all_vect; 292 u32 table_size; 293 u32 table_offset; 294 u32 table_bir; 295 #define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR0 0 296 #define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR1 2 297 #define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR2 4 298 u32 pba_offset; 299 u32 pba_bir; 300 #define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR0 0 301 #define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR1 2 302 #define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR2 4 303 } vxge_hal_mgmt_msix_cap_t; 304 305 /* 306 * vxge_hal_mgmt_msix_capabilities_get - Returns the msix capabilities 307 * @devh: HAL device handle. 308 * @msix_cap: MSIX Capabilities 309 * 310 * Return the msix capabilities 311 */ 312 vxge_hal_status_e 313 vxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh, 314 vxge_hal_mgmt_msix_cap_t *msix_cap); 315 316 /* 317 * struct vxge_hal_pci_err_cap_t - PCI Error Capabilities 318 * @pci_err_header: Error header 319 * @pci_err_uncor_status: Uncorrectable error status 320 * 0x00000001 - Training 321 * 0x00000010 - Data Link Protocol 322 * 0x00001000 - Poisoned TLP 323 * 0x00002000 - Flow Control Protocol 324 * 0x00004000 - Completion Timeout 325 * 0x00008000 - Completer Abort 326 * 0x00010000 - Unexpected Completion 327 * 0x00020000 - Receiver Overflow 328 * 0x00040000 - Malformed TLP 329 * 0x00080000 - ECRC Error Status 330 * 0x00100000 - Unsupported Request 331 * @pci_err_uncor_mask: Uncorrectable mask 332 * @pci_err_uncor_server: Uncorrectable server 333 * @pci_err_cor_status: Correctable status 334 * 0x00000001 - Receiver Error Status 335 * 0x00000040 - Bad TLP Status 336 * 0x00000080 - Bad DLLP Status 337 * 0x00000100 - REPLAY_NUM Rollover 338 * 0x00001000 - Replay Timer Timeout 339 * VXGE_HAL_PCI_ERR_COR_MASK 20 340 * @pci_err_cap: Error capability 341 * 0x00000020 - ECRC Generation Capable 342 * 0x00000040 - ECRC Generation Enable 343 * 0x00000080 - ECRC Check Capable 344 * 0x00000100 - ECRC Check Enable 345 * @err_header_log: Error header log 346 * @unused: Reserved 347 * @pci_err_root_command: Error root command 348 * @pci_err_root_status: Error root status 349 * @pci_err_root_cor_src: Error root correctible source 350 * @pci_err_root_src: Error root source 351 * 352 * MSIS Capabilities structure 353 */ 354 typedef struct vxge_hal_pci_err_cap_t { 355 u32 pci_err_header; 356 u32 pci_err_uncor_status; 357 #define VXGE_HAL_PCI_ERR_CAP_UNC_TRAIN 0x00000001 /* Training */ 358 #define VXGE_HAL_PCI_ERR_CAP_UNC_DLP 0x00000010 /* Data Link Protocol */ 359 #define VXGE_HAL_PCI_ERR_CAP_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 360 #define VXGE_HAL_PCI_ERR_CAP_UNC_FCP 0x00002000 /* Flow Ctrl Protocol */ 361 #define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 362 #define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 363 #define VXGE_HAL_PCI_ERR_CAP_UNC_UNX_COMP 0x00010000 /* Unexpected Compl */ 364 #define VXGE_HAL_PCI_ERR_CAP_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 365 #define VXGE_HAL_PCI_ERR_CAP_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 366 #define VXGE_HAL_PCI_ERR_CAP_UNC_ECRC 0x00080000 /* ECRC Error Status */ 367 #define VXGE_HAL_PCI_ERR_CAP_UNC_UNSUP 0x00100000 /* Unsupported Request */ 368 u32 pci_err_uncor_mask; 369 u32 pci_err_uncor_server; 370 u32 pci_err_cor_status; 371 #define VXGE_HAL_PCI_ERR_CAP_COR_RCVR 0x00000001 /* Recv Err Status */ 372 #define VXGE_HAL_PCI_ERR_CAP_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 373 #define VXGE_HAL_PCI_ERR_CAP_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 374 #define VXGE_HAL_PCI_ERR_CAP_COR_REP_ROLL 0x00000100 /* REPLAY Rollover */ 375 #define VXGE_HAL_PCI_ERR_CAP_COR_REP_TIMER 0x00001000 /* Replay Timeout */ 376 #define VXGE_HAL_PCI_ERR_CAP_COR_MASK 20 /* Corrble Err Mask */ 377 u32 pci_err_cap; 378 #define VXGE_HAL_PCI_ERR_CAP_CAP_FEP(x) ((x) & 31) /* First Err Ptr */ 379 #define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENC 0x00000020 /* ECRC Gen Capable */ 380 #define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENE 0x00000040 /* ECRC Gen Enable */ 381 #define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKC 0x00000080 /* ECRC Chk Capable */ 382 #define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKE 0x00000100 /* ECRC Chk Enable */ 383 u32 err_header_log; 384 #define VXGE_HAL_PCI_ERR_CAP_HEADER_LOG(x) ((x) >> 31) /* Error Hdr Log */ 385 u32 unused[3]; 386 u32 pci_err_root_command; 387 u32 pci_err_root_status; 388 u32 pci_err_root_cor_src; 389 u32 pci_err_root_src; 390 } vxge_hal_pci_err_cap_t; 391 392 /* 393 * vxge_hal_mgmt_pci_err_capabilities_get - Returns the pci error capabilities 394 * @devh: HAL device handle. 395 * @err_cap: PCI-E Extended Error Capabilities 396 * 397 * Return the PCI-E Extended Error capabilities 398 */ 399 vxge_hal_status_e 400 vxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh, 401 vxge_hal_pci_err_cap_t *err_cap); 402 403 /* 404 * vxge_hal_mgmt_driver_config - Retrieve driver configuration. 405 * @drv_config: Device configuration, see vxge_hal_driver_config_t {}. 406 * @size: Pointer to buffer containing the Size of the @drv_config. 407 * HAL will return an error if the size is smaller than 408 * sizeof(vxge_hal_driver_config_t) and returns required size in this field 409 * 410 * Get driver configuration. Permits to retrieve at run-time configuration 411 * values that were used to configure the device at load-time. 412 * 413 * Returns: VXGE_HAL_OK - success. 414 * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized. 415 * VXGE_HAL_ERR_VERSION_CONFLICT - Version is not matching. 416 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 417 * 418 * See also: vxge_hal_driver_config_t {}, vxge_hal_mgmt_device_config(). 419 */ 420 vxge_hal_status_e 421 vxge_hal_mgmt_driver_config(vxge_hal_driver_config_t *drv_config, u32 *size); 422 423 #if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 424 425 /* 426 * vxge_hal_mgmt_trace_read - Read trace buffer contents. 427 * @buffer: Buffer to store the trace buffer contents. 428 * @buf_size: Size of the buffer. 429 * @offset: Offset in the internal trace buffer to read data. 430 * @read_length: Size of the valid data in the buffer. 431 * 432 * Read HAL trace buffer contents starting from the offset 433 * up to the size of the buffer or till EOF is reached. 434 * 435 * Returns: VXGE_HAL_OK - success. 436 * VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer. 437 * 438 */ 439 vxge_hal_status_e 440 vxge_hal_mgmt_trace_read(char *buffer, 441 unsigned buf_size, 442 unsigned *offset, 443 unsigned *read_length); 444 445 #endif 446 447 /* 448 * vxge_hal_mgmt_device_config - Retrieve device configuration. 449 * @devh: HAL device handle. 450 * @dev_config: Device configuration, see vxge_hal_device_config_t {}. 451 * @size: Pointer to buffer containing the Size of the @dev_config. 452 * HAL will return an error if the size is smaller than 453 * sizeof(vxge_hal_device_config_t) and returns required size in this field 454 * 455 * Get device configuration. Permits to retrieve at run-time configuration 456 * values that were used to initialize and configure the device. 457 * 458 * Returns: VXGE_HAL_OK - success. 459 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 460 * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not matching. 461 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 462 * 463 * See also: vxge_hal_device_config_t {}, vxge_hal_mgmt_driver_config(). 464 */ 465 vxge_hal_status_e 466 vxge_hal_mgmt_device_config(vxge_hal_device_h devh, 467 vxge_hal_device_config_t *dev_config, u32 *size); 468 469 470 /* 471 * vxge_hal_mgmt_pcireg_read - Read PCI configuration at a specified 472 * offset. 473 * @devh: HAL device handle. 474 * @offset: Offset in the 256 byte PCI configuration space. 475 * @value_bits: 8, 16, or 32 (bits) to read. 476 * @value: Value returned by HAL. 477 * 478 * Read PCI configuration, given device and offset in the PCI space. 479 * 480 * Returns: VXGE_HAL_OK - success. 481 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 482 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not 483 * valid. 484 * VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid 485 * values(8/16/32). 486 * 487 */ 488 vxge_hal_status_e 489 vxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset, 490 int value_bits, u32 *value); 491 492 /* 493 * enum vxge_hal_mgmt_reg_type_e - Register types. 494 * 495 * @vxge_hal_mgmt_reg_type_legacy: Legacy registers 496 * @vxge_hal_mgmt_reg_type_toc: TOC Registers 497 * @vxge_hal_mgmt_reg_type_common: Common Registers 498 * @vxge_hal_mgmt_reg_type_memrepair: Memrepair Registers 499 * @vxge_hal_mgmt_reg_type_pcicfgmgmt: pci cfg management registers 500 * @vxge_hal_mgmt_reg_type_mrpcim: mrpcim registers 501 * @vxge_hal_mgmt_reg_type_srpcim: srpcim registers 502 * @vxge_hal_mgmt_reg_type_vpmgmt: vpath management registers 503 * @vxge_hal_mgmt_reg_type_vpath: vpath registers 504 * 505 * Register type enumaration 506 */ 507 typedef enum vxge_hal_mgmt_reg_type_e { 508 vxge_hal_mgmt_reg_type_legacy = 0, 509 vxge_hal_mgmt_reg_type_toc = 1, 510 vxge_hal_mgmt_reg_type_common = 2, 511 vxge_hal_mgmt_reg_type_memrepair = 3, 512 vxge_hal_mgmt_reg_type_pcicfgmgmt = 4, 513 vxge_hal_mgmt_reg_type_mrpcim = 5, 514 vxge_hal_mgmt_reg_type_srpcim = 6, 515 vxge_hal_mgmt_reg_type_vpmgmt = 7, 516 vxge_hal_mgmt_reg_type_vpath = 8 517 } vxge_hal_mgmt_reg_type_e; 518 519 /* 520 * vxge_hal_mgmt_reg_read - Read X3100 register. 521 * @devh: HAL device handle. 522 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {} 523 * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index 524 * ignored for others 525 * @offset: Register offset in the register space qualified by the type and 526 * index. 527 * @value: Register value. Returned by HAL. 528 * Read X3100 register. 529 * 530 * Returns: VXGE_HAL_OK - success. 531 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 532 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid. 533 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid. 534 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 535 * 536 */ 537 vxge_hal_status_e 538 vxge_hal_mgmt_reg_read(vxge_hal_device_h devh, 539 vxge_hal_mgmt_reg_type_e type, 540 u32 index, 541 u32 offset, 542 u64 *value); 543 544 /* 545 * vxge_hal_mgmt_reg_Write - Write X3100 register. 546 * @devh: HAL device handle. 547 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {} 548 * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index 549 * ignored for others 550 * @offset: Register offset in the register space qualified by the type and 551 * index. 552 * @value: Register value to be written. 553 * Write X3100 register. 554 * 555 * Returns: VXGE_HAL_OK - success. 556 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 557 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid. 558 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid. 559 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 560 * 561 */ 562 vxge_hal_status_e 563 vxge_hal_mgmt_reg_write(vxge_hal_device_h devh, 564 vxge_hal_mgmt_reg_type_e type, 565 u32 index, 566 u32 offset, 567 u64 value); 568 569 /* 570 * vxge_hal_mgmt_bar0_read - Read X3100 register located at the offset 571 * from bar0. 572 * @devh: HAL device handle. 573 * @offset: Register offset from bar0 574 * @value: Register value. Returned by HAL. 575 * Read X3100 register. 576 * 577 * Returns: VXGE_HAL_OK - success. 578 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 579 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 580 * 581 */ 582 vxge_hal_status_e 583 vxge_hal_mgmt_bar0_read(vxge_hal_device_h devh, 584 u32 offset, 585 u64 *value); 586 587 /* 588 * vxge_hal_mgmt_bar1_read - Read X3100 register located at the offset 589 * from bar1. 590 * @devh: HAL device handle. 591 * @offset: Register offset from bar1 592 * @value: Register value. Returned by HAL. 593 * Read X3100 register. 594 * 595 * Returns: VXGE_HAL_OK - success. 596 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 597 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 598 * 599 */ 600 vxge_hal_status_e 601 vxge_hal_mgmt_bar1_read(vxge_hal_device_h devh, 602 u32 offset, 603 u64 *value); 604 605 /* 606 * vxge_hal_mgmt_bar0_Write - Write X3100 register located at the offset 607 * from bar0. 608 * @devh: HAL device handle. 609 * @offset: Register offset from bar0 610 * @value: Register value to be written. 611 * Write X3100 register. 612 * 613 * Returns: VXGE_HAL_OK - success. 614 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 615 * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid. 616 * 617 */ 618 vxge_hal_status_e 619 vxge_hal_mgmt_bar0_write(vxge_hal_device_h devh, 620 u32 offset, 621 u64 value); 622 623 /* 624 * vxge_hal_mgmt_register_config - Retrieve register configuration. 625 * @devh: HAL device handle. 626 * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {} 627 * @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index 628 * ignored for others 629 * @config: Device configuration, see vxge_hal_device_config_t {}. 630 * @size: Pointer to buffer containing the Size of the @reg_config. 631 * HAL will return an error if the size is smaller than 632 * requested register space and returns required size in this field 633 * 634 * Get register configuration. Permits to retrieve register values. 635 * 636 * Returns: VXGE_HAL_OK - success. 637 * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 638 * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid. 639 * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid. 640 * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient 641 * 642 */ 643 vxge_hal_status_e 644 vxge_hal_mgmt_register_config(vxge_hal_device_h devh, 645 vxge_hal_mgmt_reg_type_e type, 646 u32 vp_id, 647 u8 *config, 648 u32 *size); 649 650 /* 651 * vxge_hal_mgmt_read_xfp_current_temp - Read current temparature of given port 652 * @devh: HAL device handle. 653 * @port: Port number 654 * 655 * This routine only gets the temperature for XFP modules. Also, updating of the 656 * NVRAM can sometimes fail and so the reading we might get may not be uptodate. 657 */ 658 u32 vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port); 659 660 /* 661 * vxge_hal_mgmt_pma_loopback - Enable or disable PMA loopback 662 * @devh: HAL device handle. 663 * @port: Port number 664 * @enable:Boolean set to 1 to enable and 0 to disable. 665 * 666 * Enable or disable PMA loopback. 667 * Return value: 668 * 0 on success. 669 */ 670 vxge_hal_status_e 671 vxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable); 672 673 /* 674 * vxge_hal_mgmt_xgmii_loopback - Enable or disable xgmii loopback 675 * @devh: HAL device handle. 676 * @port: Port number 677 * @enable:Boolean set to 1 to enable and 0 to disable. 678 * 679 * Enable or disable xgmii loopback. 680 * Return value: 681 * 0 on success. 682 */ 683 vxge_hal_status_e 684 vxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable); 685 686 __EXTERN_END_DECLS 687 688 #endif /* VXGE_HAL_MGMT_H */ 689