1 /*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ 17 * $FreeBSD$ 18 */ 19 20 #define URTWN_CONFIG_INDEX 0 21 #define URTWN_IFACE_INDEX 0 22 23 #define URTWN_NOISE_FLOOR -95 24 25 #define R92C_MAX_CHAINS 2 26 27 /* Maximum number of output pipes is 3. */ 28 #define R92C_MAX_EPOUT 3 29 30 #define R92C_MAX_TX_PWR 0x3f 31 32 #define R92C_PUBQ_NPAGES 231 33 #define R92C_TXPKTBUF_COUNT 256 34 #define R92C_TX_PAGE_COUNT 248 35 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 36 #define R88E_TXPKTBUF_COUNT 177 37 #define R88E_TX_PAGE_COUNT 169 38 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 39 40 #define R92C_H2C_NBOX 4 41 42 /* USB Requests. */ 43 #define R92C_REQ_REGS 0x05 44 45 /* 46 * MAC registers. 47 */ 48 /* System Configuration. */ 49 #define R92C_SYS_ISO_CTRL 0x000 50 #define R92C_SYS_FUNC_EN 0x002 51 #define R92C_APS_FSMCO 0x004 52 #define R92C_SYS_CLKR 0x008 53 #define R92C_AFE_MISC 0x010 54 #define R92C_SPS0_CTRL 0x011 55 #define R92C_SPS_OCP_CFG 0x018 56 #define R92C_RSV_CTRL 0x01c 57 #define R92C_RF_CTRL 0x01f 58 #define R92C_LDOA15_CTRL 0x020 59 #define R92C_LDOV12D_CTRL 0x021 60 #define R92C_LDOHCI12_CTRL 0x022 61 #define R92C_LPLDO_CTRL 0x023 62 #define R92C_AFE_XTAL_CTRL 0x024 63 #define R92C_AFE_PLL_CTRL 0x028 64 #define R92C_EFUSE_CTRL 0x030 65 #define R92C_EFUSE_TEST 0x034 66 #define R92C_PWR_DATA 0x038 67 #define R92C_CAL_TIMER 0x03c 68 #define R92C_ACLK_MON 0x03e 69 #define R92C_GPIO_MUXCFG 0x040 70 #define R92C_GPIO_IO_SEL 0x042 71 #define R92C_MAC_PINMUX_CFG 0x043 72 #define R92C_GPIO_PIN_CTRL 0x044 73 #define R92C_GPIO_IN 0x044 74 #define R92C_GPIO_OUT 0x045 75 #define R92C_GPIO_IOSEL 0x046 76 #define R92C_GPIO_MOD 0x047 77 #define R92C_GPIO_INTM 0x048 78 #define R92C_LEDCFG0 0x04c 79 #define R92C_LEDCFG1 0x04d 80 #define R92C_LEDCFG2 0x04e 81 #define R92C_LEDCFG3 0x04f 82 #define R92C_FSIMR 0x050 83 #define R92C_FSISR 0x054 84 #define R92C_HSIMR 0x058 85 #define R92C_HSISR 0x05c 86 #define R88E_BB_PAD_CTRL 0x064 87 #define R92C_MCUFWDL 0x080 88 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 89 #define R88E_HIMR 0x0b0 90 #define R88E_HISR 0x0b4 91 #define R88E_HIMRE 0x0b8 92 #define R88E_HISRE 0x0bc 93 #define R92C_EFUSE_ACCESS 0x0cf 94 #define R92C_BIST_SCAN 0x0d0 95 #define R92C_BIST_RPT 0x0d4 96 #define R92C_BIST_ROM_RPT 0x0d8 97 #define R92C_USB_SIE_INTF 0x0e0 98 #define R92C_PCIE_MIO_INTF 0x0e4 99 #define R92C_PCIE_MIO_INTD 0x0e8 100 #define R92C_HPON_FSM 0x0ec 101 #define R92C_SYS_CFG 0x0f0 102 /* MAC General Configuration. */ 103 #define R92C_CR 0x100 104 #define R92C_MSR 0x102 105 #define R92C_PBP 0x104 106 #define R92C_TRXDMA_CTRL 0x10c 107 #define R92C_TRXFF_BNDY 0x114 108 #define R92C_TRXFF_STATUS 0x118 109 #define R92C_RXFF_PTR 0x11c 110 #define R92C_HIMR 0x120 111 #define R92C_HISR 0x124 112 #define R92C_HIMRE 0x128 113 #define R92C_HISRE 0x12c 114 #define R92C_CPWM 0x12f 115 #define R92C_FWIMR 0x130 116 #define R92C_FWISR 0x134 117 #define R92C_PKTBUF_DBG_CTRL 0x140 118 #define R92C_PKTBUF_DBG_DATA_L 0x144 119 #define R92C_PKTBUF_DBG_DATA_H 0x148 120 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 121 #define R92C_TCUNIT_BASE 0x164 122 #define R92C_MBIST_START 0x174 123 #define R92C_MBIST_DONE 0x178 124 #define R92C_MBIST_FAIL 0x17c 125 #define R88E_32K_CTRL 0x194 126 #define R92C_C2HEVT_MSG_NORMAL 0x1a0 127 #define R92C_C2HEVT_MSG_TEST 0x1b8 128 #define R92C_C2HEVT_CLEAR 0x1bf 129 #define R92C_MCUTST_1 0x1c0 130 #define R92C_FMETHR 0x1c8 131 #define R92C_HMETFR 0x1cc 132 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 133 #define R92C_LLT_INIT 0x1e0 134 #define R92C_BB_ACCESS_CTRL 0x1e8 135 #define R92C_BB_ACCESS_DATA 0x1ec 136 #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 137 /* Tx DMA Configuration. */ 138 #define R92C_RQPN 0x200 139 #define R92C_FIFOPAGE 0x204 140 #define R92C_TDECTRL 0x208 141 #define R92C_TXDMA_OFFSET_CHK 0x20c 142 #define R92C_TXDMA_STATUS 0x210 143 #define R92C_RQPN_NPQ 0x214 144 /* Rx DMA Configuration. */ 145 #define R92C_RXDMA_AGG_PG_TH 0x280 146 #define R92C_RXPKT_NUM 0x284 147 #define R92C_RXDMA_STATUS 0x288 148 /* Protocol Configuration. */ 149 #define R92C_FWHW_TXQ_CTRL 0x420 150 #define R92C_HWSEQ_CTRL 0x423 151 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 152 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 153 #define R92C_SPEC_SIFS 0x428 154 #define R92C_RL 0x42a 155 #define R92C_DARFRC 0x430 156 #define R92C_RARFRC 0x438 157 #define R92C_RRSR 0x440 158 #define R92C_ARFR(i) (0x444 + (i) * 4) 159 #define R92C_AGGLEN_LMT 0x458 160 #define R92C_AMPDU_MIN_SPACE 0x45c 161 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 162 #define R92C_FAST_EDCA_CTRL 0x460 163 #define R92C_RD_RESP_PKT_TH 0x463 164 #define R92C_INIRTS_RATE_SEL 0x480 165 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 166 #define R92C_POWER_STATUS 0x4a4 167 #define R92C_MAX_AGGR_NUM 0x4ca 168 #define R88E_TX_RPT_CTRL 0x4ec 169 #define R88E_TX_RPT_MACID_MAX 0x4ed 170 #define R88E_TX_RPT_TIME 0x4f0 171 /* EDCA Configuration. */ 172 #define R92C_EDCA_VO_PARAM 0x500 173 #define R92C_EDCA_VI_PARAM 0x504 174 #define R92C_EDCA_BE_PARAM 0x508 175 #define R92C_EDCA_BK_PARAM 0x50c 176 #define R92C_BCNTCFG 0x510 177 #define R92C_PIFS 0x512 178 #define R92C_RDG_PIFS 0x513 179 #define R92C_SIFS_CCK 0x514 180 #define R92C_SIFS_OFDM 0x516 181 #define R92C_AGGR_BREAK_TIME 0x51a 182 #define R92C_SLOT 0x51b 183 #define R92C_TX_PTCL_CTRL 0x520 184 #define R92C_TXPAUSE 0x522 185 #define R92C_DIS_TXREQ_CLR 0x523 186 #define R92C_RD_CTRL 0x524 187 #define R92C_TBTT_PROHIBIT 0x540 188 #define R92C_RD_NAV_NXT 0x544 189 #define R92C_NAV_PROT_LEN 0x546 190 #define R92C_BCN_CTRL 0x550 191 #define R92C_MBID_NUM 0x552 192 #define R92C_DUAL_TSF_RST 0x553 193 #define R92C_BCN_INTERVAL 0x554 194 #define R92C_DRVERLYINT 0x558 195 #define R92C_BCNDMATIM 0x559 196 #define R92C_ATIMWND 0x55a 197 #define R92C_USTIME_TSF 0x55c 198 #define R92C_BCN_MAX_ERR 0x55d 199 #define R92C_RXTSF_OFFSET_CCK 0x55e 200 #define R92C_RXTSF_OFFSET_OFDM 0x55f 201 #define R92C_TSFTR 0x560 202 #define R92C_INIT_TSFTR 0x564 203 #define R92C_PSTIMER 0x580 204 #define R92C_TIMER0 0x584 205 #define R92C_TIMER1 0x588 206 #define R92C_ACMHWCTRL 0x5c0 207 #define R92C_ACMRSTCTRL 0x5c1 208 #define R92C_ACMAVG 0x5c2 209 #define R92C_VO_ADMTIME 0x5c4 210 #define R92C_VI_ADMTIME 0x5c6 211 #define R92C_BE_ADMTIME 0x5c8 212 #define R92C_EDCA_RANDOM_GEN 0x5cc 213 #define R92C_SCH_TXCMD 0x5d0 214 #define R88E_SCH_TXCMD 0x5f8 215 /* WMAC Configuration. */ 216 #define R92C_APSD_CTRL 0x600 217 #define R92C_BWOPMODE 0x603 218 #define R92C_RCR 0x608 219 #define R92C_RX_DRVINFO_SZ 0x60f 220 #define R92C_MACID 0x610 221 #define R92C_BSSID 0x618 222 #define R92C_MAR 0x620 223 #define R92C_MAC_SPEC_SIFS 0x63a 224 #define R92C_R2T_SIFS 0x63c 225 #define R92C_T2T_SIFS 0x63e 226 #define R92C_ACKTO 0x640 227 #define R92C_CAMCMD 0x670 228 #define R92C_CAMWRITE 0x674 229 #define R92C_CAMREAD 0x678 230 #define R92C_CAMDBG 0x67c 231 #define R92C_SECCFG 0x680 232 #define R92C_RXFLTMAP0 0x6a0 233 #define R92C_RXFLTMAP1 0x6a2 234 #define R92C_RXFLTMAP2 0x6a4 235 236 /* Bits for R92C_SYS_ISO_CTRL. */ 237 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 238 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 239 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 240 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 241 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 242 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 243 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 244 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 245 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 246 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 247 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 248 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 249 250 /* Bits for R92C_SYS_FUNC_EN. */ 251 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 252 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 253 #define R92C_SYS_FUNC_EN_USBA 0x0004 254 #define R92C_SYS_FUNC_EN_UPLL 0x0008 255 #define R92C_SYS_FUNC_EN_USBD 0x0010 256 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 257 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 258 #define R92C_SYS_FUNC_EN_PPLL 0x0080 259 #define R92C_SYS_FUNC_EN_PCIED 0x0100 260 #define R92C_SYS_FUNC_EN_DIOE 0x0200 261 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 262 #define R92C_SYS_FUNC_EN_DCORE 0x0800 263 #define R92C_SYS_FUNC_EN_ELDR 0x1000 264 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 265 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 266 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 267 268 /* Bits for R92C_APS_FSMCO. */ 269 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 270 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 271 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 272 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 273 #define R92C_APS_FSMCO_PDN_EN 0x00000010 274 #define R92C_APS_FSMCO_PDN_PL 0x00000020 275 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 276 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 277 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 278 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 279 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 280 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 281 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 282 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 283 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 284 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 285 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 286 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 287 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 288 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 289 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 290 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 291 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 292 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 293 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 294 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 295 296 /* Bits for R92C_SYS_CLKR. */ 297 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 298 #define R92C_SYS_CLKR_ANA8M 0x00000002 299 #define R92C_SYS_CLKR_MACSLP 0x00000010 300 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 301 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 302 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 303 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 304 #define R92C_SYS_CLKR_SEC_EN 0x00000400 305 #define R92C_SYS_CLKR_MAC_EN 0x00000800 306 #define R92C_SYS_CLKR_SYS_EN 0x00001000 307 #define R92C_SYS_CLKR_RING_EN 0x00002000 308 309 /* Bits for R92C_RF_CTRL. */ 310 #define R92C_RF_CTRL_EN 0x01 311 #define R92C_RF_CTRL_RSTB 0x02 312 #define R92C_RF_CTRL_SDMRSTB 0x04 313 314 /* Bits for R92C_LDOA15_CTRL. */ 315 #define R92C_LDOA15_CTRL_EN 0x01 316 #define R92C_LDOA15_CTRL_STBY 0x02 317 #define R92C_LDOA15_CTRL_OBUF 0x04 318 #define R92C_LDOA15_CTRL_REG_VOS 0x08 319 320 /* Bits for R92C_LDOV12D_CTRL. */ 321 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 322 323 /* Bits for R92C_LPLDO_CTRL. */ 324 #define R92C_LPLDO_CTRL_SLEEP 0x10 325 326 /* Bits for R92C_AFE_XTAL_CTRL. */ 327 #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 328 #define R92C_AFE_XTAL_CTRL_ADDR_S 11 329 330 /* Bits for R92C_AFE_PLL_CTRL. */ 331 #define R92C_AFE_PLL_CTRL_EN 0x0001 332 #define R92C_AFE_PLL_CTRL_320_EN 0x0002 333 #define R92C_AFE_PLL_CTRL_FREF_SEL 0x0004 334 #define R92C_AFE_PLL_CTRL_EDGE_SEL 0x0008 335 #define R92C_AFE_PLL_CTRL_WDOGB 0x0010 336 #define R92C_AFE_PLL_CTRL_LPFEN 0x0020 337 338 /* Bits for R92C_EFUSE_CTRL. */ 339 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 340 #define R92C_EFUSE_CTRL_DATA_S 0 341 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 342 #define R92C_EFUSE_CTRL_ADDR_S 8 343 #define R92C_EFUSE_CTRL_VALID 0x80000000 344 345 /* Bits for R92C_GPIO_MUXCFG. */ 346 #define R92C_GPIO_MUXCFG_ENBT 0x0020 347 348 /* Bits for R92C_LEDCFG0. */ 349 #define R92C_LEDCFG0_DIS 0x08 350 351 /* Bits for R92C_MCUFWDL. */ 352 #define R92C_MCUFWDL_EN 0x00000001 353 #define R92C_MCUFWDL_RDY 0x00000002 354 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 355 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 356 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 357 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 358 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 359 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 360 #define R92C_MCUFWDL_PAGE_M 0x00070000 361 #define R92C_MCUFWDL_PAGE_S 16 362 #define R92C_MCUFWDL_CPRST 0x00800000 363 364 /* Bits for R88E_HIMR. */ 365 #define R88E_HIMR_CPWM 0x00000100 366 #define R88E_HIMR_CPWM2 0x00000200 367 #define R88E_HIMR_TBDER 0x04000000 368 #define R88E_HIMR_PSTIMEOUT 0x20000000 369 370 /* Bits for R88E_HIMRE.*/ 371 #define R88E_HIMRE_RXFOVW 0x00000100 372 #define R88E_HIMRE_TXFOVW 0x00000200 373 #define R88E_HIMRE_RXERR 0x00000400 374 #define R88E_HIMRE_TXERR 0x00000800 375 376 /* Bits for R92C_EFUSE_ACCESS. */ 377 #define R92C_EFUSE_ACCESS_OFF 0x00 378 #define R92C_EFUSE_ACCESS_ON 0x69 379 380 /* Bits for R92C_HPON_FSM. */ 381 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 382 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 383 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 384 385 /* Bits for R92C_SYS_CFG. */ 386 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 387 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 388 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 389 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 390 #define R92C_SYS_CFG_PCIRSTB 0x00000010 391 #define R92C_SYS_CFG_V15_VLD 0x00000020 392 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 393 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 394 #define R92C_SYS_CFG_BD_MAC2 0x00000200 395 #define R92C_SYS_CFG_BD_MAC1 0x00000400 396 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 397 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 398 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 399 #define R92C_SYS_CFG_BT_FUNC 0x00010000 400 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 401 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 402 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 403 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 404 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 405 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 406 #define R92C_SYS_CFG_TYPE_92C 0x08000000 407 408 /* Bits for R92C_CR. */ 409 #define R92C_CR_HCI_TXDMA_EN 0x0001 410 #define R92C_CR_HCI_RXDMA_EN 0x0002 411 #define R92C_CR_TXDMA_EN 0x0004 412 #define R92C_CR_RXDMA_EN 0x0008 413 #define R92C_CR_PROTOCOL_EN 0x0010 414 #define R92C_CR_SCHEDULE_EN 0x0020 415 #define R92C_CR_MACTXEN 0x0040 416 #define R92C_CR_MACRXEN 0x0080 417 #define R92C_CR_ENSEC 0x0200 418 #define R92C_CR_CALTMR_EN 0x0400 419 420 /* Bits for R92C_MSR. */ 421 #define R92C_MSR_NOLINK 0x00 422 #define R92C_MSR_ADHOC 0x01 423 #define R92C_MSR_INFRA 0x02 424 #define R92C_MSR_AP 0x03 425 #define R92C_MSR_MASK (R92C_MSR_AP) 426 427 /* Bits for R92C_PBP. */ 428 #define R92C_PBP_PSRX_M 0x0f 429 #define R92C_PBP_PSRX_S 0 430 #define R92C_PBP_PSTX_M 0xf0 431 #define R92C_PBP_PSTX_S 4 432 #define R92C_PBP_64 0 433 #define R92C_PBP_128 1 434 #define R92C_PBP_256 2 435 #define R92C_PBP_512 3 436 #define R92C_PBP_1024 4 437 438 /* Bits for R92C_TRXDMA_CTRL. */ 439 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 440 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 441 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 442 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 443 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 444 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 445 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 446 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 447 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 448 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 449 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 450 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 451 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 452 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 453 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 454 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 455 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 456 /* Shortcuts. */ 457 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 458 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 459 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 460 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 461 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 462 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 463 464 /* Bits for R92C_LLT_INIT. */ 465 #define R92C_LLT_INIT_DATA_M 0x000000ff 466 #define R92C_LLT_INIT_DATA_S 0 467 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 468 #define R92C_LLT_INIT_ADDR_S 8 469 #define R92C_LLT_INIT_OP_M 0xc0000000 470 #define R92C_LLT_INIT_OP_S 30 471 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 472 #define R92C_LLT_INIT_OP_WRITE 1 473 474 /* Bits for R92C_RQPN. */ 475 #define R92C_RQPN_HPQ_M 0x000000ff 476 #define R92C_RQPN_HPQ_S 0 477 #define R92C_RQPN_LPQ_M 0x0000ff00 478 #define R92C_RQPN_LPQ_S 8 479 #define R92C_RQPN_PUBQ_M 0x00ff0000 480 #define R92C_RQPN_PUBQ_S 16 481 #define R92C_RQPN_LD 0x80000000 482 483 /* Bits for R92C_TDECTRL. */ 484 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0 485 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 486 #define R92C_TDECTRL_BCN_VALID 0x00010000 487 488 /* Bits for R92C_FWHW_TXQ_CTRL. */ 489 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 490 491 /* Bits for R92C_SPEC_SIFS. */ 492 #define R92C_SPEC_SIFS_CCK_M 0x00ff 493 #define R92C_SPEC_SIFS_CCK_S 0 494 #define R92C_SPEC_SIFS_OFDM_M 0xff00 495 #define R92C_SPEC_SIFS_OFDM_S 8 496 497 /* Bits for R92C_RL. */ 498 #define R92C_RL_LRL_M 0x003f 499 #define R92C_RL_LRL_S 0 500 #define R92C_RL_SRL_M 0x3f00 501 #define R92C_RL_SRL_S 8 502 503 /* Bits for R92C_RRSR. */ 504 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 505 #define R92C_RRSR_RATE_BITMAP_S 0 506 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 507 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 508 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 509 #define R92C_RRSR_SHORT 0x00800000 510 511 /* Bits for R88E_TX_RPT_CTRL. */ 512 #define R88E_TX_RPT1_ENA 0x01 513 #define R88E_TX_RPT2_ENA 0x02 514 515 /* Bits for R92C_EDCA_XX_PARAM. */ 516 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 517 #define R92C_EDCA_PARAM_AIFS_S 0 518 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 519 #define R92C_EDCA_PARAM_ECWMIN_S 8 520 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 521 #define R92C_EDCA_PARAM_ECWMAX_S 12 522 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 523 #define R92C_EDCA_PARAM_TXOP_S 16 524 525 /* Bits for R92C_HWSEQ_CTRL / R92C_TXPAUSE. */ 526 #define R92C_TX_QUEUE_VO 0x01 527 #define R92C_TX_QUEUE_VI 0x02 528 #define R92C_TX_QUEUE_BE 0x04 529 #define R92C_TX_QUEUE_BK 0x08 530 #define R92C_TX_QUEUE_MGT 0x10 531 #define R92C_TX_QUEUE_HIGH 0x20 532 #define R92C_TX_QUEUE_BCN 0x40 533 534 /* Shortcuts. */ 535 #define R92C_TX_QUEUE_AC \ 536 (R92C_TX_QUEUE_VO | R92C_TX_QUEUE_VI | \ 537 R92C_TX_QUEUE_BE | R92C_TX_QUEUE_BK) 538 539 #define R92C_TX_QUEUE_ALL \ 540 (R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | \ 541 R92C_TX_QUEUE_HIGH | R92C_TX_QUEUE_BCN | 0x80) /* XXX */ 542 543 /* Bits for R92C_BCN_CTRL. */ 544 #define R92C_BCN_CTRL_EN_MBSSID 0x02 545 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 546 #define R92C_BCN_CTRL_EN_BCN 0x08 547 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 548 549 /* Bits for R92C_MBID_NUM. */ 550 #define R92C_MBID_TXBCN_RPT0 0x08 551 #define R92C_MBID_TXBCN_RPT1 0x10 552 553 /* Bits for R92C_DUAL_TSF_RST. */ 554 #define R92C_DUAL_TSF_RST0 0x01 555 #define R92C_DUAL_TSF_RST1 0x02 556 557 /* Bits for R92C_ACMHWCTRL. */ 558 #define R92C_ACMHWCTRL_EN 0x01 559 #define R92C_ACMHWCTRL_BE 0x02 560 #define R92C_ACMHWCTRL_VI 0x04 561 #define R92C_ACMHWCTRL_VO 0x08 562 #define R92C_ACMHWCTRL_ACM_MASK 0x0f 563 564 /* Bits for R92C_APSD_CTRL. */ 565 #define R92C_APSD_CTRL_OFF 0x40 566 #define R92C_APSD_CTRL_OFF_STATUS 0x80 567 568 /* Bits for R92C_BWOPMODE. */ 569 #define R92C_BWOPMODE_11J 0x01 570 #define R92C_BWOPMODE_5G 0x02 571 #define R92C_BWOPMODE_20MHZ 0x04 572 573 /* Bits for R92C_RCR. */ 574 #define R92C_RCR_AAP 0x00000001 575 #define R92C_RCR_APM 0x00000002 576 #define R92C_RCR_AM 0x00000004 577 #define R92C_RCR_AB 0x00000008 578 #define R92C_RCR_ADD3 0x00000010 579 #define R92C_RCR_APWRMGT 0x00000020 580 #define R92C_RCR_CBSSID_DATA 0x00000040 581 #define R92C_RCR_CBSSID_BCN 0x00000080 582 #define R92C_RCR_ACRC32 0x00000100 583 #define R92C_RCR_AICV 0x00000200 584 #define R92C_RCR_ADF 0x00000800 585 #define R92C_RCR_ACF 0x00001000 586 #define R92C_RCR_AMF 0x00002000 587 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 588 #define R92C_RCR_MFBEN 0x00400000 589 #define R92C_RCR_LSIGEN 0x00800000 590 #define R92C_RCR_ENMBID 0x01000000 591 #define R92C_RCR_APP_BA_SSN 0x08000000 592 #define R92C_RCR_APP_PHYSTS 0x10000000 593 #define R92C_RCR_APP_ICV 0x20000000 594 #define R92C_RCR_APP_MIC 0x40000000 595 #define R92C_RCR_APPFCS 0x80000000 596 597 /* Bits for R92C_CAMCMD. */ 598 #define R92C_CAMCMD_ADDR_M 0x0000ffff 599 #define R92C_CAMCMD_ADDR_S 0 600 #define R92C_CAMCMD_WRITE 0x00010000 601 #define R92C_CAMCMD_CLR 0x40000000 602 #define R92C_CAMCMD_POLLING 0x80000000 603 604 /* Bits for R92C_SECCFG. */ 605 #define R92C_SECCFG_TXUCKEY_DEF 0x0001 606 #define R92C_SECCFG_RXUCKEY_DEF 0x0002 607 #define R92C_SECCFG_TXENC_ENA 0x0004 608 #define R92C_SECCFG_RXDEC_ENA 0x0008 609 #define R92C_SECCFG_CMP_A2 0x0010 610 #define R92C_SECCFG_TXBCKEY_DEF 0x0040 611 #define R92C_SECCFG_RXBCKEY_DEF 0x0080 612 #define R88E_SECCFG_CHK_KEYID 0x0100 613 614 /* Bits for R92C_RXFLTMAP*. */ 615 #define R92C_RXFLTMAP_SUBTYPE(subtype) \ 616 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT)) 617 618 619 /* 620 * Baseband registers. 621 */ 622 #define R92C_FPGA0_RFMOD 0x800 623 #define R92C_FPGA0_TXINFO 0x804 624 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 625 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 626 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 627 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 628 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 629 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 630 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 631 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 632 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 633 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 634 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 635 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 636 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 637 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 638 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 639 #define R92C_FPGA0_ANAPARAM2 0x884 640 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 641 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 642 #define R92C_FPGA1_RFMOD 0x900 643 #define R92C_FPGA1_TXINFO 0x90c 644 #define R92C_CCK0_SYSTEM 0xa00 645 #define R92C_CCK0_AFESETTING 0xa04 646 #define R92C_OFDM0_TRXPATHENA 0xc04 647 #define R92C_OFDM0_TRMUXPAR 0xc08 648 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 649 #define R92C_OFDM0_AGCPARAM1 0xc70 650 #define R92C_OFDM0_AGCRSSITABLE 0xc78 651 #define R92C_OFDM1_LSTF 0xd00 652 653 /* Bits for R92C_FPGA[01]_RFMOD. */ 654 #define R92C_RFMOD_40MHZ 0x00000001 655 #define R92C_RFMOD_JAPAN 0x00000002 656 #define R92C_RFMOD_CCK_TXSC 0x00000030 657 #define R92C_RFMOD_CCK_EN 0x01000000 658 #define R92C_RFMOD_OFDM_EN 0x02000000 659 660 /* Bits for R92C_HSSI_PARAM1(i). */ 661 #define R92C_HSSI_PARAM1_PI 0x00000100 662 663 /* Bits for R92C_HSSI_PARAM2(i). */ 664 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 665 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 666 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 667 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 668 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 669 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 670 671 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 672 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 673 #define R92C_TXAGC_A_CCK1_S 8 674 675 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 676 #define R92C_TXAGC_B_CCK11_M 0x000000ff 677 #define R92C_TXAGC_B_CCK11_S 0 678 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 679 #define R92C_TXAGC_A_CCK2_S 8 680 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 681 #define R92C_TXAGC_A_CCK55_S 16 682 #define R92C_TXAGC_A_CCK11_M 0xff000000 683 #define R92C_TXAGC_A_CCK11_S 24 684 685 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 686 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 687 #define R92C_TXAGC_B_CCK1_S 8 688 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 689 #define R92C_TXAGC_B_CCK2_S 16 690 #define R92C_TXAGC_B_CCK55_M 0xff000000 691 #define R92C_TXAGC_B_CCK55_S 24 692 693 /* Bits for R92C_TXAGC_RATE18_06(x). */ 694 #define R92C_TXAGC_RATE06_M 0x000000ff 695 #define R92C_TXAGC_RATE06_S 0 696 #define R92C_TXAGC_RATE09_M 0x0000ff00 697 #define R92C_TXAGC_RATE09_S 8 698 #define R92C_TXAGC_RATE12_M 0x00ff0000 699 #define R92C_TXAGC_RATE12_S 16 700 #define R92C_TXAGC_RATE18_M 0xff000000 701 #define R92C_TXAGC_RATE18_S 24 702 703 /* Bits for R92C_TXAGC_RATE54_24(x). */ 704 #define R92C_TXAGC_RATE24_M 0x000000ff 705 #define R92C_TXAGC_RATE24_S 0 706 #define R92C_TXAGC_RATE36_M 0x0000ff00 707 #define R92C_TXAGC_RATE36_S 8 708 #define R92C_TXAGC_RATE48_M 0x00ff0000 709 #define R92C_TXAGC_RATE48_S 16 710 #define R92C_TXAGC_RATE54_M 0xff000000 711 #define R92C_TXAGC_RATE54_S 24 712 713 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 714 #define R92C_TXAGC_MCS00_M 0x000000ff 715 #define R92C_TXAGC_MCS00_S 0 716 #define R92C_TXAGC_MCS01_M 0x0000ff00 717 #define R92C_TXAGC_MCS01_S 8 718 #define R92C_TXAGC_MCS02_M 0x00ff0000 719 #define R92C_TXAGC_MCS02_S 16 720 #define R92C_TXAGC_MCS03_M 0xff000000 721 #define R92C_TXAGC_MCS03_S 24 722 723 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 724 #define R92C_TXAGC_MCS04_M 0x000000ff 725 #define R92C_TXAGC_MCS04_S 0 726 #define R92C_TXAGC_MCS05_M 0x0000ff00 727 #define R92C_TXAGC_MCS05_S 8 728 #define R92C_TXAGC_MCS06_M 0x00ff0000 729 #define R92C_TXAGC_MCS06_S 16 730 #define R92C_TXAGC_MCS07_M 0xff000000 731 #define R92C_TXAGC_MCS07_S 24 732 733 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 734 #define R92C_TXAGC_MCS08_M 0x000000ff 735 #define R92C_TXAGC_MCS08_S 0 736 #define R92C_TXAGC_MCS09_M 0x0000ff00 737 #define R92C_TXAGC_MCS09_S 8 738 #define R92C_TXAGC_MCS10_M 0x00ff0000 739 #define R92C_TXAGC_MCS10_S 16 740 #define R92C_TXAGC_MCS11_M 0xff000000 741 #define R92C_TXAGC_MCS11_S 24 742 743 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 744 #define R92C_TXAGC_MCS12_M 0x000000ff 745 #define R92C_TXAGC_MCS12_S 0 746 #define R92C_TXAGC_MCS13_M 0x0000ff00 747 #define R92C_TXAGC_MCS13_S 8 748 #define R92C_TXAGC_MCS14_M 0x00ff0000 749 #define R92C_TXAGC_MCS14_S 16 750 #define R92C_TXAGC_MCS15_M 0xff000000 751 #define R92C_TXAGC_MCS15_S 24 752 753 /* Bits for R92C_LSSI_PARAM(i). */ 754 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 755 #define R92C_LSSI_PARAM_DATA_S 0 756 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 757 #define R92C_LSSI_PARAM_ADDR_S 20 758 #define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 759 #define R88E_LSSI_PARAM_ADDR_S 20 760 761 /* Bits for R92C_FPGA0_ANAPARAM2. */ 762 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 763 764 /* Bits for R92C_LSSI_READBACK(i). */ 765 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 766 #define R92C_LSSI_READBACK_DATA_S 0 767 768 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 769 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 770 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 771 772 773 /* 774 * USB registers. 775 */ 776 #define R92C_USB_SUSPEND 0xfe10 777 #define R92C_USB_INFO 0xfe17 778 #define R92C_USB_SPECIAL_OPTION 0xfe55 779 #define R92C_USB_HCPWM 0xfe57 780 #define R92C_USB_HRPWM 0xfe58 781 #define R92C_USB_DMA_AGG_TO 0xfe5b 782 #define R92C_USB_AGG_TO 0xfe5c 783 #define R92C_USB_AGG_TH 0xfe5d 784 #define R92C_USB_VID 0xfe60 785 #define R92C_USB_PID 0xfe62 786 #define R92C_USB_OPTIONAL 0xfe64 787 #define R92C_USB_EP 0xfe65 788 #define R92C_USB_PHY 0xfe68 789 #define R92C_USB_MAC_ADDR 0xfe70 790 #define R92C_USB_STRING 0xfe80 791 792 /* Bits for R92C_USB_SPECIAL_OPTION. */ 793 #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 794 #define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 795 796 /* Bits for R92C_USB_EP. */ 797 #define R92C_USB_EP_HQ_M 0x000f 798 #define R92C_USB_EP_HQ_S 0 799 #define R92C_USB_EP_NQ_M 0x00f0 800 #define R92C_USB_EP_NQ_S 4 801 #define R92C_USB_EP_LQ_M 0x0f00 802 #define R92C_USB_EP_LQ_S 8 803 804 805 /* 806 * Firmware base address. 807 */ 808 #define R92C_FW_START_ADDR 0x1000 809 #define R92C_FW_PAGE_SIZE 4096 810 811 812 /* 813 * RF (6052) registers. 814 */ 815 #define R92C_RF_AC 0x00 816 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 817 #define R92C_RF_POW_TRSW 0x05 818 #define R92C_RF_GAIN_RX 0x06 819 #define R92C_RF_GAIN_TX 0x07 820 #define R92C_RF_TXM_IDAC 0x08 821 #define R92C_RF_BS_IQGEN 0x0f 822 #define R92C_RF_MODE1 0x10 823 #define R92C_RF_MODE2 0x11 824 #define R92C_RF_RX_AGC_HP 0x12 825 #define R92C_RF_TX_AGC 0x13 826 #define R92C_RF_BIAS 0x14 827 #define R92C_RF_IPA 0x15 828 #define R92C_RF_POW_ABILITY 0x17 829 #define R92C_RF_CHNLBW 0x18 830 #define R92C_RF_RX_G1 0x1a 831 #define R92C_RF_RX_G2 0x1b 832 #define R92C_RF_RX_BB2 0x1c 833 #define R92C_RF_RX_BB1 0x1d 834 #define R92C_RF_RCK1 0x1e 835 #define R92C_RF_RCK2 0x1f 836 #define R92C_RF_TX_G(i) (0x20 + (i)) 837 #define R92C_RF_TX_BB1 0x23 838 #define R92C_RF_T_METER 0x24 839 #define R92C_RF_SYN_G(i) (0x25 + (i)) 840 #define R92C_RF_RCK_OS 0x30 841 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 842 #define R88E_RF_T_METER 0x42 843 844 /* Bits for R92C_RF_AC. */ 845 #define R92C_RF_AC_MODE_M 0x70000 846 #define R92C_RF_AC_MODE_S 16 847 #define R92C_RF_AC_MODE_STANDBY 1 848 849 /* Bits for R92C_RF_CHNLBW. */ 850 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 851 #define R92C_RF_CHNLBW_CHNL_S 0 852 #define R92C_RF_CHNLBW_BW20 0x00400 853 #define R88E_RF_CHNLBW_BW20 0x00c00 854 #define R92C_RF_CHNLBW_LCSTART 0x08000 855 856 /* Bits for R92C_RF_T_METER. */ 857 #define R92C_RF_T_METER_START 0x60 858 #define R92C_RF_T_METER_VAL_M 0x1f 859 #define R92C_RF_T_METER_VAL_S 0 860 861 /* Bits for R88E_RF_T_METER. */ 862 #define R88E_RF_T_METER_VAL_M 0x0fc00 863 #define R88E_RF_T_METER_VAL_S 10 864 #define R88E_RF_T_METER_START 0x30000 865 866 867 /* 868 * CAM entries. 869 */ 870 #define R92C_CAM_ENTRY_COUNT 32 871 872 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 873 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 874 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 875 #define R92C_CAM_CTL6(entry) ((entry) * 8 + 6) 876 #define R92C_CAM_CTL7(entry) ((entry) * 8 + 7) 877 878 /* Bits for R92C_CAM_CTL0(i). */ 879 #define R92C_CAM_KEYID_M 0x00000003 880 #define R92C_CAM_KEYID_S 0 881 #define R92C_CAM_ALGO_M 0x0000001c 882 #define R92C_CAM_ALGO_S 2 883 #define R92C_CAM_ALGO_NONE 0 884 #define R92C_CAM_ALGO_WEP40 1 885 #define R92C_CAM_ALGO_TKIP 2 886 #define R92C_CAM_ALGO_AES 4 887 #define R92C_CAM_ALGO_WEP104 5 888 #define R92C_CAM_VALID 0x00008000 889 #define R92C_CAM_MACLO_M 0xffff0000 890 #define R92C_CAM_MACLO_S 16 891 892 /* Rate adaptation modes. */ 893 #define R92C_RAID_11GN 1 894 #define R92C_RAID_11N 3 895 #define R92C_RAID_11BG 4 896 #define R92C_RAID_11G 5 /* "pure" 11g */ 897 #define R92C_RAID_11B 6 898 899 900 /* 901 * Macros to access subfields in registers. 902 */ 903 /* Mask and Shift (getter). */ 904 #define MS(val, field) \ 905 (((val) & field##_M) >> field##_S) 906 907 /* Shift and Mask (setter). */ 908 #define SM(field, val) \ 909 (((val) << field##_S) & field##_M) 910 911 /* Rewrite. */ 912 #define RW(var, field, val) \ 913 (((var) & ~field##_M) | SM(field, val)) 914 915 /* 916 * Firmware image header. 917 */ 918 struct r92c_fw_hdr { 919 /* QWORD0 */ 920 uint16_t signature; 921 uint8_t category; 922 uint8_t function; 923 uint16_t version; 924 uint16_t subversion; 925 /* QWORD1 */ 926 uint8_t month; 927 uint8_t date; 928 uint8_t hour; 929 uint8_t minute; 930 uint16_t ramcodesize; 931 uint16_t reserved2; 932 /* QWORD2 */ 933 uint32_t svnidx; 934 uint32_t reserved3; 935 /* QWORD3 */ 936 uint32_t reserved4; 937 uint32_t reserved5; 938 } __packed; 939 940 /* 941 * Host to firmware commands. 942 */ 943 struct r92c_fw_cmd { 944 uint8_t id; 945 #define R92C_CMD_AP_OFFLOAD 0 946 #define R92C_CMD_SET_PWRMODE 1 947 #define R92C_CMD_JOINBSS_RPT 2 948 #define R92C_CMD_RSVD_PAGE 3 949 #define R92C_CMD_RSSI 4 950 #define R92C_CMD_RSSI_SETTING 5 951 #define R92C_CMD_MACID_CONFIG 6 952 #define R92C_CMD_MACID_PS_MODE 7 953 #define R92C_CMD_P2P_PS_OFFLOAD 8 954 #define R92C_CMD_SELECTIVE_SUSPEND 9 955 #define R92C_CMD_FLAG_EXT 0x80 956 957 uint8_t msg[5]; 958 } __packed; 959 960 /* Structure for R92C_CMD_RSSI_SETTING. */ 961 struct r92c_fw_cmd_rssi { 962 uint8_t macid; 963 uint8_t reserved; 964 uint8_t pwdb; 965 } __packed; 966 967 /* Structure for R92C_CMD_MACID_CONFIG. */ 968 struct r92c_fw_cmd_macid_cfg { 969 uint32_t mask; 970 uint8_t macid; 971 #define URTWN_MACID_BSS 0 972 #define URTWN_MACID_BC 4 /* Broadcast. */ 973 #define R92C_MACID_MAX 31 974 #define R88E_MACID_MAX 63 975 #define URTWN_MACID_MAX(sc) (((sc)->chip & URTWN_CHIP_88E) ? \ 976 R88E_MACID_MAX : R92C_MACID_MAX) 977 #define URTWN_MACID_UNDEFINED (uint8_t)-1 978 #define URTWN_MACID_VALID 0x80 979 } __packed; 980 981 /* 982 * RTL8192CU ROM image. 983 */ 984 struct r92c_rom { 985 uint16_t id; /* 0x8192 */ 986 uint8_t reserved1[5]; 987 uint8_t dbg_sel; 988 uint16_t reserved2; 989 uint16_t vid; 990 uint16_t pid; 991 uint8_t usb_opt; 992 uint8_t ep_setting; 993 uint16_t reserved3; 994 uint8_t usb_phy; 995 uint8_t reserved4[3]; 996 uint8_t macaddr[IEEE80211_ADDR_LEN]; 997 uint8_t string[61]; /* "Realtek" */ 998 uint8_t subcustomer_id; 999 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 1000 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 1001 uint8_t ht40_2s_tx_pwr_diff[3]; 1002 uint8_t ht20_tx_pwr_diff[3]; 1003 uint8_t ofdm_tx_pwr_diff[3]; 1004 uint8_t ht40_max_pwr[3]; 1005 uint8_t ht20_max_pwr[3]; 1006 uint8_t xtal_calib; 1007 uint8_t tssi[R92C_MAX_CHAINS]; 1008 uint8_t thermal_meter; 1009 uint8_t rf_opt1; 1010 #define R92C_ROM_RF1_REGULATORY_M 0x07 1011 #define R92C_ROM_RF1_REGULATORY_S 0 1012 #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1013 #define R92C_ROM_RF1_BOARD_TYPE_S 5 1014 #define R92C_BOARD_TYPE_DONGLE 0 1015 #define R92C_BOARD_TYPE_HIGHPA 1 1016 #define R92C_BOARD_TYPE_MINICARD 2 1017 #define R92C_BOARD_TYPE_SOLO 3 1018 #define R92C_BOARD_TYPE_COMBO 4 1019 1020 uint8_t rf_opt2; 1021 uint8_t rf_opt3; 1022 uint8_t rf_opt4; 1023 uint8_t channel_plan; 1024 #define R92C_CHANNEL_PLAN_BY_HW 0x80 1025 1026 uint8_t version; 1027 uint8_t customer_id; 1028 } __packed; 1029 1030 /* 1031 * RTL8188EU ROM image. 1032 */ 1033 struct r88e_rom { 1034 uint8_t reserved1[16]; 1035 uint8_t cck_tx_pwr[6]; 1036 uint8_t ht40_tx_pwr[5]; 1037 uint8_t tx_pwr_diff; 1038 uint8_t reserved2[156]; 1039 uint8_t channel_plan; 1040 uint8_t crystalcap; 1041 uint8_t reserved3[7]; 1042 uint8_t rf_board_opt; 1043 uint8_t rf_feature_opt; 1044 uint8_t rf_bt_opt; 1045 uint8_t version; 1046 uint8_t customer_id; 1047 uint8_t reserved4[3]; 1048 uint8_t rf_ant_opt; 1049 uint8_t reserved5[6]; 1050 uint16_t vid; 1051 uint16_t pid; 1052 uint8_t usb_opt; 1053 uint8_t reserved6[2]; 1054 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1055 uint8_t reserved7[2]; 1056 uint8_t string[33]; /* "realtek 802.11n NIC" */ 1057 uint8_t reserved8[256]; 1058 } __packed; 1059 1060 #define URTWN_EFUSE_MAX_LEN 512 1061 1062 /* Rx MAC descriptor. */ 1063 struct r92c_rx_stat { 1064 uint32_t rxdw0; 1065 #define R92C_RXDW0_PKTLEN_M 0x00003fff 1066 #define R92C_RXDW0_PKTLEN_S 0 1067 #define R92C_RXDW0_CRCERR 0x00004000 1068 #define R92C_RXDW0_ICVERR 0x00008000 1069 #define R92C_RXDW0_INFOSZ_M 0x000f0000 1070 #define R92C_RXDW0_INFOSZ_S 16 1071 #define R92C_RXDW0_CIPHER_M 0x00700000 1072 #define R92C_RXDW0_CIPHER_S 20 1073 #define R92C_RXDW0_QOS 0x00800000 1074 #define R92C_RXDW0_SHIFT_M 0x03000000 1075 #define R92C_RXDW0_SHIFT_S 24 1076 #define R92C_RXDW0_PHYST 0x04000000 1077 #define R92C_RXDW0_DECRYPTED 0x08000000 1078 1079 uint32_t rxdw1; 1080 uint32_t rxdw2; 1081 #define R92C_RXDW2_PKTCNT_M 0x00ff0000 1082 #define R92C_RXDW2_PKTCNT_S 16 1083 1084 uint32_t rxdw3; 1085 #define R92C_RXDW3_RATE_M 0x0000003f 1086 #define R92C_RXDW3_RATE_S 0 1087 #define R92C_RXDW3_HT 0x00000040 1088 #define R92C_RXDW3_HTC 0x00000400 1089 #define R88E_RXDW3_RPT_M 0x0000c000 1090 #define R88E_RXDW3_RPT_S 14 1091 #define R88E_RXDW3_RPT_RX 0 1092 #define R88E_RXDW3_RPT_TX1 1 1093 #define R88E_RXDW3_RPT_TX2 2 1094 1095 uint32_t rxdw4; 1096 uint32_t rxdw5; 1097 } __packed __attribute__((aligned(4))); 1098 1099 /* Rx PHY descriptor. */ 1100 struct r92c_rx_phystat { 1101 uint32_t phydw0; 1102 uint32_t phydw1; 1103 uint32_t phydw2; 1104 uint32_t phydw3; 1105 uint32_t phydw4; 1106 uint32_t phydw5; 1107 uint32_t phydw6; 1108 uint32_t phydw7; 1109 } __packed __attribute__((aligned(4))); 1110 1111 /* Rx PHY CCK descriptor. */ 1112 struct r92c_rx_cck { 1113 uint8_t adc_pwdb[4]; 1114 uint8_t sq_rpt; 1115 uint8_t agc_rpt; 1116 } __packed; 1117 1118 struct r88e_rx_cck { 1119 uint8_t path_agc[2]; 1120 uint8_t chan; 1121 uint8_t reserved1; 1122 uint8_t sig_qual; 1123 uint8_t agc_rpt; 1124 uint8_t rpt_b; 1125 uint8_t reserved2; 1126 uint8_t noise_power; 1127 uint8_t path_cfotail[2]; 1128 uint8_t pcts_mask[2]; 1129 uint8_t stream_rxevm[2]; 1130 uint8_t path_rxsnr[2]; 1131 uint8_t noise_power_db_lsb; 1132 uint8_t reserved3[3]; 1133 uint8_t stream_csi[2]; 1134 uint8_t stream_target_csi[2]; 1135 uint8_t sig_evm; 1136 } __packed; 1137 1138 /* Tx MAC descriptor. */ 1139 struct r92c_tx_desc { 1140 uint32_t txdw0; 1141 #define R92C_TXDW0_PKTLEN_M 0x0000ffff 1142 #define R92C_TXDW0_PKTLEN_S 0 1143 #define R92C_TXDW0_OFFSET_M 0x00ff0000 1144 #define R92C_TXDW0_OFFSET_S 16 1145 #define R92C_TXDW0_BMCAST 0x01000000 1146 #define R92C_TXDW0_LSG 0x04000000 1147 #define R92C_TXDW0_FSG 0x08000000 1148 #define R92C_TXDW0_OWN 0x80000000 1149 1150 uint32_t txdw1; 1151 #define R92C_TXDW1_MACID_M 0x0000001f 1152 #define R92C_TXDW1_MACID_S 0 1153 #define R88E_TXDW1_MACID_M 0x0000003f 1154 #define R88E_TXDW1_MACID_S 0 1155 #define R92C_TXDW1_AGGEN 0x00000020 1156 #define R92C_TXDW1_AGGBK 0x00000040 1157 #define R92C_TXDW1_QSEL_M 0x00001f00 1158 #define R92C_TXDW1_QSEL_S 8 1159 1160 #define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 */ 1161 #define R92C_TXDW1_QSEL_BK 0x01 /* or 0x02 */ 1162 #define R92C_TXDW1_QSEL_VI 0x04 /* or 0x05 */ 1163 #define R92C_TXDW1_QSEL_VO 0x06 /* or 0x07 */ 1164 #define URTWN_MAX_TID 8 1165 1166 #define R92C_TXDW1_QSEL_BEACON 0x10 1167 #define R92C_TXDW1_QSEL_MGNT 0x12 1168 1169 #define R92C_TXDW1_RAID_M 0x000f0000 1170 #define R92C_TXDW1_RAID_S 16 1171 #define R92C_TXDW1_CIPHER_M 0x00c00000 1172 #define R92C_TXDW1_CIPHER_S 22 1173 #define R92C_TXDW1_CIPHER_NONE 0 1174 #define R92C_TXDW1_CIPHER_RC4 1 1175 #define R92C_TXDW1_CIPHER_AES 3 1176 #define R92C_TXDW1_PKTOFF_M 0x7c000000 1177 #define R92C_TXDW1_PKTOFF_S 26 1178 1179 uint32_t txdw2; 1180 #define R88E_TXDW2_AGGBK 0x00010000 1181 #define R88E_TXDW2_CCX_RPT 0x00080000 1182 1183 uint16_t txdw3; 1184 uint16_t txdseq; 1185 #define R88E_TXDSEQ_HWSEQ_EN 0x8000 1186 1187 uint32_t txdw4; 1188 #define R92C_TXDW4_RTSRATE_M 0x0000003f 1189 #define R92C_TXDW4_RTSRATE_S 0 1190 #define R92C_TXDW4_HWSEQ_QOS 0x00000040 1191 #define R92C_TXDW4_HWSEQ_EN 0x00000080 1192 #define R92C_TXDW4_DRVRATE 0x00000100 1193 #define R92C_TXDW4_CTS2SELF 0x00000800 1194 #define R92C_TXDW4_RTSEN 0x00001000 1195 #define R92C_TXDW4_HWRTSEN 0x00002000 1196 #define R92C_TXDW4_SCO_M 0x003f0000 1197 #define R92C_TXDW4_SCO_S 20 1198 #define R92C_TXDW4_SCO_SCA 1 1199 #define R92C_TXDW4_SCO_SCB 2 1200 #define R92C_TXDW4_40MHZ 0x02000000 1201 1202 uint32_t txdw5; 1203 #define R92C_TXDW5_DATARATE_M 0x0000003f 1204 #define R92C_TXDW5_DATARATE_S 0 1205 #define R92C_TXDW5_SGI 0x00000040 1206 #define R92C_TXDW5_RTY_LMT_ENA 0x00020000 1207 #define R92C_TXDW5_RTY_LMT_M 0x00fc0000 1208 #define R92C_TXDW5_RTY_LMT_S 18 1209 #define R92C_TXDW5_AGGNUM_M 0xff000000 1210 #define R92C_TXDW5_AGGNUM_S 24 1211 1212 uint32_t txdw6; 1213 uint16_t txdsum; 1214 uint16_t pad; 1215 } __packed __attribute__((aligned(4))); 1216 1217 struct r88e_tx_rpt_ccx { 1218 uint8_t rptb0; 1219 uint8_t rptb1; 1220 #define R88E_RPTB1_MACID_M 0x3f 1221 #define R88E_RPTB1_MACID_S 0 1222 #define R88E_RPTB1_PKT_OK 0x40 1223 #define R88E_RPTB1_BMC 0x80 1224 1225 uint8_t rptb2; 1226 #define R88E_RPTB2_RETRY_CNT_M 0x3f 1227 #define R88E_RPTB2_RETRY_CNT_S 0 1228 #define R88E_RPTB2_LIFE_EXPIRE 0x40 1229 #define R88E_RPTB2_RETRY_OVER 0x80 1230 1231 uint8_t rptb3; 1232 uint8_t rptb4; 1233 uint8_t rptb5; 1234 uint8_t rptb6; 1235 #define R88E_RPTB6_QSEL_M 0xf0 1236 #define R88E_RPTB6_QSEL_S 4 1237 1238 uint8_t rptb7; 1239 } __packed; 1240 1241 1242 static const uint8_t ridx2rate[] = 1243 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1244 1245 /* HW rate indices. */ 1246 #define URTWN_RIDX_CCK1 0 1247 #define URTWN_RIDX_CCK11 3 1248 #define URTWN_RIDX_OFDM6 4 1249 #define URTWN_RIDX_OFDM24 8 1250 #define URTWN_RIDX_OFDM54 11 1251 1252 #define URTWN_RIDX_COUNT 28 1253 #define URTWN_RIDX_UNKNOWN (uint8_t)-1 1254 1255 1256 /* 1257 * MAC initialization values. 1258 */ 1259 static const struct { 1260 uint16_t reg; 1261 uint8_t val; 1262 } rtl8188eu_mac[] = { 1263 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a }, 1264 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 }, 1265 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 }, 1266 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 }, 1267 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 }, 1268 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, 1269 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 }, 1270 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 }, 1271 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff }, 1272 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 }, 1273 { 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f }, 1274 { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e }, 1275 { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e }, 1276 { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 }, 1277 { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a }, 1278 { 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, 1279 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1280 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1281 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1282 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1283 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 }, 1284 { 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, 1285 { 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 } 1286 }, rtl8192cu_mac[] = { 1287 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1288 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1289 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1290 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1291 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1292 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1293 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1294 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1295 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1296 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1297 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1298 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1299 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1300 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1301 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1302 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1303 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1304 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1305 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1306 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1307 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1308 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1309 }; 1310 1311 /* 1312 * Baseband initialization values. 1313 */ 1314 struct urtwn_bb_prog { 1315 int count; 1316 const uint16_t *regs; 1317 const uint32_t *vals; 1318 int agccount; 1319 const uint32_t *agcvals; 1320 }; 1321 1322 /* 1323 * RTL8192CU and RTL8192CE-VAU. 1324 */ 1325 static const uint16_t rtl8192ce_bb_regs[] = { 1326 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1327 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1328 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1329 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1330 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1331 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1332 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1333 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1334 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1335 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1336 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1337 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1338 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1339 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1340 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1341 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1342 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1343 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1344 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1345 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1346 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1347 }; 1348 1349 static const uint32_t rtl8192ce_bb_vals[] = { 1350 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1351 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1352 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1353 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1354 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1355 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1356 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1357 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1358 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1359 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1360 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1361 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1362 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1363 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1364 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1365 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1366 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1367 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1368 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1369 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1370 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1371 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1372 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1373 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1374 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1375 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1376 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1377 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1378 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1379 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1380 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1381 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1382 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1383 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1384 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1385 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1386 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1387 0x00000000, 0x00000300 1388 }; 1389 1390 static const uint32_t rtl8192ce_agc_vals[] = { 1391 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1392 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1393 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1394 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1395 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1396 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1397 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1398 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1399 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1400 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1401 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1402 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1403 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1404 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1405 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1406 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1407 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1408 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1409 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1410 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1411 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1412 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1413 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1414 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1415 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1416 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1417 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1418 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1419 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1420 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1421 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1422 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1423 }; 1424 1425 static const struct urtwn_bb_prog rtl8192ce_bb_prog = { 1426 nitems(rtl8192ce_bb_regs), 1427 rtl8192ce_bb_regs, 1428 rtl8192ce_bb_vals, 1429 nitems(rtl8192ce_agc_vals), 1430 rtl8192ce_agc_vals 1431 }; 1432 1433 /* 1434 * RTL8188CU. 1435 */ 1436 static const uint32_t rtl8192cu_bb_vals[] = { 1437 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1438 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1439 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1440 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1441 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1442 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1443 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1444 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1445 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1446 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1447 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1448 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1449 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1450 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1451 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1452 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1453 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1454 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1455 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1456 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1457 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1458 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1459 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1460 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1461 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1462 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1463 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1464 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1465 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1466 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1467 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1468 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1469 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1470 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1471 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1472 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1473 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1474 0x00000000, 0x00000300 1475 }; 1476 1477 static const struct urtwn_bb_prog rtl8192cu_bb_prog = { 1478 nitems(rtl8192ce_bb_regs), 1479 rtl8192ce_bb_regs, 1480 rtl8192cu_bb_vals, 1481 nitems(rtl8192ce_agc_vals), 1482 rtl8192ce_agc_vals 1483 }; 1484 1485 /* 1486 * RTL8188CE-VAU. 1487 */ 1488 static const uint32_t rtl8188ce_bb_vals[] = { 1489 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1490 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1491 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1492 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1493 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1494 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1495 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1496 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1497 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1498 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1499 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1500 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1501 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1502 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1503 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1504 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1505 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1506 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1507 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1508 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1509 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1510 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1511 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1512 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1513 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1514 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1515 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1516 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1517 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1518 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1519 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1520 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1521 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1522 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1523 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1524 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1525 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1526 0x00000000, 0x00000300 1527 }; 1528 1529 static const uint32_t rtl8188ce_agc_vals[] = { 1530 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1531 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1532 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1533 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1534 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1535 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1536 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1537 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1538 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1539 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1540 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1541 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1542 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1543 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1544 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1545 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1546 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1547 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1548 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1549 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1550 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1551 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1552 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1553 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1554 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1555 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1556 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1557 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1558 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1559 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1560 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1561 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1562 }; 1563 1564 static const struct urtwn_bb_prog rtl8188ce_bb_prog = { 1565 nitems(rtl8192ce_bb_regs), 1566 rtl8192ce_bb_regs, 1567 rtl8188ce_bb_vals, 1568 nitems(rtl8188ce_agc_vals), 1569 rtl8188ce_agc_vals 1570 }; 1571 1572 static const uint32_t rtl8188cu_bb_vals[] = { 1573 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1574 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1575 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1576 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1577 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1578 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1579 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1580 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1581 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1582 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1583 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1584 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1585 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1586 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1587 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1588 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1589 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1590 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1591 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1592 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1593 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1594 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1595 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1596 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1597 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1598 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1599 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1600 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1601 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1602 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1603 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1604 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1605 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1606 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1607 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1608 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1609 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1610 0x00000000, 0x00000300 1611 }; 1612 1613 static const struct urtwn_bb_prog rtl8188cu_bb_prog = { 1614 nitems(rtl8192ce_bb_regs), 1615 rtl8192ce_bb_regs, 1616 rtl8188cu_bb_vals, 1617 nitems(rtl8188ce_agc_vals), 1618 rtl8188ce_agc_vals 1619 }; 1620 1621 /* 1622 * RTL8188EU. 1623 */ 1624 static const uint16_t rtl8188eu_bb_regs[] = { 1625 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 1626 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1627 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1628 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 1629 0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 1630 0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04, 1631 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 1632 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 0xb2c, 1633 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 1634 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 1635 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 1636 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 1637 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 1638 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1639 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1640 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 1641 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 1642 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 1643 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 1644 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 1645 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 1646 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 1647 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1648 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14, 0xf4c, 0xf00 1649 }; 1650 1651 static const uint32_t rtl8188eu_bb_vals[] = { 1652 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 1653 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204, 1654 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1655 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 1656 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110, 1657 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000, 1658 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 1659 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 1660 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002, 1661 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f, 1662 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000, 1663 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1664 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40, 1665 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 1666 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 1667 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c, 1668 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420, 1669 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b, 1670 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f, 1671 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000, 1672 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 1673 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1674 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 1675 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 1676 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740, 1677 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 1678 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 1679 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1680 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68, 1681 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 1682 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d, 1683 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f, 1684 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 1685 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 1686 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014, 1687 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014, 1688 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014, 1689 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003, 1690 0x00000000, 0x00000300 1691 }; 1692 1693 static const uint32_t rtl8188eu_agc_vals[] = { 1694 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 1695 0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 1696 0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001, 1697 0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001, 1698 0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001, 1699 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001, 1700 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 1701 0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001, 1702 0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001, 1703 0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001, 1704 0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001, 1705 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001, 1706 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 1707 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 1708 0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001, 1709 0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001, 1710 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001, 1711 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001, 1712 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 1713 0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 1714 0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001, 1715 0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001, 1716 0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001, 1717 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001, 1718 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 1719 0x407d0001, 0x407e0001, 0x407f0001 1720 }; 1721 1722 static const struct urtwn_bb_prog rtl8188eu_bb_prog = { 1723 nitems(rtl8188eu_bb_regs), 1724 rtl8188eu_bb_regs, 1725 rtl8188eu_bb_vals, 1726 nitems(rtl8188eu_agc_vals), 1727 rtl8188eu_agc_vals 1728 }; 1729 1730 /* 1731 * RTL8188RU. 1732 */ 1733 static const uint16_t rtl8188ru_bb_regs[] = { 1734 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1735 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1736 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1737 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1738 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1739 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1740 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1741 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1742 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1743 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1744 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1745 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1746 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1747 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1748 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1749 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1750 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1751 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1752 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1753 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1754 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1755 }; 1756 1757 static const uint32_t rtl8188ru_bb_vals[] = { 1758 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1759 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1760 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1761 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1762 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1763 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1764 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1765 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1766 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1767 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1768 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1769 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1770 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1771 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1772 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1773 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1774 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1775 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1776 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1777 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1778 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1779 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1780 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1781 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1782 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1783 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1784 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1785 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1786 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1787 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1788 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1789 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1790 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1791 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1792 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1793 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1794 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1795 0x31555448, 0x00000003, 0x00000000, 0x00000300 1796 }; 1797 1798 static const uint32_t rtl8188ru_agc_vals[] = { 1799 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1800 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1801 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1802 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1803 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1804 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1805 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1806 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1807 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1808 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1809 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1810 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1811 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1812 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1813 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1814 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1815 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1816 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1817 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1818 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1819 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1820 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1821 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1822 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1823 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1824 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1825 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1826 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1827 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1828 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1829 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1830 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1831 }; 1832 1833 static const struct urtwn_bb_prog rtl8188ru_bb_prog = { 1834 nitems(rtl8188ru_bb_regs), 1835 rtl8188ru_bb_regs, 1836 rtl8188ru_bb_vals, 1837 nitems(rtl8188ru_agc_vals), 1838 rtl8188ru_agc_vals 1839 }; 1840 1841 /* 1842 * RF initialization values. 1843 */ 1844 struct urtwn_rf_prog { 1845 int count; 1846 const uint8_t *regs; 1847 const uint32_t *vals; 1848 }; 1849 1850 /* 1851 * RTL8192CU and RTL8192CE-VAU. 1852 */ 1853 static const uint8_t rtl8192ce_rf1_regs[] = { 1854 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1855 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1856 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1857 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1858 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1859 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1860 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1861 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1862 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1863 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1864 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1865 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1866 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1867 }; 1868 1869 static const uint32_t rtl8192ce_rf1_vals[] = { 1870 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1871 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1872 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1873 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1874 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1875 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1876 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1877 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1878 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1879 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1880 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1881 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1882 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1883 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1884 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1885 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1886 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1887 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1888 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1889 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1890 0x30159 1891 }; 1892 1893 static const uint8_t rtl8192ce_rf2_regs[] = { 1894 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1895 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1896 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1897 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1898 }; 1899 1900 static const uint32_t rtl8192ce_rf2_vals[] = { 1901 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1902 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1903 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1904 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1905 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1906 0xe0330, 0xa0330, 0x60330, 0x20330 1907 }; 1908 1909 static const struct urtwn_rf_prog rtl8192ce_rf_prog[] = { 1910 { 1911 nitems(rtl8192ce_rf1_regs), 1912 rtl8192ce_rf1_regs, 1913 rtl8192ce_rf1_vals 1914 }, 1915 { 1916 nitems(rtl8192ce_rf2_regs), 1917 rtl8192ce_rf2_regs, 1918 rtl8192ce_rf2_vals 1919 } 1920 }; 1921 1922 /* 1923 * RTL8188CE-VAU. 1924 */ 1925 static const uint32_t rtl8188ce_rf_vals[] = { 1926 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1927 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1928 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1929 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1930 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1931 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1932 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1933 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1934 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1935 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1936 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1937 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1938 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1939 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1940 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1941 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1942 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1943 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1944 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1945 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1946 0x30159 1947 }; 1948 1949 static const struct urtwn_rf_prog rtl8188ce_rf_prog[] = { 1950 { 1951 nitems(rtl8192ce_rf1_regs), 1952 rtl8192ce_rf1_regs, 1953 rtl8188ce_rf_vals 1954 } 1955 }; 1956 1957 1958 /* 1959 * RTL8188CU. 1960 */ 1961 static const uint32_t rtl8188cu_rf_vals[] = { 1962 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1963 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1964 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1965 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1966 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1967 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1968 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1969 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1970 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1971 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1972 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1973 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1974 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1975 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1976 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1977 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1978 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1979 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1980 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1981 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1982 0x30159 1983 }; 1984 1985 static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = { 1986 { 1987 nitems(rtl8192ce_rf1_regs), 1988 rtl8192ce_rf1_regs, 1989 rtl8188cu_rf_vals 1990 } 1991 }; 1992 1993 /* 1994 * RTL8188EU. 1995 */ 1996 static const uint8_t rtl8188eu_rf_regs[] = { 1997 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57, 1998 0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8, 1999 0xb9, 0xba, 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 2000 0xc8, 0xc9, 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 2001 0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18, 0x5a, 2002 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 2003 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b, 2004 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 2005 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 0xfe, 2006 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2007 }; 2008 2009 static const uint32_t rtl8188eu_rf_vals[] = { 2010 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 2011 0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 2012 0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 2013 0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999, 2014 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0, 2015 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186, 2016 0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07, 2017 0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 2018 0x054ee, 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 2019 0x68200, 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 2020 0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 2021 0x722b0, 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080, 2022 0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003, 2023 0x00000, 0x00000, 0x00001, 0x80000, 0x33e60 2024 }; 2025 2026 static const struct urtwn_rf_prog rtl8188eu_rf_prog[] = { 2027 { 2028 nitems(rtl8188eu_rf_regs), 2029 rtl8188eu_rf_regs, 2030 rtl8188eu_rf_vals 2031 } 2032 }; 2033 2034 /* 2035 * RTL8188RU. 2036 */ 2037 static const uint32_t rtl8188ru_rf_vals[] = { 2038 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 2039 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 2040 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2041 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 2042 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2043 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2044 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2045 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2046 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2047 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2048 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2049 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2050 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2051 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2052 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2053 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2054 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2055 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2056 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2057 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2058 0x30159 2059 }; 2060 2061 static const struct urtwn_rf_prog rtl8188ru_rf_prog[] = { 2062 { 2063 nitems(rtl8192ce_rf1_regs), 2064 rtl8192ce_rf1_regs, 2065 rtl8188ru_rf_vals 2066 } 2067 }; 2068 2069 struct urtwn_txpwr { 2070 uint8_t pwr[3][28]; 2071 }; 2072 2073 struct urtwn_r88e_txpwr { 2074 uint8_t pwr[6][28]; 2075 }; 2076 2077 /* 2078 * Per RF chain/group/rate Tx gain values. 2079 */ 2080 static const struct urtwn_txpwr rtl8192cu_txagc[] = { 2081 { { /* Chain 0. */ 2082 { /* Group 0. */ 2083 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2084 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 2085 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 2086 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 2087 }, 2088 { /* Group 1. */ 2089 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2090 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2091 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2092 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2093 }, 2094 { /* Group 2. */ 2095 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2096 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2097 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2098 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2099 } 2100 } }, 2101 { { /* Chain 1. */ 2102 { /* Group 0. */ 2103 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2104 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2106 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2107 }, 2108 { /* Group 1. */ 2109 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2110 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2111 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2113 }, 2114 { /* Group 2. */ 2115 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2116 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2117 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2118 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2119 } 2120 } } 2121 }; 2122 2123 static const struct urtwn_txpwr rtl8188ru_txagc[] = { 2124 { { /* Chain 0. */ 2125 { /* Group 0. */ 2126 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2127 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 2128 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 2129 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 2130 }, 2131 { /* Group 1. */ 2132 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2134 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2136 }, 2137 { /* Group 2. */ 2138 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2139 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2140 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2142 } 2143 } } 2144 }; 2145 2146 static const struct urtwn_r88e_txpwr rtl8188eu_txagc[] = { 2147 { { /* Chain 0. */ 2148 { /* Group 0. */ 2149 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2150 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2152 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2153 }, 2154 { /* Group 1. */ 2155 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2156 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2158 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2159 }, 2160 { /* Group 2. */ 2161 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2162 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2163 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2164 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2165 }, 2166 { /* Group 3. */ 2167 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2168 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2169 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2171 }, 2172 { /* Group 4. */ 2173 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2174 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2177 }, 2178 { /* Group 5. */ 2179 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2183 } 2184 } } 2185 }; 2186