1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
2
3 /*-
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34 /*-
35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
36 *
37 * Permission to use, copy, modify, and distribute this software for any
38 * purpose with or without fee is hereby granted, provided that the above
39 * copyright notice and this permission notice appear in all copies.
40 *
41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
48 */
49
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
52
53 /*
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
56 * References:
57 * The XaQti XMAC II datasheet,
58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
60 *
61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
64 *
65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
66 *
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
70 */
71 /*
72 * The SysKonnect gigabit ethernet adapters consist of two main
73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75 * components and a PHY while the GEnesis controller provides a PCI
76 * interface with DMA support. Each card may have between 512K and
77 * 2MB of SRAM on board depending on the configuration.
78 *
79 * The SysKonnect GEnesis controller can have either one or two XMAC
80 * chips connected to it, allowing single or dual port NIC configurations.
81 * SysKonnect has the distinction of being the only vendor on the market
82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84 * XMAC registers. This driver takes advantage of these features to allow
85 * both XMACs to operate as independent interfaces.
86 */
87
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/bus.h>
91 #include <sys/endian.h>
92 #include <sys/mbuf.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/queue.h>
99 #include <sys/sysctl.h>
100
101 #include <net/bpf.h>
102 #include <net/ethernet.h>
103 #include <net/if.h>
104 #include <net/if_var.h>
105 #include <net/if_arp.h>
106 #include <net/if_dl.h>
107 #include <net/if_media.h>
108 #include <net/if_types.h>
109 #include <net/if_vlan_var.h>
110
111 #include <netinet/in.h>
112 #include <netinet/in_systm.h>
113 #include <netinet/ip.h>
114
115 #include <machine/bus.h>
116 #include <machine/in_cksum.h>
117 #include <machine/resource.h>
118 #include <sys/rman.h>
119
120 #include <dev/mii/mii.h>
121 #include <dev/mii/miivar.h>
122 #include <dev/mii/brgphyreg.h>
123
124 #include <dev/pci/pcireg.h>
125 #include <dev/pci/pcivar.h>
126
127 #if 0
128 #define SK_USEIOSPACE
129 #endif
130
131 #include <dev/sk/if_skreg.h>
132 #include <dev/sk/xmaciireg.h>
133 #include <dev/sk/yukonreg.h>
134
135 MODULE_DEPEND(sk, pci, 1, 1, 1);
136 MODULE_DEPEND(sk, ether, 1, 1, 1);
137 MODULE_DEPEND(sk, miibus, 1, 1, 1);
138
139 /* "device miibus" required. See GENERIC if you get errors here. */
140 #include "miibus_if.h"
141
142 static const struct sk_type sk_devs[] = {
143 {
144 VENDORID_SK,
145 DEVICEID_SK_V1,
146 "SysKonnect Gigabit Ethernet (V1.0)"
147 },
148 {
149 VENDORID_SK,
150 DEVICEID_SK_V2,
151 "SysKonnect Gigabit Ethernet (V2.0)"
152 },
153 {
154 VENDORID_MARVELL,
155 DEVICEID_SK_V2,
156 "Marvell Gigabit Ethernet"
157 },
158 {
159 VENDORID_MARVELL,
160 DEVICEID_BELKIN_5005,
161 "Belkin F5D5005 Gigabit Ethernet"
162 },
163 {
164 VENDORID_3COM,
165 DEVICEID_3COM_3C940,
166 "3Com 3C940 Gigabit Ethernet"
167 },
168 {
169 VENDORID_LINKSYS,
170 DEVICEID_LINKSYS_EG1032,
171 "Linksys EG1032 Gigabit Ethernet"
172 },
173 {
174 VENDORID_DLINK,
175 DEVICEID_DLINK_DGE530T_A1,
176 "D-Link DGE-530T Gigabit Ethernet"
177 },
178 {
179 VENDORID_DLINK,
180 DEVICEID_DLINK_DGE530T_B1,
181 "D-Link DGE-530T Gigabit Ethernet"
182 },
183 { 0, 0, NULL }
184 };
185
186 static int skc_probe(device_t);
187 static int skc_attach(device_t);
188 static int skc_detach(device_t);
189 static int skc_shutdown(device_t);
190 static int skc_suspend(device_t);
191 static int skc_resume(device_t);
192 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
193 static int sk_detach(device_t);
194 static int sk_probe(device_t);
195 static int sk_attach(device_t);
196 static void sk_tick(void *);
197 static void sk_yukon_tick(void *);
198 static void sk_intr(void *);
199 static void sk_intr_xmac(struct sk_if_softc *);
200 static void sk_intr_bcom(struct sk_if_softc *);
201 static void sk_intr_yukon(struct sk_if_softc *);
202 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
203 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
204 static void sk_rxeof(struct sk_if_softc *);
205 static void sk_jumbo_rxeof(struct sk_if_softc *);
206 static void sk_txeof(struct sk_if_softc *);
207 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
208 static int sk_encap(struct sk_if_softc *, struct mbuf **);
209 static void sk_start(struct ifnet *);
210 static void sk_start_locked(struct ifnet *);
211 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
212 static void sk_init(void *);
213 static void sk_init_locked(struct sk_if_softc *);
214 static void sk_init_xmac(struct sk_if_softc *);
215 static void sk_init_yukon(struct sk_if_softc *);
216 static void sk_stop(struct sk_if_softc *);
217 static void sk_watchdog(void *);
218 static int sk_ifmedia_upd(struct ifnet *);
219 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
220 static void sk_reset(struct sk_softc *);
221 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
222 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
223 static int sk_newbuf(struct sk_if_softc *, int);
224 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
225 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
226 static int sk_dma_alloc(struct sk_if_softc *);
227 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
228 static void sk_dma_free(struct sk_if_softc *);
229 static void sk_dma_jumbo_free(struct sk_if_softc *);
230 static int sk_init_rx_ring(struct sk_if_softc *);
231 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
232 static void sk_init_tx_ring(struct sk_if_softc *);
233 static u_int32_t sk_win_read_4(struct sk_softc *, int);
234 static u_int16_t sk_win_read_2(struct sk_softc *, int);
235 static u_int8_t sk_win_read_1(struct sk_softc *, int);
236 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
237 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
238 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
239
240 static int sk_miibus_readreg(device_t, int, int);
241 static int sk_miibus_writereg(device_t, int, int, int);
242 static void sk_miibus_statchg(device_t);
243
244 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
245 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
246 int);
247 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
248
249 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
250 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
251 int);
252 static void sk_marv_miibus_statchg(struct sk_if_softc *);
253
254 static uint32_t sk_xmchash(const uint8_t *);
255 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
256 static void sk_rxfilter(struct sk_if_softc *);
257 static void sk_rxfilter_genesis(struct sk_if_softc *);
258 static void sk_rxfilter_yukon(struct sk_if_softc *);
259
260 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
261 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
262
263 /* Tunables. */
264 static int jumbo_disable = 0;
265 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
266
267 /*
268 * It seems that SK-NET GENESIS supports very simple checksum offload
269 * capability for Tx and I believe it can generate 0 checksum value for
270 * UDP packets in Tx as the hardware can't differenciate UDP packets from
271 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
272 * means sender didn't perforam checksum computation. For the safety I
273 * disabled UDP checksum offload capability at the moment. Alternatively
274 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
275 * offload routine.
276 */
277 #define SK_CSUM_FEATURES (CSUM_TCP)
278
279 /*
280 * Note that we have newbus methods for both the GEnesis controller
281 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
282 * the miibus code is a child of the XMACs. We need to do it this way
283 * so that the miibus drivers can access the PHY registers on the
284 * right PHY. It's not quite what I had in mind, but it's the only
285 * design that achieves the desired effect.
286 */
287 static device_method_t skc_methods[] = {
288 /* Device interface */
289 DEVMETHOD(device_probe, skc_probe),
290 DEVMETHOD(device_attach, skc_attach),
291 DEVMETHOD(device_detach, skc_detach),
292 DEVMETHOD(device_suspend, skc_suspend),
293 DEVMETHOD(device_resume, skc_resume),
294 DEVMETHOD(device_shutdown, skc_shutdown),
295
296 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag),
297
298 DEVMETHOD_END
299 };
300
301 static driver_t skc_driver = {
302 "skc",
303 skc_methods,
304 sizeof(struct sk_softc)
305 };
306
307 static devclass_t skc_devclass;
308
309 static device_method_t sk_methods[] = {
310 /* Device interface */
311 DEVMETHOD(device_probe, sk_probe),
312 DEVMETHOD(device_attach, sk_attach),
313 DEVMETHOD(device_detach, sk_detach),
314 DEVMETHOD(device_shutdown, bus_generic_shutdown),
315
316 /* MII interface */
317 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
318 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
319 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
320
321 DEVMETHOD_END
322 };
323
324 static driver_t sk_driver = {
325 "sk",
326 sk_methods,
327 sizeof(struct sk_if_softc)
328 };
329
330 static devclass_t sk_devclass;
331
332 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL);
333 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL);
334 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
335
336 static struct resource_spec sk_res_spec_io[] = {
337 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
338 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
339 { -1, 0, 0 }
340 };
341
342 static struct resource_spec sk_res_spec_mem[] = {
343 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
344 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
345 { -1, 0, 0 }
346 };
347
348 #define SK_SETBIT(sc, reg, x) \
349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
350
351 #define SK_CLRBIT(sc, reg, x) \
352 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
353
354 #define SK_WIN_SETBIT_4(sc, reg, x) \
355 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
356
357 #define SK_WIN_CLRBIT_4(sc, reg, x) \
358 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
359
360 #define SK_WIN_SETBIT_2(sc, reg, x) \
361 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
362
363 #define SK_WIN_CLRBIT_2(sc, reg, x) \
364 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
365
366 static u_int32_t
sk_win_read_4(sc,reg)367 sk_win_read_4(sc, reg)
368 struct sk_softc *sc;
369 int reg;
370 {
371 #ifdef SK_USEIOSPACE
372 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
373 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
374 #else
375 return(CSR_READ_4(sc, reg));
376 #endif
377 }
378
379 static u_int16_t
sk_win_read_2(sc,reg)380 sk_win_read_2(sc, reg)
381 struct sk_softc *sc;
382 int reg;
383 {
384 #ifdef SK_USEIOSPACE
385 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
386 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
387 #else
388 return(CSR_READ_2(sc, reg));
389 #endif
390 }
391
392 static u_int8_t
sk_win_read_1(sc,reg)393 sk_win_read_1(sc, reg)
394 struct sk_softc *sc;
395 int reg;
396 {
397 #ifdef SK_USEIOSPACE
398 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
399 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
400 #else
401 return(CSR_READ_1(sc, reg));
402 #endif
403 }
404
405 static void
sk_win_write_4(sc,reg,val)406 sk_win_write_4(sc, reg, val)
407 struct sk_softc *sc;
408 int reg;
409 u_int32_t val;
410 {
411 #ifdef SK_USEIOSPACE
412 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
413 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
414 #else
415 CSR_WRITE_4(sc, reg, val);
416 #endif
417 return;
418 }
419
420 static void
sk_win_write_2(sc,reg,val)421 sk_win_write_2(sc, reg, val)
422 struct sk_softc *sc;
423 int reg;
424 u_int32_t val;
425 {
426 #ifdef SK_USEIOSPACE
427 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
428 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
429 #else
430 CSR_WRITE_2(sc, reg, val);
431 #endif
432 return;
433 }
434
435 static void
sk_win_write_1(sc,reg,val)436 sk_win_write_1(sc, reg, val)
437 struct sk_softc *sc;
438 int reg;
439 u_int32_t val;
440 {
441 #ifdef SK_USEIOSPACE
442 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
443 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
444 #else
445 CSR_WRITE_1(sc, reg, val);
446 #endif
447 return;
448 }
449
450 static int
sk_miibus_readreg(dev,phy,reg)451 sk_miibus_readreg(dev, phy, reg)
452 device_t dev;
453 int phy, reg;
454 {
455 struct sk_if_softc *sc_if;
456 int v;
457
458 sc_if = device_get_softc(dev);
459
460 SK_IF_MII_LOCK(sc_if);
461 switch(sc_if->sk_softc->sk_type) {
462 case SK_GENESIS:
463 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
464 break;
465 case SK_YUKON:
466 case SK_YUKON_LITE:
467 case SK_YUKON_LP:
468 v = sk_marv_miibus_readreg(sc_if, phy, reg);
469 break;
470 default:
471 v = 0;
472 break;
473 }
474 SK_IF_MII_UNLOCK(sc_if);
475
476 return (v);
477 }
478
479 static int
sk_miibus_writereg(dev,phy,reg,val)480 sk_miibus_writereg(dev, phy, reg, val)
481 device_t dev;
482 int phy, reg, val;
483 {
484 struct sk_if_softc *sc_if;
485 int v;
486
487 sc_if = device_get_softc(dev);
488
489 SK_IF_MII_LOCK(sc_if);
490 switch(sc_if->sk_softc->sk_type) {
491 case SK_GENESIS:
492 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
493 break;
494 case SK_YUKON:
495 case SK_YUKON_LITE:
496 case SK_YUKON_LP:
497 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
498 break;
499 default:
500 v = 0;
501 break;
502 }
503 SK_IF_MII_UNLOCK(sc_if);
504
505 return (v);
506 }
507
508 static void
sk_miibus_statchg(dev)509 sk_miibus_statchg(dev)
510 device_t dev;
511 {
512 struct sk_if_softc *sc_if;
513
514 sc_if = device_get_softc(dev);
515
516 SK_IF_MII_LOCK(sc_if);
517 switch(sc_if->sk_softc->sk_type) {
518 case SK_GENESIS:
519 sk_xmac_miibus_statchg(sc_if);
520 break;
521 case SK_YUKON:
522 case SK_YUKON_LITE:
523 case SK_YUKON_LP:
524 sk_marv_miibus_statchg(sc_if);
525 break;
526 }
527 SK_IF_MII_UNLOCK(sc_if);
528
529 return;
530 }
531
532 static int
sk_xmac_miibus_readreg(sc_if,phy,reg)533 sk_xmac_miibus_readreg(sc_if, phy, reg)
534 struct sk_if_softc *sc_if;
535 int phy, reg;
536 {
537 int i;
538
539 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
540 SK_XM_READ_2(sc_if, XM_PHY_DATA);
541 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
542 for (i = 0; i < SK_TIMEOUT; i++) {
543 DELAY(1);
544 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
545 XM_MMUCMD_PHYDATARDY)
546 break;
547 }
548
549 if (i == SK_TIMEOUT) {
550 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
551 return(0);
552 }
553 }
554 DELAY(1);
555 i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
556
557 return(i);
558 }
559
560 static int
sk_xmac_miibus_writereg(sc_if,phy,reg,val)561 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
562 struct sk_if_softc *sc_if;
563 int phy, reg, val;
564 {
565 int i;
566
567 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
568 for (i = 0; i < SK_TIMEOUT; i++) {
569 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
570 break;
571 }
572
573 if (i == SK_TIMEOUT) {
574 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
575 return (ETIMEDOUT);
576 }
577
578 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
579 for (i = 0; i < SK_TIMEOUT; i++) {
580 DELAY(1);
581 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
582 break;
583 }
584 if (i == SK_TIMEOUT)
585 if_printf(sc_if->sk_ifp, "phy write timed out\n");
586
587 return(0);
588 }
589
590 static void
sk_xmac_miibus_statchg(sc_if)591 sk_xmac_miibus_statchg(sc_if)
592 struct sk_if_softc *sc_if;
593 {
594 struct mii_data *mii;
595
596 mii = device_get_softc(sc_if->sk_miibus);
597
598 /*
599 * If this is a GMII PHY, manually set the XMAC's
600 * duplex mode accordingly.
601 */
602 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
603 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
604 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
605 } else {
606 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
607 }
608 }
609 }
610
611 static int
sk_marv_miibus_readreg(sc_if,phy,reg)612 sk_marv_miibus_readreg(sc_if, phy, reg)
613 struct sk_if_softc *sc_if;
614 int phy, reg;
615 {
616 u_int16_t val;
617 int i;
618
619 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
620 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
621 return(0);
622 }
623
624 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
625 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
626
627 for (i = 0; i < SK_TIMEOUT; i++) {
628 DELAY(1);
629 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
630 if (val & YU_SMICR_READ_VALID)
631 break;
632 }
633
634 if (i == SK_TIMEOUT) {
635 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
636 return(0);
637 }
638
639 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
640
641 return(val);
642 }
643
644 static int
sk_marv_miibus_writereg(sc_if,phy,reg,val)645 sk_marv_miibus_writereg(sc_if, phy, reg, val)
646 struct sk_if_softc *sc_if;
647 int phy, reg, val;
648 {
649 int i;
650
651 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
652 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
653 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
654
655 for (i = 0; i < SK_TIMEOUT; i++) {
656 DELAY(1);
657 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
658 break;
659 }
660 if (i == SK_TIMEOUT)
661 if_printf(sc_if->sk_ifp, "phy write timeout\n");
662
663 return(0);
664 }
665
666 static void
sk_marv_miibus_statchg(sc_if)667 sk_marv_miibus_statchg(sc_if)
668 struct sk_if_softc *sc_if;
669 {
670 return;
671 }
672
673 #define HASH_BITS 6
674
675 static u_int32_t
sk_xmchash(addr)676 sk_xmchash(addr)
677 const uint8_t *addr;
678 {
679 uint32_t crc;
680
681 /* Compute CRC for the address value. */
682 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
683
684 return (~crc & ((1 << HASH_BITS) - 1));
685 }
686
687 static void
sk_setfilt(sc_if,addr,slot)688 sk_setfilt(sc_if, addr, slot)
689 struct sk_if_softc *sc_if;
690 u_int16_t *addr;
691 int slot;
692 {
693 int base;
694
695 base = XM_RXFILT_ENTRY(slot);
696
697 SK_XM_WRITE_2(sc_if, base, addr[0]);
698 SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
699 SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
700
701 return;
702 }
703
704 static void
sk_rxfilter(sc_if)705 sk_rxfilter(sc_if)
706 struct sk_if_softc *sc_if;
707 {
708 struct sk_softc *sc;
709
710 SK_IF_LOCK_ASSERT(sc_if);
711
712 sc = sc_if->sk_softc;
713 if (sc->sk_type == SK_GENESIS)
714 sk_rxfilter_genesis(sc_if);
715 else
716 sk_rxfilter_yukon(sc_if);
717 }
718
719 static void
sk_rxfilter_genesis(sc_if)720 sk_rxfilter_genesis(sc_if)
721 struct sk_if_softc *sc_if;
722 {
723 struct ifnet *ifp = sc_if->sk_ifp;
724 u_int32_t hashes[2] = { 0, 0 }, mode;
725 int h = 0, i;
726 struct ifmultiaddr *ifma;
727 u_int16_t dummy[] = { 0, 0, 0 };
728 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2];
729
730 SK_IF_LOCK_ASSERT(sc_if);
731
732 mode = SK_XM_READ_4(sc_if, XM_MODE);
733 mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
734 XM_MODE_RX_USE_PERFECT);
735 /* First, zot all the existing perfect filters. */
736 for (i = 1; i < XM_RXFILT_MAX; i++)
737 sk_setfilt(sc_if, dummy, i);
738
739 /* Now program new ones. */
740 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
741 if (ifp->if_flags & IFF_ALLMULTI)
742 mode |= XM_MODE_RX_USE_HASH;
743 if (ifp->if_flags & IFF_PROMISC)
744 mode |= XM_MODE_RX_PROMISC;
745 hashes[0] = 0xFFFFFFFF;
746 hashes[1] = 0xFFFFFFFF;
747 } else {
748 i = 1;
749 if_maddr_rlock(ifp);
750 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
751 ifma_link) {
752 if (ifma->ifma_addr->sa_family != AF_LINK)
753 continue;
754 /*
755 * Program the first XM_RXFILT_MAX multicast groups
756 * into the perfect filter.
757 */
758 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
759 maddr, ETHER_ADDR_LEN);
760 if (i < XM_RXFILT_MAX) {
761 sk_setfilt(sc_if, maddr, i);
762 mode |= XM_MODE_RX_USE_PERFECT;
763 i++;
764 continue;
765 }
766 h = sk_xmchash((const uint8_t *)maddr);
767 if (h < 32)
768 hashes[0] |= (1 << h);
769 else
770 hashes[1] |= (1 << (h - 32));
771 mode |= XM_MODE_RX_USE_HASH;
772 }
773 if_maddr_runlock(ifp);
774 }
775
776 SK_XM_WRITE_4(sc_if, XM_MODE, mode);
777 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
778 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
779 }
780
781 static void
sk_rxfilter_yukon(sc_if)782 sk_rxfilter_yukon(sc_if)
783 struct sk_if_softc *sc_if;
784 {
785 struct ifnet *ifp;
786 u_int32_t crc, hashes[2] = { 0, 0 }, mode;
787 struct ifmultiaddr *ifma;
788
789 SK_IF_LOCK_ASSERT(sc_if);
790
791 ifp = sc_if->sk_ifp;
792 mode = SK_YU_READ_2(sc_if, YUKON_RCR);
793 if (ifp->if_flags & IFF_PROMISC)
794 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
795 else if (ifp->if_flags & IFF_ALLMULTI) {
796 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
797 hashes[0] = 0xFFFFFFFF;
798 hashes[1] = 0xFFFFFFFF;
799 } else {
800 mode |= YU_RCR_UFLEN;
801 if_maddr_rlock(ifp);
802 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
803 if (ifma->ifma_addr->sa_family != AF_LINK)
804 continue;
805 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
806 ifma->ifma_addr), ETHER_ADDR_LEN);
807 /* Just want the 6 least significant bits. */
808 crc &= 0x3f;
809 /* Set the corresponding bit in the hash table. */
810 hashes[crc >> 5] |= 1 << (crc & 0x1f);
811 }
812 if_maddr_runlock(ifp);
813 if (hashes[0] != 0 || hashes[1] != 0)
814 mode |= YU_RCR_MUFLEN;
815 }
816
817 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
818 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
819 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
820 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
821 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
822 }
823
824 static int
sk_init_rx_ring(sc_if)825 sk_init_rx_ring(sc_if)
826 struct sk_if_softc *sc_if;
827 {
828 struct sk_ring_data *rd;
829 bus_addr_t addr;
830 u_int32_t csum_start;
831 int i;
832
833 sc_if->sk_cdata.sk_rx_cons = 0;
834
835 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 |
836 ETHER_HDR_LEN;
837 rd = &sc_if->sk_rdata;
838 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
839 for (i = 0; i < SK_RX_RING_CNT; i++) {
840 if (sk_newbuf(sc_if, i) != 0)
841 return (ENOBUFS);
842 if (i == (SK_RX_RING_CNT - 1))
843 addr = SK_RX_RING_ADDR(sc_if, 0);
844 else
845 addr = SK_RX_RING_ADDR(sc_if, i + 1);
846 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
847 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
848 }
849
850 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
851 sc_if->sk_cdata.sk_rx_ring_map,
852 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
853
854 return(0);
855 }
856
857 static int
sk_init_jumbo_rx_ring(sc_if)858 sk_init_jumbo_rx_ring(sc_if)
859 struct sk_if_softc *sc_if;
860 {
861 struct sk_ring_data *rd;
862 bus_addr_t addr;
863 u_int32_t csum_start;
864 int i;
865
866 sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
867
868 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
869 ETHER_HDR_LEN;
870 rd = &sc_if->sk_rdata;
871 bzero(rd->sk_jumbo_rx_ring,
872 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
873 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
874 if (sk_jumbo_newbuf(sc_if, i) != 0)
875 return (ENOBUFS);
876 if (i == (SK_JUMBO_RX_RING_CNT - 1))
877 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
878 else
879 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
880 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
881 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
882 }
883
884 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
885 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
886 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
887
888 return (0);
889 }
890
891 static void
sk_init_tx_ring(sc_if)892 sk_init_tx_ring(sc_if)
893 struct sk_if_softc *sc_if;
894 {
895 struct sk_ring_data *rd;
896 struct sk_txdesc *txd;
897 bus_addr_t addr;
898 int i;
899
900 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
901 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
902
903 sc_if->sk_cdata.sk_tx_prod = 0;
904 sc_if->sk_cdata.sk_tx_cons = 0;
905 sc_if->sk_cdata.sk_tx_cnt = 0;
906
907 rd = &sc_if->sk_rdata;
908 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
909 for (i = 0; i < SK_TX_RING_CNT; i++) {
910 if (i == (SK_TX_RING_CNT - 1))
911 addr = SK_TX_RING_ADDR(sc_if, 0);
912 else
913 addr = SK_TX_RING_ADDR(sc_if, i + 1);
914 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
915 txd = &sc_if->sk_cdata.sk_txdesc[i];
916 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
917 }
918
919 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
920 sc_if->sk_cdata.sk_tx_ring_map,
921 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
922 }
923
924 static __inline void
sk_discard_rxbuf(sc_if,idx)925 sk_discard_rxbuf(sc_if, idx)
926 struct sk_if_softc *sc_if;
927 int idx;
928 {
929 struct sk_rx_desc *r;
930 struct sk_rxdesc *rxd;
931 struct mbuf *m;
932
933
934 r = &sc_if->sk_rdata.sk_rx_ring[idx];
935 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
936 m = rxd->rx_m;
937 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
938 }
939
940 static __inline void
sk_discard_jumbo_rxbuf(sc_if,idx)941 sk_discard_jumbo_rxbuf(sc_if, idx)
942 struct sk_if_softc *sc_if;
943 int idx;
944 {
945 struct sk_rx_desc *r;
946 struct sk_rxdesc *rxd;
947 struct mbuf *m;
948
949 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
950 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
951 m = rxd->rx_m;
952 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
953 }
954
955 static int
sk_newbuf(sc_if,idx)956 sk_newbuf(sc_if, idx)
957 struct sk_if_softc *sc_if;
958 int idx;
959 {
960 struct sk_rx_desc *r;
961 struct sk_rxdesc *rxd;
962 struct mbuf *m;
963 bus_dma_segment_t segs[1];
964 bus_dmamap_t map;
965 int nsegs;
966
967 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
968 if (m == NULL)
969 return (ENOBUFS);
970 m->m_len = m->m_pkthdr.len = MCLBYTES;
971 m_adj(m, ETHER_ALIGN);
972
973 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
974 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
975 m_freem(m);
976 return (ENOBUFS);
977 }
978 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
979
980 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
981 if (rxd->rx_m != NULL) {
982 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
983 BUS_DMASYNC_POSTREAD);
984 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
985 }
986 map = rxd->rx_dmamap;
987 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
988 sc_if->sk_cdata.sk_rx_sparemap = map;
989 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
990 BUS_DMASYNC_PREREAD);
991 rxd->rx_m = m;
992 r = &sc_if->sk_rdata.sk_rx_ring[idx];
993 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
994 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
995 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
996
997 return (0);
998 }
999
1000 static int
sk_jumbo_newbuf(sc_if,idx)1001 sk_jumbo_newbuf(sc_if, idx)
1002 struct sk_if_softc *sc_if;
1003 int idx;
1004 {
1005 struct sk_rx_desc *r;
1006 struct sk_rxdesc *rxd;
1007 struct mbuf *m;
1008 bus_dma_segment_t segs[1];
1009 bus_dmamap_t map;
1010 int nsegs;
1011
1012 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1013 if (m == NULL)
1014 return (ENOBUFS);
1015 m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1016 /*
1017 * Adjust alignment so packet payload begins on a
1018 * longword boundary. Mandatory for Alpha, useful on
1019 * x86 too.
1020 */
1021 m_adj(m, ETHER_ALIGN);
1022
1023 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1024 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1025 m_freem(m);
1026 return (ENOBUFS);
1027 }
1028 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1029
1030 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1031 if (rxd->rx_m != NULL) {
1032 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1033 BUS_DMASYNC_POSTREAD);
1034 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1035 rxd->rx_dmamap);
1036 }
1037 map = rxd->rx_dmamap;
1038 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1039 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1040 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1041 BUS_DMASYNC_PREREAD);
1042 rxd->rx_m = m;
1043 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1044 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1045 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1046 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1047
1048 return (0);
1049 }
1050
1051 /*
1052 * Set media options.
1053 */
1054 static int
sk_ifmedia_upd(ifp)1055 sk_ifmedia_upd(ifp)
1056 struct ifnet *ifp;
1057 {
1058 struct sk_if_softc *sc_if = ifp->if_softc;
1059 struct mii_data *mii;
1060
1061 mii = device_get_softc(sc_if->sk_miibus);
1062 sk_init(sc_if);
1063 mii_mediachg(mii);
1064
1065 return(0);
1066 }
1067
1068 /*
1069 * Report current media status.
1070 */
1071 static void
sk_ifmedia_sts(ifp,ifmr)1072 sk_ifmedia_sts(ifp, ifmr)
1073 struct ifnet *ifp;
1074 struct ifmediareq *ifmr;
1075 {
1076 struct sk_if_softc *sc_if;
1077 struct mii_data *mii;
1078
1079 sc_if = ifp->if_softc;
1080 mii = device_get_softc(sc_if->sk_miibus);
1081
1082 mii_pollstat(mii);
1083 ifmr->ifm_active = mii->mii_media_active;
1084 ifmr->ifm_status = mii->mii_media_status;
1085
1086 return;
1087 }
1088
1089 static int
sk_ioctl(ifp,command,data)1090 sk_ioctl(ifp, command, data)
1091 struct ifnet *ifp;
1092 u_long command;
1093 caddr_t data;
1094 {
1095 struct sk_if_softc *sc_if = ifp->if_softc;
1096 struct ifreq *ifr = (struct ifreq *) data;
1097 int error, mask;
1098 struct mii_data *mii;
1099
1100 error = 0;
1101 switch(command) {
1102 case SIOCSIFMTU:
1103 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1104 error = EINVAL;
1105 else if (ifp->if_mtu != ifr->ifr_mtu) {
1106 if (sc_if->sk_jumbo_disable != 0 &&
1107 ifr->ifr_mtu > SK_MAX_FRAMELEN)
1108 error = EINVAL;
1109 else {
1110 SK_IF_LOCK(sc_if);
1111 ifp->if_mtu = ifr->ifr_mtu;
1112 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1113 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1114 sk_init_locked(sc_if);
1115 }
1116 SK_IF_UNLOCK(sc_if);
1117 }
1118 }
1119 break;
1120 case SIOCSIFFLAGS:
1121 SK_IF_LOCK(sc_if);
1122 if (ifp->if_flags & IFF_UP) {
1123 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1124 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1125 & (IFF_PROMISC | IFF_ALLMULTI))
1126 sk_rxfilter(sc_if);
1127 } else
1128 sk_init_locked(sc_if);
1129 } else {
1130 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1131 sk_stop(sc_if);
1132 }
1133 sc_if->sk_if_flags = ifp->if_flags;
1134 SK_IF_UNLOCK(sc_if);
1135 break;
1136 case SIOCADDMULTI:
1137 case SIOCDELMULTI:
1138 SK_IF_LOCK(sc_if);
1139 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1140 sk_rxfilter(sc_if);
1141 SK_IF_UNLOCK(sc_if);
1142 break;
1143 case SIOCGIFMEDIA:
1144 case SIOCSIFMEDIA:
1145 mii = device_get_softc(sc_if->sk_miibus);
1146 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1147 break;
1148 case SIOCSIFCAP:
1149 SK_IF_LOCK(sc_if);
1150 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1151 SK_IF_UNLOCK(sc_if);
1152 break;
1153 }
1154 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1155 if ((mask & IFCAP_TXCSUM) != 0 &&
1156 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1157 ifp->if_capenable ^= IFCAP_TXCSUM;
1158 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1159 ifp->if_hwassist |= SK_CSUM_FEATURES;
1160 else
1161 ifp->if_hwassist &= ~SK_CSUM_FEATURES;
1162 }
1163 if ((mask & IFCAP_RXCSUM) != 0 &&
1164 (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
1165 ifp->if_capenable ^= IFCAP_RXCSUM;
1166 SK_IF_UNLOCK(sc_if);
1167 break;
1168 default:
1169 error = ether_ioctl(ifp, command, data);
1170 break;
1171 }
1172
1173 return (error);
1174 }
1175
1176 /*
1177 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1178 * IDs against our list and return a device name if we find a match.
1179 */
1180 static int
skc_probe(dev)1181 skc_probe(dev)
1182 device_t dev;
1183 {
1184 const struct sk_type *t = sk_devs;
1185
1186 while(t->sk_name != NULL) {
1187 if ((pci_get_vendor(dev) == t->sk_vid) &&
1188 (pci_get_device(dev) == t->sk_did)) {
1189 /*
1190 * Only attach to rev. 2 of the Linksys EG1032 adapter.
1191 * Rev. 3 is supported by re(4).
1192 */
1193 if ((t->sk_vid == VENDORID_LINKSYS) &&
1194 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1195 (pci_get_subdevice(dev) !=
1196 SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1197 t++;
1198 continue;
1199 }
1200 device_set_desc(dev, t->sk_name);
1201 return (BUS_PROBE_DEFAULT);
1202 }
1203 t++;
1204 }
1205
1206 return(ENXIO);
1207 }
1208
1209 /*
1210 * Force the GEnesis into reset, then bring it out of reset.
1211 */
1212 static void
sk_reset(sc)1213 sk_reset(sc)
1214 struct sk_softc *sc;
1215 {
1216
1217 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1218 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1219 if (SK_YUKON_FAMILY(sc->sk_type))
1220 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1221
1222 DELAY(1000);
1223 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1224 DELAY(2);
1225 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1226 if (SK_YUKON_FAMILY(sc->sk_type))
1227 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1228
1229 if (sc->sk_type == SK_GENESIS) {
1230 /* Configure packet arbiter */
1231 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1232 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1233 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1234 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1235 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1236 }
1237
1238 /* Enable RAM interface */
1239 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1240
1241 /*
1242 * Configure interrupt moderation. The moderation timer
1243 * defers interrupts specified in the interrupt moderation
1244 * timer mask based on the timeout specified in the interrupt
1245 * moderation timer init register. Each bit in the timer
1246 * register represents one tick, so to specify a timeout in
1247 * microseconds, we have to multiply by the correct number of
1248 * ticks-per-microsecond.
1249 */
1250 switch (sc->sk_type) {
1251 case SK_GENESIS:
1252 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1253 break;
1254 default:
1255 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1256 break;
1257 }
1258 if (bootverbose)
1259 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1260 sc->sk_int_mod);
1261 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1262 sc->sk_int_ticks));
1263 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1264 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1265 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1266
1267 return;
1268 }
1269
1270 static int
sk_probe(dev)1271 sk_probe(dev)
1272 device_t dev;
1273 {
1274 struct sk_softc *sc;
1275
1276 sc = device_get_softc(device_get_parent(dev));
1277
1278 /*
1279 * Not much to do here. We always know there will be
1280 * at least one XMAC present, and if there are two,
1281 * skc_attach() will create a second device instance
1282 * for us.
1283 */
1284 switch (sc->sk_type) {
1285 case SK_GENESIS:
1286 device_set_desc(dev, "XaQti Corp. XMAC II");
1287 break;
1288 case SK_YUKON:
1289 case SK_YUKON_LITE:
1290 case SK_YUKON_LP:
1291 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1292 break;
1293 }
1294
1295 return (BUS_PROBE_DEFAULT);
1296 }
1297
1298 /*
1299 * Each XMAC chip is attached as a separate logical IP interface.
1300 * Single port cards will have only one logical interface of course.
1301 */
1302 static int
sk_attach(dev)1303 sk_attach(dev)
1304 device_t dev;
1305 {
1306 struct sk_softc *sc;
1307 struct sk_if_softc *sc_if;
1308 struct ifnet *ifp;
1309 u_int32_t r;
1310 int error, i, phy, port;
1311 u_char eaddr[6];
1312 u_char inv_mac[] = {0, 0, 0, 0, 0, 0};
1313
1314 if (dev == NULL)
1315 return(EINVAL);
1316
1317 error = 0;
1318 sc_if = device_get_softc(dev);
1319 sc = device_get_softc(device_get_parent(dev));
1320 port = *(int *)device_get_ivars(dev);
1321
1322 sc_if->sk_if_dev = dev;
1323 sc_if->sk_port = port;
1324 sc_if->sk_softc = sc;
1325 sc->sk_if[port] = sc_if;
1326 if (port == SK_PORT_A)
1327 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1328 if (port == SK_PORT_B)
1329 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1330
1331 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1332 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1333
1334 if (sk_dma_alloc(sc_if) != 0) {
1335 error = ENOMEM;
1336 goto fail;
1337 }
1338 sk_dma_jumbo_alloc(sc_if);
1339
1340 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1341 if (ifp == NULL) {
1342 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1343 error = ENOSPC;
1344 goto fail;
1345 }
1346 ifp->if_softc = sc_if;
1347 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1348 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1349 /*
1350 * SK_GENESIS has a bug in checksum offload - From linux.
1351 */
1352 if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1353 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
1354 ifp->if_hwassist = 0;
1355 } else {
1356 ifp->if_capabilities = 0;
1357 ifp->if_hwassist = 0;
1358 }
1359 ifp->if_capenable = ifp->if_capabilities;
1360 /*
1361 * Some revision of Yukon controller generates corrupted
1362 * frame when TX checksum offloading is enabled. The
1363 * frame has a valid checksum value so payload might be
1364 * modified during TX checksum calculation. Disable TX
1365 * checksum offloading but give users chance to enable it
1366 * when they know their controller works without problems
1367 * with TX checksum offloading.
1368 */
1369 ifp->if_capenable &= ~IFCAP_TXCSUM;
1370 ifp->if_ioctl = sk_ioctl;
1371 ifp->if_start = sk_start;
1372 ifp->if_init = sk_init;
1373 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1374 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1375 IFQ_SET_READY(&ifp->if_snd);
1376
1377 /*
1378 * Get station address for this interface. Note that
1379 * dual port cards actually come with three station
1380 * addresses: one for each port, plus an extra. The
1381 * extra one is used by the SysKonnect driver software
1382 * as a 'virtual' station address for when both ports
1383 * are operating in failover mode. Currently we don't
1384 * use this extra address.
1385 */
1386 SK_IF_LOCK(sc_if);
1387 for (i = 0; i < ETHER_ADDR_LEN; i++)
1388 eaddr[i] =
1389 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1390
1391 /* Verify whether the station address is invalid or not. */
1392 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1393 device_printf(sc_if->sk_if_dev,
1394 "Generating random ethernet address\n");
1395 r = arc4random();
1396 /*
1397 * Set OUI to convenient locally assigned address. 'b'
1398 * is 0x62, which has the locally assigned bit set, and
1399 * the broadcast/multicast bit clear.
1400 */
1401 eaddr[0] = 'b';
1402 eaddr[1] = 's';
1403 eaddr[2] = 'd';
1404 eaddr[3] = (r >> 16) & 0xff;
1405 eaddr[4] = (r >> 8) & 0xff;
1406 eaddr[5] = (r >> 0) & 0xff;
1407 }
1408 /*
1409 * Set up RAM buffer addresses. The NIC will have a certain
1410 * amount of SRAM on it, somewhere between 512K and 2MB. We
1411 * need to divide this up a) between the transmitter and
1412 * receiver and b) between the two XMACs, if this is a
1413 * dual port NIC. Our algotithm is to divide up the memory
1414 * evenly so that everyone gets a fair share.
1415 *
1416 * Just to be contrary, Yukon2 appears to have separate memory
1417 * for each MAC.
1418 */
1419 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1420 u_int32_t chunk, val;
1421
1422 chunk = sc->sk_ramsize / 2;
1423 val = sc->sk_rboff / sizeof(u_int64_t);
1424 sc_if->sk_rx_ramstart = val;
1425 val += (chunk / sizeof(u_int64_t));
1426 sc_if->sk_rx_ramend = val - 1;
1427 sc_if->sk_tx_ramstart = val;
1428 val += (chunk / sizeof(u_int64_t));
1429 sc_if->sk_tx_ramend = val - 1;
1430 } else {
1431 u_int32_t chunk, val;
1432
1433 chunk = sc->sk_ramsize / 4;
1434 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1435 sizeof(u_int64_t);
1436 sc_if->sk_rx_ramstart = val;
1437 val += (chunk / sizeof(u_int64_t));
1438 sc_if->sk_rx_ramend = val - 1;
1439 sc_if->sk_tx_ramstart = val;
1440 val += (chunk / sizeof(u_int64_t));
1441 sc_if->sk_tx_ramend = val - 1;
1442 }
1443
1444 /* Read and save PHY type and set PHY address */
1445 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1446 if (!SK_YUKON_FAMILY(sc->sk_type)) {
1447 switch(sc_if->sk_phytype) {
1448 case SK_PHYTYPE_XMAC:
1449 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1450 break;
1451 case SK_PHYTYPE_BCOM:
1452 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1453 break;
1454 default:
1455 device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1456 sc_if->sk_phytype);
1457 error = ENODEV;
1458 SK_IF_UNLOCK(sc_if);
1459 goto fail;
1460 }
1461 } else {
1462 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1463 sc->sk_pmd != 'S') {
1464 /* not initialized, punt */
1465 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1466 sc->sk_coppertype = 1;
1467 }
1468
1469 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1470
1471 if (!(sc->sk_coppertype))
1472 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1473 }
1474
1475 /*
1476 * Call MI attach routine. Can't hold locks when calling into ether_*.
1477 */
1478 SK_IF_UNLOCK(sc_if);
1479 ether_ifattach(ifp, eaddr);
1480 SK_IF_LOCK(sc_if);
1481
1482 /*
1483 * The hardware should be ready for VLAN_MTU by default:
1484 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1485 * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1486 *
1487 */
1488 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1489 ifp->if_capenable |= IFCAP_VLAN_MTU;
1490 /*
1491 * Tell the upper layer(s) we support long frames.
1492 * Must appear after the call to ether_ifattach() because
1493 * ether_ifattach() sets ifi_hdrlen to the default value.
1494 */
1495 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1496
1497 /*
1498 * Do miibus setup.
1499 */
1500 phy = MII_PHY_ANY;
1501 switch (sc->sk_type) {
1502 case SK_GENESIS:
1503 sk_init_xmac(sc_if);
1504 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1505 phy = 0;
1506 break;
1507 case SK_YUKON:
1508 case SK_YUKON_LITE:
1509 case SK_YUKON_LP:
1510 sk_init_yukon(sc_if);
1511 phy = 0;
1512 break;
1513 }
1514
1515 SK_IF_UNLOCK(sc_if);
1516 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1517 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1518 if (error != 0) {
1519 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1520 ether_ifdetach(ifp);
1521 goto fail;
1522 }
1523
1524 fail:
1525 if (error) {
1526 /* Access should be ok even though lock has been dropped */
1527 sc->sk_if[port] = NULL;
1528 sk_detach(dev);
1529 }
1530
1531 return(error);
1532 }
1533
1534 /*
1535 * Attach the interface. Allocate softc structures, do ifmedia
1536 * setup and ethernet/BPF attach.
1537 */
1538 static int
skc_attach(dev)1539 skc_attach(dev)
1540 device_t dev;
1541 {
1542 struct sk_softc *sc;
1543 int error = 0, *port;
1544 uint8_t skrs;
1545 const char *pname = NULL;
1546 char *revstr;
1547
1548 sc = device_get_softc(dev);
1549 sc->sk_dev = dev;
1550
1551 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1552 MTX_DEF);
1553 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1554 /*
1555 * Map control/status registers.
1556 */
1557 pci_enable_busmaster(dev);
1558
1559 /* Allocate resources */
1560 #ifdef SK_USEIOSPACE
1561 sc->sk_res_spec = sk_res_spec_io;
1562 #else
1563 sc->sk_res_spec = sk_res_spec_mem;
1564 #endif
1565 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1566 if (error) {
1567 if (sc->sk_res_spec == sk_res_spec_mem)
1568 sc->sk_res_spec = sk_res_spec_io;
1569 else
1570 sc->sk_res_spec = sk_res_spec_mem;
1571 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1572 if (error) {
1573 device_printf(dev, "couldn't allocate %s resources\n",
1574 sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1575 "I/O");
1576 goto fail;
1577 }
1578 }
1579
1580 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1581 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1582
1583 /* Bail out if chip is not recognized. */
1584 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1585 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1586 sc->sk_type, sc->sk_rev);
1587 error = ENXIO;
1588 goto fail;
1589 }
1590
1591 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1592 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1593 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1594 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1595 "SK interrupt moderation");
1596
1597 /* Pull in device tunables. */
1598 sc->sk_int_mod = SK_IM_DEFAULT;
1599 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1600 "int_mod", &sc->sk_int_mod);
1601 if (error == 0) {
1602 if (sc->sk_int_mod < SK_IM_MIN ||
1603 sc->sk_int_mod > SK_IM_MAX) {
1604 device_printf(dev, "int_mod value out of range; "
1605 "using default: %d\n", SK_IM_DEFAULT);
1606 sc->sk_int_mod = SK_IM_DEFAULT;
1607 }
1608 }
1609
1610 /* Reset the adapter. */
1611 sk_reset(sc);
1612
1613 skrs = sk_win_read_1(sc, SK_EPROM0);
1614 if (sc->sk_type == SK_GENESIS) {
1615 /* Read and save RAM size and RAMbuffer offset */
1616 switch(skrs) {
1617 case SK_RAMSIZE_512K_64:
1618 sc->sk_ramsize = 0x80000;
1619 sc->sk_rboff = SK_RBOFF_0;
1620 break;
1621 case SK_RAMSIZE_1024K_64:
1622 sc->sk_ramsize = 0x100000;
1623 sc->sk_rboff = SK_RBOFF_80000;
1624 break;
1625 case SK_RAMSIZE_1024K_128:
1626 sc->sk_ramsize = 0x100000;
1627 sc->sk_rboff = SK_RBOFF_0;
1628 break;
1629 case SK_RAMSIZE_2048K_128:
1630 sc->sk_ramsize = 0x200000;
1631 sc->sk_rboff = SK_RBOFF_0;
1632 break;
1633 default:
1634 device_printf(dev, "unknown ram size: %d\n", skrs);
1635 error = ENXIO;
1636 goto fail;
1637 }
1638 } else { /* SK_YUKON_FAMILY */
1639 if (skrs == 0x00)
1640 sc->sk_ramsize = 0x20000;
1641 else
1642 sc->sk_ramsize = skrs * (1<<12);
1643 sc->sk_rboff = SK_RBOFF_0;
1644 }
1645
1646 /* Read and save physical media type */
1647 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1648
1649 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1650 sc->sk_coppertype = 1;
1651 else
1652 sc->sk_coppertype = 0;
1653
1654 /* Determine whether to name it with VPD PN or just make it up.
1655 * Marvell Yukon VPD PN seems to freqently be bogus. */
1656 switch (pci_get_device(dev)) {
1657 case DEVICEID_SK_V1:
1658 case DEVICEID_BELKIN_5005:
1659 case DEVICEID_3COM_3C940:
1660 case DEVICEID_LINKSYS_EG1032:
1661 case DEVICEID_DLINK_DGE530T_A1:
1662 case DEVICEID_DLINK_DGE530T_B1:
1663 /* Stay with VPD PN. */
1664 (void) pci_get_vpd_ident(dev, &pname);
1665 break;
1666 case DEVICEID_SK_V2:
1667 /* YUKON VPD PN might bear no resemblance to reality. */
1668 switch (sc->sk_type) {
1669 case SK_GENESIS:
1670 /* Stay with VPD PN. */
1671 (void) pci_get_vpd_ident(dev, &pname);
1672 break;
1673 case SK_YUKON:
1674 pname = "Marvell Yukon Gigabit Ethernet";
1675 break;
1676 case SK_YUKON_LITE:
1677 pname = "Marvell Yukon Lite Gigabit Ethernet";
1678 break;
1679 case SK_YUKON_LP:
1680 pname = "Marvell Yukon LP Gigabit Ethernet";
1681 break;
1682 default:
1683 pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1684 break;
1685 }
1686
1687 /* Yukon Lite Rev. A0 needs special test. */
1688 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1689 u_int32_t far;
1690 u_int8_t testbyte;
1691
1692 /* Save flash address register before testing. */
1693 far = sk_win_read_4(sc, SK_EP_ADDR);
1694
1695 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1696 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1697
1698 if (testbyte != 0x00) {
1699 /* Yukon Lite Rev. A0 detected. */
1700 sc->sk_type = SK_YUKON_LITE;
1701 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1702 /* Restore flash address register. */
1703 sk_win_write_4(sc, SK_EP_ADDR, far);
1704 }
1705 }
1706 break;
1707 default:
1708 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1709 "chipver=%02x, rev=%x\n",
1710 pci_get_vendor(dev), pci_get_device(dev),
1711 sc->sk_type, sc->sk_rev);
1712 error = ENXIO;
1713 goto fail;
1714 }
1715
1716 if (sc->sk_type == SK_YUKON_LITE) {
1717 switch (sc->sk_rev) {
1718 case SK_YUKON_LITE_REV_A0:
1719 revstr = "A0";
1720 break;
1721 case SK_YUKON_LITE_REV_A1:
1722 revstr = "A1";
1723 break;
1724 case SK_YUKON_LITE_REV_A3:
1725 revstr = "A3";
1726 break;
1727 default:
1728 revstr = "";
1729 break;
1730 }
1731 } else {
1732 revstr = "";
1733 }
1734
1735 /* Announce the product name and more VPD data if there. */
1736 if (pname != NULL)
1737 device_printf(dev, "%s rev. %s(0x%x)\n",
1738 pname, revstr, sc->sk_rev);
1739
1740 if (bootverbose) {
1741 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type);
1742 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev);
1743 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1744 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1745 }
1746
1747 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1748 if (sc->sk_devs[SK_PORT_A] == NULL) {
1749 device_printf(dev, "failed to add child for PORT_A\n");
1750 error = ENXIO;
1751 goto fail;
1752 }
1753 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1754 if (port == NULL) {
1755 device_printf(dev, "failed to allocate memory for "
1756 "ivars of PORT_A\n");
1757 error = ENXIO;
1758 goto fail;
1759 }
1760 *port = SK_PORT_A;
1761 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1762
1763 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1764 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1765 if (sc->sk_devs[SK_PORT_B] == NULL) {
1766 device_printf(dev, "failed to add child for PORT_B\n");
1767 error = ENXIO;
1768 goto fail;
1769 }
1770 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1771 if (port == NULL) {
1772 device_printf(dev, "failed to allocate memory for "
1773 "ivars of PORT_B\n");
1774 error = ENXIO;
1775 goto fail;
1776 }
1777 *port = SK_PORT_B;
1778 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1779 }
1780
1781 /* Turn on the 'driver is loaded' LED. */
1782 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1783
1784 error = bus_generic_attach(dev);
1785 if (error) {
1786 device_printf(dev, "failed to attach port(s)\n");
1787 goto fail;
1788 }
1789
1790 /* Hook interrupt last to avoid having to lock softc */
1791 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1792 NULL, sk_intr, sc, &sc->sk_intrhand);
1793
1794 if (error) {
1795 device_printf(dev, "couldn't set up irq\n");
1796 goto fail;
1797 }
1798
1799 fail:
1800 if (error)
1801 skc_detach(dev);
1802
1803 return(error);
1804 }
1805
1806 /*
1807 * Shutdown hardware and free up resources. This can be called any
1808 * time after the mutex has been initialized. It is called in both
1809 * the error case in attach and the normal detach case so it needs
1810 * to be careful about only freeing resources that have actually been
1811 * allocated.
1812 */
1813 static int
sk_detach(dev)1814 sk_detach(dev)
1815 device_t dev;
1816 {
1817 struct sk_if_softc *sc_if;
1818 struct ifnet *ifp;
1819
1820 sc_if = device_get_softc(dev);
1821 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1822 ("sk mutex not initialized in sk_detach"));
1823 SK_IF_LOCK(sc_if);
1824
1825 ifp = sc_if->sk_ifp;
1826 /* These should only be active if attach_xmac succeeded */
1827 if (device_is_attached(dev)) {
1828 sk_stop(sc_if);
1829 /* Can't hold locks while calling detach */
1830 SK_IF_UNLOCK(sc_if);
1831 callout_drain(&sc_if->sk_tick_ch);
1832 callout_drain(&sc_if->sk_watchdog_ch);
1833 ether_ifdetach(ifp);
1834 SK_IF_LOCK(sc_if);
1835 }
1836 /*
1837 * We're generally called from skc_detach() which is using
1838 * device_delete_child() to get to here. It's already trashed
1839 * miibus for us, so don't do it here or we'll panic.
1840 */
1841 /*
1842 if (sc_if->sk_miibus != NULL)
1843 device_delete_child(dev, sc_if->sk_miibus);
1844 */
1845 bus_generic_detach(dev);
1846 sk_dma_jumbo_free(sc_if);
1847 sk_dma_free(sc_if);
1848 SK_IF_UNLOCK(sc_if);
1849 if (ifp)
1850 if_free(ifp);
1851
1852 return(0);
1853 }
1854
1855 static int
skc_detach(dev)1856 skc_detach(dev)
1857 device_t dev;
1858 {
1859 struct sk_softc *sc;
1860
1861 sc = device_get_softc(dev);
1862 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1863
1864 if (device_is_alive(dev)) {
1865 if (sc->sk_devs[SK_PORT_A] != NULL) {
1866 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1867 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1868 }
1869 if (sc->sk_devs[SK_PORT_B] != NULL) {
1870 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1871 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1872 }
1873 bus_generic_detach(dev);
1874 }
1875
1876 if (sc->sk_intrhand)
1877 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1878 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1879
1880 mtx_destroy(&sc->sk_mii_mtx);
1881 mtx_destroy(&sc->sk_mtx);
1882
1883 return(0);
1884 }
1885
1886 static bus_dma_tag_t
skc_get_dma_tag(device_t bus,device_t child __unused)1887 skc_get_dma_tag(device_t bus, device_t child __unused)
1888 {
1889
1890 return (bus_get_dma_tag(bus));
1891 }
1892
1893 struct sk_dmamap_arg {
1894 bus_addr_t sk_busaddr;
1895 };
1896
1897 static void
sk_dmamap_cb(arg,segs,nseg,error)1898 sk_dmamap_cb(arg, segs, nseg, error)
1899 void *arg;
1900 bus_dma_segment_t *segs;
1901 int nseg;
1902 int error;
1903 {
1904 struct sk_dmamap_arg *ctx;
1905
1906 if (error != 0)
1907 return;
1908
1909 ctx = arg;
1910 ctx->sk_busaddr = segs[0].ds_addr;
1911 }
1912
1913 /*
1914 * Allocate jumbo buffer storage. The SysKonnect adapters support
1915 * "jumbograms" (9K frames), although SysKonnect doesn't currently
1916 * use them in their drivers. In order for us to use them, we need
1917 * large 9K receive buffers, however standard mbuf clusters are only
1918 * 2048 bytes in size. Consequently, we need to allocate and manage
1919 * our own jumbo buffer pool. Fortunately, this does not require an
1920 * excessive amount of additional code.
1921 */
1922 static int
sk_dma_alloc(sc_if)1923 sk_dma_alloc(sc_if)
1924 struct sk_if_softc *sc_if;
1925 {
1926 struct sk_dmamap_arg ctx;
1927 struct sk_txdesc *txd;
1928 struct sk_rxdesc *rxd;
1929 int error, i;
1930
1931 /* create parent tag */
1932 /*
1933 * XXX
1934 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1935 * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1936 * However bz@ reported that it does not work on amd64 with > 4GB
1937 * RAM. Until we have more clues of the breakage, disable DAC mode
1938 * by limiting DMA address to be in 32bit address space.
1939 */
1940 error = bus_dma_tag_create(
1941 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1942 1, 0, /* algnmnt, boundary */
1943 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1944 BUS_SPACE_MAXADDR, /* highaddr */
1945 NULL, NULL, /* filter, filterarg */
1946 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1947 0, /* nsegments */
1948 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1949 0, /* flags */
1950 NULL, NULL, /* lockfunc, lockarg */
1951 &sc_if->sk_cdata.sk_parent_tag);
1952 if (error != 0) {
1953 device_printf(sc_if->sk_if_dev,
1954 "failed to create parent DMA tag\n");
1955 goto fail;
1956 }
1957
1958 /* create tag for Tx ring */
1959 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1960 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1961 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1962 BUS_SPACE_MAXADDR, /* highaddr */
1963 NULL, NULL, /* filter, filterarg */
1964 SK_TX_RING_SZ, /* maxsize */
1965 1, /* nsegments */
1966 SK_TX_RING_SZ, /* maxsegsize */
1967 0, /* flags */
1968 NULL, NULL, /* lockfunc, lockarg */
1969 &sc_if->sk_cdata.sk_tx_ring_tag);
1970 if (error != 0) {
1971 device_printf(sc_if->sk_if_dev,
1972 "failed to allocate Tx ring DMA tag\n");
1973 goto fail;
1974 }
1975
1976 /* create tag for Rx ring */
1977 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1978 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1979 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1980 BUS_SPACE_MAXADDR, /* highaddr */
1981 NULL, NULL, /* filter, filterarg */
1982 SK_RX_RING_SZ, /* maxsize */
1983 1, /* nsegments */
1984 SK_RX_RING_SZ, /* maxsegsize */
1985 0, /* flags */
1986 NULL, NULL, /* lockfunc, lockarg */
1987 &sc_if->sk_cdata.sk_rx_ring_tag);
1988 if (error != 0) {
1989 device_printf(sc_if->sk_if_dev,
1990 "failed to allocate Rx ring DMA tag\n");
1991 goto fail;
1992 }
1993
1994 /* create tag for Tx buffers */
1995 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1996 1, 0, /* algnmnt, boundary */
1997 BUS_SPACE_MAXADDR, /* lowaddr */
1998 BUS_SPACE_MAXADDR, /* highaddr */
1999 NULL, NULL, /* filter, filterarg */
2000 MCLBYTES * SK_MAXTXSEGS, /* maxsize */
2001 SK_MAXTXSEGS, /* nsegments */
2002 MCLBYTES, /* maxsegsize */
2003 0, /* flags */
2004 NULL, NULL, /* lockfunc, lockarg */
2005 &sc_if->sk_cdata.sk_tx_tag);
2006 if (error != 0) {
2007 device_printf(sc_if->sk_if_dev,
2008 "failed to allocate Tx DMA tag\n");
2009 goto fail;
2010 }
2011
2012 /* create tag for Rx buffers */
2013 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2014 1, 0, /* algnmnt, boundary */
2015 BUS_SPACE_MAXADDR, /* lowaddr */
2016 BUS_SPACE_MAXADDR, /* highaddr */
2017 NULL, NULL, /* filter, filterarg */
2018 MCLBYTES, /* maxsize */
2019 1, /* nsegments */
2020 MCLBYTES, /* maxsegsize */
2021 0, /* flags */
2022 NULL, NULL, /* lockfunc, lockarg */
2023 &sc_if->sk_cdata.sk_rx_tag);
2024 if (error != 0) {
2025 device_printf(sc_if->sk_if_dev,
2026 "failed to allocate Rx DMA tag\n");
2027 goto fail;
2028 }
2029
2030 /* allocate DMA'able memory and load the DMA map for Tx ring */
2031 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2032 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
2033 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
2034 if (error != 0) {
2035 device_printf(sc_if->sk_if_dev,
2036 "failed to allocate DMA'able memory for Tx ring\n");
2037 goto fail;
2038 }
2039
2040 ctx.sk_busaddr = 0;
2041 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2042 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2043 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2044 if (error != 0) {
2045 device_printf(sc_if->sk_if_dev,
2046 "failed to load DMA'able memory for Tx ring\n");
2047 goto fail;
2048 }
2049 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2050
2051 /* allocate DMA'able memory and load the DMA map for Rx ring */
2052 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2053 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2054 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2055 if (error != 0) {
2056 device_printf(sc_if->sk_if_dev,
2057 "failed to allocate DMA'able memory for Rx ring\n");
2058 goto fail;
2059 }
2060
2061 ctx.sk_busaddr = 0;
2062 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2063 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2064 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2065 if (error != 0) {
2066 device_printf(sc_if->sk_if_dev,
2067 "failed to load DMA'able memory for Rx ring\n");
2068 goto fail;
2069 }
2070 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2071
2072 /* create DMA maps for Tx buffers */
2073 for (i = 0; i < SK_TX_RING_CNT; i++) {
2074 txd = &sc_if->sk_cdata.sk_txdesc[i];
2075 txd->tx_m = NULL;
2076 txd->tx_dmamap = NULL;
2077 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2078 &txd->tx_dmamap);
2079 if (error != 0) {
2080 device_printf(sc_if->sk_if_dev,
2081 "failed to create Tx dmamap\n");
2082 goto fail;
2083 }
2084 }
2085
2086 /* create DMA maps for Rx buffers */
2087 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2088 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2089 device_printf(sc_if->sk_if_dev,
2090 "failed to create spare Rx dmamap\n");
2091 goto fail;
2092 }
2093 for (i = 0; i < SK_RX_RING_CNT; i++) {
2094 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2095 rxd->rx_m = NULL;
2096 rxd->rx_dmamap = NULL;
2097 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2098 &rxd->rx_dmamap);
2099 if (error != 0) {
2100 device_printf(sc_if->sk_if_dev,
2101 "failed to create Rx dmamap\n");
2102 goto fail;
2103 }
2104 }
2105
2106 fail:
2107 return (error);
2108 }
2109
2110 static int
sk_dma_jumbo_alloc(sc_if)2111 sk_dma_jumbo_alloc(sc_if)
2112 struct sk_if_softc *sc_if;
2113 {
2114 struct sk_dmamap_arg ctx;
2115 struct sk_rxdesc *jrxd;
2116 int error, i;
2117
2118 if (jumbo_disable != 0) {
2119 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2120 sc_if->sk_jumbo_disable = 1;
2121 return (0);
2122 }
2123 /* create tag for jumbo Rx ring */
2124 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2125 SK_RING_ALIGN, 0, /* algnmnt, boundary */
2126 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2127 BUS_SPACE_MAXADDR, /* highaddr */
2128 NULL, NULL, /* filter, filterarg */
2129 SK_JUMBO_RX_RING_SZ, /* maxsize */
2130 1, /* nsegments */
2131 SK_JUMBO_RX_RING_SZ, /* maxsegsize */
2132 0, /* flags */
2133 NULL, NULL, /* lockfunc, lockarg */
2134 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2135 if (error != 0) {
2136 device_printf(sc_if->sk_if_dev,
2137 "failed to allocate jumbo Rx ring DMA tag\n");
2138 goto jumbo_fail;
2139 }
2140
2141 /* create tag for jumbo Rx buffers */
2142 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2143 1, 0, /* algnmnt, boundary */
2144 BUS_SPACE_MAXADDR, /* lowaddr */
2145 BUS_SPACE_MAXADDR, /* highaddr */
2146 NULL, NULL, /* filter, filterarg */
2147 MJUM9BYTES, /* maxsize */
2148 1, /* nsegments */
2149 MJUM9BYTES, /* maxsegsize */
2150 0, /* flags */
2151 NULL, NULL, /* lockfunc, lockarg */
2152 &sc_if->sk_cdata.sk_jumbo_rx_tag);
2153 if (error != 0) {
2154 device_printf(sc_if->sk_if_dev,
2155 "failed to allocate jumbo Rx DMA tag\n");
2156 goto jumbo_fail;
2157 }
2158
2159 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2160 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2161 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2162 BUS_DMA_COHERENT | BUS_DMA_ZERO,
2163 &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2164 if (error != 0) {
2165 device_printf(sc_if->sk_if_dev,
2166 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2167 goto jumbo_fail;
2168 }
2169
2170 ctx.sk_busaddr = 0;
2171 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2172 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2173 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2174 &ctx, BUS_DMA_NOWAIT);
2175 if (error != 0) {
2176 device_printf(sc_if->sk_if_dev,
2177 "failed to load DMA'able memory for jumbo Rx ring\n");
2178 goto jumbo_fail;
2179 }
2180 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2181
2182 /* create DMA maps for jumbo Rx buffers */
2183 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2184 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2185 device_printf(sc_if->sk_if_dev,
2186 "failed to create spare jumbo Rx dmamap\n");
2187 goto jumbo_fail;
2188 }
2189 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2190 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2191 jrxd->rx_m = NULL;
2192 jrxd->rx_dmamap = NULL;
2193 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2194 &jrxd->rx_dmamap);
2195 if (error != 0) {
2196 device_printf(sc_if->sk_if_dev,
2197 "failed to create jumbo Rx dmamap\n");
2198 goto jumbo_fail;
2199 }
2200 }
2201
2202 return (0);
2203
2204 jumbo_fail:
2205 sk_dma_jumbo_free(sc_if);
2206 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2207 "resource shortage\n");
2208 sc_if->sk_jumbo_disable = 1;
2209 return (0);
2210 }
2211
2212 static void
sk_dma_free(sc_if)2213 sk_dma_free(sc_if)
2214 struct sk_if_softc *sc_if;
2215 {
2216 struct sk_txdesc *txd;
2217 struct sk_rxdesc *rxd;
2218 int i;
2219
2220 /* Tx ring */
2221 if (sc_if->sk_cdata.sk_tx_ring_tag) {
2222 if (sc_if->sk_rdata.sk_tx_ring_paddr)
2223 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2224 sc_if->sk_cdata.sk_tx_ring_map);
2225 if (sc_if->sk_rdata.sk_tx_ring)
2226 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2227 sc_if->sk_rdata.sk_tx_ring,
2228 sc_if->sk_cdata.sk_tx_ring_map);
2229 sc_if->sk_rdata.sk_tx_ring = NULL;
2230 sc_if->sk_rdata.sk_tx_ring_paddr = 0;
2231 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2232 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2233 }
2234 /* Rx ring */
2235 if (sc_if->sk_cdata.sk_rx_ring_tag) {
2236 if (sc_if->sk_rdata.sk_rx_ring_paddr)
2237 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2238 sc_if->sk_cdata.sk_rx_ring_map);
2239 if (sc_if->sk_rdata.sk_rx_ring)
2240 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2241 sc_if->sk_rdata.sk_rx_ring,
2242 sc_if->sk_cdata.sk_rx_ring_map);
2243 sc_if->sk_rdata.sk_rx_ring = NULL;
2244 sc_if->sk_rdata.sk_rx_ring_paddr = 0;
2245 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2246 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2247 }
2248 /* Tx buffers */
2249 if (sc_if->sk_cdata.sk_tx_tag) {
2250 for (i = 0; i < SK_TX_RING_CNT; i++) {
2251 txd = &sc_if->sk_cdata.sk_txdesc[i];
2252 if (txd->tx_dmamap) {
2253 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2254 txd->tx_dmamap);
2255 txd->tx_dmamap = NULL;
2256 }
2257 }
2258 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2259 sc_if->sk_cdata.sk_tx_tag = NULL;
2260 }
2261 /* Rx buffers */
2262 if (sc_if->sk_cdata.sk_rx_tag) {
2263 for (i = 0; i < SK_RX_RING_CNT; i++) {
2264 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2265 if (rxd->rx_dmamap) {
2266 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2267 rxd->rx_dmamap);
2268 rxd->rx_dmamap = NULL;
2269 }
2270 }
2271 if (sc_if->sk_cdata.sk_rx_sparemap) {
2272 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2273 sc_if->sk_cdata.sk_rx_sparemap);
2274 sc_if->sk_cdata.sk_rx_sparemap = NULL;
2275 }
2276 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2277 sc_if->sk_cdata.sk_rx_tag = NULL;
2278 }
2279
2280 if (sc_if->sk_cdata.sk_parent_tag) {
2281 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2282 sc_if->sk_cdata.sk_parent_tag = NULL;
2283 }
2284 }
2285
2286 static void
sk_dma_jumbo_free(sc_if)2287 sk_dma_jumbo_free(sc_if)
2288 struct sk_if_softc *sc_if;
2289 {
2290 struct sk_rxdesc *jrxd;
2291 int i;
2292
2293 /* jumbo Rx ring */
2294 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2295 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr)
2296 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2297 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2298 if (sc_if->sk_rdata.sk_jumbo_rx_ring)
2299 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2300 sc_if->sk_rdata.sk_jumbo_rx_ring,
2301 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2302 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2303 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0;
2304 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2305 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2306 }
2307
2308 /* jumbo Rx buffers */
2309 if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2310 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2311 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2312 if (jrxd->rx_dmamap) {
2313 bus_dmamap_destroy(
2314 sc_if->sk_cdata.sk_jumbo_rx_tag,
2315 jrxd->rx_dmamap);
2316 jrxd->rx_dmamap = NULL;
2317 }
2318 }
2319 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2320 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2321 sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2322 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2323 }
2324 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2325 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2326 }
2327 }
2328
2329 static void
sk_txcksum(ifp,m,f)2330 sk_txcksum(ifp, m, f)
2331 struct ifnet *ifp;
2332 struct mbuf *m;
2333 struct sk_tx_desc *f;
2334 {
2335 struct ip *ip;
2336 u_int16_t offset;
2337 u_int8_t *p;
2338
2339 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2340 for(; m && m->m_len == 0; m = m->m_next)
2341 ;
2342 if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2343 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2344 /* checksum may be corrupted */
2345 goto sendit;
2346 }
2347 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2348 if (m->m_len != ETHER_HDR_LEN) {
2349 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2350 __func__);
2351 /* checksum may be corrupted */
2352 goto sendit;
2353 }
2354 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2355 ;
2356 if (m == NULL) {
2357 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2358 /* checksum may be corrupted */
2359 goto sendit;
2360 }
2361 ip = mtod(m, struct ip *);
2362 } else {
2363 p = mtod(m, u_int8_t *);
2364 p += ETHER_HDR_LEN;
2365 ip = (struct ip *)p;
2366 }
2367 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2368
2369 sendit:
2370 f->sk_csum_startval = 0;
2371 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2372 (offset << 16));
2373 }
2374
2375 static int
sk_encap(sc_if,m_head)2376 sk_encap(sc_if, m_head)
2377 struct sk_if_softc *sc_if;
2378 struct mbuf **m_head;
2379 {
2380 struct sk_txdesc *txd;
2381 struct sk_tx_desc *f = NULL;
2382 struct mbuf *m;
2383 bus_dma_segment_t txsegs[SK_MAXTXSEGS];
2384 u_int32_t cflags, frag, si, sk_ctl;
2385 int error, i, nseg;
2386
2387 SK_IF_LOCK_ASSERT(sc_if);
2388
2389 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2390 return (ENOBUFS);
2391
2392 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2393 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2394 if (error == EFBIG) {
2395 m = m_defrag(*m_head, M_NOWAIT);
2396 if (m == NULL) {
2397 m_freem(*m_head);
2398 *m_head = NULL;
2399 return (ENOMEM);
2400 }
2401 *m_head = m;
2402 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2403 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2404 if (error != 0) {
2405 m_freem(*m_head);
2406 *m_head = NULL;
2407 return (error);
2408 }
2409 } else if (error != 0)
2410 return (error);
2411 if (nseg == 0) {
2412 m_freem(*m_head);
2413 *m_head = NULL;
2414 return (EIO);
2415 }
2416 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2417 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2418 return (ENOBUFS);
2419 }
2420
2421 m = *m_head;
2422 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2423 cflags = SK_OPCODE_CSUM;
2424 else
2425 cflags = SK_OPCODE_DEFAULT;
2426 si = frag = sc_if->sk_cdata.sk_tx_prod;
2427 for (i = 0; i < nseg; i++) {
2428 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2429 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2430 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2431 sk_ctl = txsegs[i].ds_len | cflags;
2432 if (i == 0) {
2433 if (cflags == SK_OPCODE_CSUM)
2434 sk_txcksum(sc_if->sk_ifp, m, f);
2435 sk_ctl |= SK_TXCTL_FIRSTFRAG;
2436 } else
2437 sk_ctl |= SK_TXCTL_OWN;
2438 f->sk_ctl = htole32(sk_ctl);
2439 sc_if->sk_cdata.sk_tx_cnt++;
2440 SK_INC(frag, SK_TX_RING_CNT);
2441 }
2442 sc_if->sk_cdata.sk_tx_prod = frag;
2443
2444 /* set EOF on the last desciptor */
2445 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2446 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2447 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2448
2449 /* turn the first descriptor ownership to NIC */
2450 f = &sc_if->sk_rdata.sk_tx_ring[si];
2451 f->sk_ctl |= htole32(SK_TXCTL_OWN);
2452
2453 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2454 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2455 txd->tx_m = m;
2456
2457 /* sync descriptors */
2458 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2459 BUS_DMASYNC_PREWRITE);
2460 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2461 sc_if->sk_cdata.sk_tx_ring_map,
2462 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2463
2464 return (0);
2465 }
2466
2467 static void
sk_start(ifp)2468 sk_start(ifp)
2469 struct ifnet *ifp;
2470 {
2471 struct sk_if_softc *sc_if;
2472
2473 sc_if = ifp->if_softc;
2474
2475 SK_IF_LOCK(sc_if);
2476 sk_start_locked(ifp);
2477 SK_IF_UNLOCK(sc_if);
2478
2479 return;
2480 }
2481
2482 static void
sk_start_locked(ifp)2483 sk_start_locked(ifp)
2484 struct ifnet *ifp;
2485 {
2486 struct sk_softc *sc;
2487 struct sk_if_softc *sc_if;
2488 struct mbuf *m_head;
2489 int enq;
2490
2491 sc_if = ifp->if_softc;
2492 sc = sc_if->sk_softc;
2493
2494 SK_IF_LOCK_ASSERT(sc_if);
2495
2496 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2497 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2498 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2499 if (m_head == NULL)
2500 break;
2501
2502 /*
2503 * Pack the data into the transmit ring. If we
2504 * don't have room, set the OACTIVE flag and wait
2505 * for the NIC to drain the ring.
2506 */
2507 if (sk_encap(sc_if, &m_head)) {
2508 if (m_head == NULL)
2509 break;
2510 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2511 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2512 break;
2513 }
2514
2515 enq++;
2516 /*
2517 * If there's a BPF listener, bounce a copy of this frame
2518 * to him.
2519 */
2520 BPF_MTAP(ifp, m_head);
2521 }
2522
2523 if (enq > 0) {
2524 /* Transmit */
2525 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2526
2527 /* Set a timeout in case the chip goes out to lunch. */
2528 sc_if->sk_watchdog_timer = 5;
2529 }
2530 }
2531
2532
2533 static void
sk_watchdog(arg)2534 sk_watchdog(arg)
2535 void *arg;
2536 {
2537 struct sk_if_softc *sc_if;
2538 struct ifnet *ifp;
2539
2540 ifp = arg;
2541 sc_if = ifp->if_softc;
2542
2543 SK_IF_LOCK_ASSERT(sc_if);
2544
2545 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2546 goto done;
2547
2548 /*
2549 * Reclaim first as there is a possibility of losing Tx completion
2550 * interrupts.
2551 */
2552 sk_txeof(sc_if);
2553 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2554 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2555 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2556 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2557 sk_init_locked(sc_if);
2558 }
2559
2560 done:
2561 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2562
2563 return;
2564 }
2565
2566 static int
skc_shutdown(dev)2567 skc_shutdown(dev)
2568 device_t dev;
2569 {
2570 struct sk_softc *sc;
2571
2572 sc = device_get_softc(dev);
2573 SK_LOCK(sc);
2574
2575 /* Turn off the 'driver is loaded' LED. */
2576 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2577
2578 /*
2579 * Reset the GEnesis controller. Doing this should also
2580 * assert the resets on the attached XMAC(s).
2581 */
2582 sk_reset(sc);
2583 SK_UNLOCK(sc);
2584
2585 return (0);
2586 }
2587
2588 static int
skc_suspend(dev)2589 skc_suspend(dev)
2590 device_t dev;
2591 {
2592 struct sk_softc *sc;
2593 struct sk_if_softc *sc_if0, *sc_if1;
2594 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2595
2596 sc = device_get_softc(dev);
2597
2598 SK_LOCK(sc);
2599
2600 sc_if0 = sc->sk_if[SK_PORT_A];
2601 sc_if1 = sc->sk_if[SK_PORT_B];
2602 if (sc_if0 != NULL)
2603 ifp0 = sc_if0->sk_ifp;
2604 if (sc_if1 != NULL)
2605 ifp1 = sc_if1->sk_ifp;
2606 if (ifp0 != NULL)
2607 sk_stop(sc_if0);
2608 if (ifp1 != NULL)
2609 sk_stop(sc_if1);
2610 sc->sk_suspended = 1;
2611
2612 SK_UNLOCK(sc);
2613
2614 return (0);
2615 }
2616
2617 static int
skc_resume(dev)2618 skc_resume(dev)
2619 device_t dev;
2620 {
2621 struct sk_softc *sc;
2622 struct sk_if_softc *sc_if0, *sc_if1;
2623 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2624
2625 sc = device_get_softc(dev);
2626
2627 SK_LOCK(sc);
2628
2629 sc_if0 = sc->sk_if[SK_PORT_A];
2630 sc_if1 = sc->sk_if[SK_PORT_B];
2631 if (sc_if0 != NULL)
2632 ifp0 = sc_if0->sk_ifp;
2633 if (sc_if1 != NULL)
2634 ifp1 = sc_if1->sk_ifp;
2635 if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2636 sk_init_locked(sc_if0);
2637 if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2638 sk_init_locked(sc_if1);
2639 sc->sk_suspended = 0;
2640
2641 SK_UNLOCK(sc);
2642
2643 return (0);
2644 }
2645
2646 /*
2647 * According to the data sheet from SK-NET GENESIS the hardware can compute
2648 * two Rx checksums at the same time(Each checksum start position is
2649 * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2650 * does not work at least on my Yukon hardware. I tried every possible ways
2651 * to get correct checksum value but couldn't get correct one. So TCP/UDP
2652 * checksum offload was disabled at the moment and only IP checksum offload
2653 * was enabled.
2654 * As nomral IP header size is 20 bytes I can't expect it would give an
2655 * increase in throughput. However it seems it doesn't hurt performance in
2656 * my testing. If there is a more detailed information for checksum secret
2657 * of the hardware in question please contact yongari@FreeBSD.org to add
2658 * TCP/UDP checksum offload support.
2659 */
2660 static __inline void
sk_rxcksum(ifp,m,csum)2661 sk_rxcksum(ifp, m, csum)
2662 struct ifnet *ifp;
2663 struct mbuf *m;
2664 u_int32_t csum;
2665 {
2666 struct ether_header *eh;
2667 struct ip *ip;
2668 int32_t hlen, len, pktlen;
2669 u_int16_t csum1, csum2, ipcsum;
2670
2671 pktlen = m->m_pkthdr.len;
2672 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2673 return;
2674 eh = mtod(m, struct ether_header *);
2675 if (eh->ether_type != htons(ETHERTYPE_IP))
2676 return;
2677 ip = (struct ip *)(eh + 1);
2678 if (ip->ip_v != IPVERSION)
2679 return;
2680 hlen = ip->ip_hl << 2;
2681 pktlen -= sizeof(struct ether_header);
2682 if (hlen < sizeof(struct ip))
2683 return;
2684 if (ntohs(ip->ip_len) < hlen)
2685 return;
2686 if (ntohs(ip->ip_len) != pktlen)
2687 return;
2688
2689 csum1 = htons(csum & 0xffff);
2690 csum2 = htons((csum >> 16) & 0xffff);
2691 ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2692 /* checksum fixup for IP options */
2693 len = hlen - sizeof(struct ip);
2694 if (len > 0) {
2695 /*
2696 * If the second checksum value is correct we can compute IP
2697 * checksum with simple math. Unfortunately the second checksum
2698 * value is wrong so we can't verify the checksum from the
2699 * value(It seems there is some magic here to get correct
2700 * value). If the second checksum value is correct it also
2701 * means we can get TCP/UDP checksum) here. However, it still
2702 * needs pseudo header checksum calculation due to hardware
2703 * limitations.
2704 */
2705 return;
2706 }
2707 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2708 if (ipcsum == 0xffff)
2709 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2710 }
2711
2712 static __inline int
sk_rxvalid(sc,stat,len)2713 sk_rxvalid(sc, stat, len)
2714 struct sk_softc *sc;
2715 u_int32_t stat, len;
2716 {
2717
2718 if (sc->sk_type == SK_GENESIS) {
2719 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2720 XM_RXSTAT_BYTES(stat) != len)
2721 return (0);
2722 } else {
2723 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2724 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2725 YU_RXSTAT_JABBER)) != 0 ||
2726 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2727 YU_RXSTAT_BYTES(stat) != len)
2728 return (0);
2729 }
2730
2731 return (1);
2732 }
2733
2734 static void
sk_rxeof(sc_if)2735 sk_rxeof(sc_if)
2736 struct sk_if_softc *sc_if;
2737 {
2738 struct sk_softc *sc;
2739 struct mbuf *m;
2740 struct ifnet *ifp;
2741 struct sk_rx_desc *cur_rx;
2742 struct sk_rxdesc *rxd;
2743 int cons, prog;
2744 u_int32_t csum, rxstat, sk_ctl;
2745
2746 sc = sc_if->sk_softc;
2747 ifp = sc_if->sk_ifp;
2748
2749 SK_IF_LOCK_ASSERT(sc_if);
2750
2751 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2752 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2753
2754 prog = 0;
2755 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2756 prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2757 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2758 sk_ctl = le32toh(cur_rx->sk_ctl);
2759 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2760 break;
2761 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2762 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2763
2764 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2765 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2766 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2767 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2768 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2769 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2770 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2771 sk_discard_rxbuf(sc_if, cons);
2772 continue;
2773 }
2774
2775 m = rxd->rx_m;
2776 csum = le32toh(cur_rx->sk_csum);
2777 if (sk_newbuf(sc_if, cons) != 0) {
2778 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2779 /* reuse old buffer */
2780 sk_discard_rxbuf(sc_if, cons);
2781 continue;
2782 }
2783 m->m_pkthdr.rcvif = ifp;
2784 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2785 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2786 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2787 sk_rxcksum(ifp, m, csum);
2788 SK_IF_UNLOCK(sc_if);
2789 (*ifp->if_input)(ifp, m);
2790 SK_IF_LOCK(sc_if);
2791 }
2792
2793 if (prog > 0) {
2794 sc_if->sk_cdata.sk_rx_cons = cons;
2795 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2796 sc_if->sk_cdata.sk_rx_ring_map,
2797 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2798 }
2799 }
2800
2801 static void
sk_jumbo_rxeof(sc_if)2802 sk_jumbo_rxeof(sc_if)
2803 struct sk_if_softc *sc_if;
2804 {
2805 struct sk_softc *sc;
2806 struct mbuf *m;
2807 struct ifnet *ifp;
2808 struct sk_rx_desc *cur_rx;
2809 struct sk_rxdesc *jrxd;
2810 int cons, prog;
2811 u_int32_t csum, rxstat, sk_ctl;
2812
2813 sc = sc_if->sk_softc;
2814 ifp = sc_if->sk_ifp;
2815
2816 SK_IF_LOCK_ASSERT(sc_if);
2817
2818 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2819 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2820
2821 prog = 0;
2822 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2823 prog < SK_JUMBO_RX_RING_CNT;
2824 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2825 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2826 sk_ctl = le32toh(cur_rx->sk_ctl);
2827 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2828 break;
2829 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2830 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2831
2832 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2833 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2834 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2835 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2836 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2837 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2838 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2839 sk_discard_jumbo_rxbuf(sc_if, cons);
2840 continue;
2841 }
2842
2843 m = jrxd->rx_m;
2844 csum = le32toh(cur_rx->sk_csum);
2845 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2846 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2847 /* reuse old buffer */
2848 sk_discard_jumbo_rxbuf(sc_if, cons);
2849 continue;
2850 }
2851 m->m_pkthdr.rcvif = ifp;
2852 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2853 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2854 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2855 sk_rxcksum(ifp, m, csum);
2856 SK_IF_UNLOCK(sc_if);
2857 (*ifp->if_input)(ifp, m);
2858 SK_IF_LOCK(sc_if);
2859 }
2860
2861 if (prog > 0) {
2862 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2863 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2864 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2865 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2866 }
2867 }
2868
2869 static void
sk_txeof(sc_if)2870 sk_txeof(sc_if)
2871 struct sk_if_softc *sc_if;
2872 {
2873 struct sk_txdesc *txd;
2874 struct sk_tx_desc *cur_tx;
2875 struct ifnet *ifp;
2876 u_int32_t idx, sk_ctl;
2877
2878 ifp = sc_if->sk_ifp;
2879
2880 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2881 if (txd == NULL)
2882 return;
2883 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2884 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2885 /*
2886 * Go through our tx ring and free mbufs for those
2887 * frames that have been sent.
2888 */
2889 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2890 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2891 break;
2892 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2893 sk_ctl = le32toh(cur_tx->sk_ctl);
2894 if (sk_ctl & SK_TXCTL_OWN)
2895 break;
2896 sc_if->sk_cdata.sk_tx_cnt--;
2897 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2898 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2899 continue;
2900 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2901 BUS_DMASYNC_POSTWRITE);
2902 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2903
2904 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2905 m_freem(txd->tx_m);
2906 txd->tx_m = NULL;
2907 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2908 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2909 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2910 }
2911 sc_if->sk_cdata.sk_tx_cons = idx;
2912 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2913
2914 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2915 sc_if->sk_cdata.sk_tx_ring_map,
2916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2917 }
2918
2919 static void
sk_tick(xsc_if)2920 sk_tick(xsc_if)
2921 void *xsc_if;
2922 {
2923 struct sk_if_softc *sc_if;
2924 struct mii_data *mii;
2925 struct ifnet *ifp;
2926 int i;
2927
2928 sc_if = xsc_if;
2929 ifp = sc_if->sk_ifp;
2930 mii = device_get_softc(sc_if->sk_miibus);
2931
2932 if (!(ifp->if_flags & IFF_UP))
2933 return;
2934
2935 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2936 sk_intr_bcom(sc_if);
2937 return;
2938 }
2939
2940 /*
2941 * According to SysKonnect, the correct way to verify that
2942 * the link has come back up is to poll bit 0 of the GPIO
2943 * register three times. This pin has the signal from the
2944 * link_sync pin connected to it; if we read the same link
2945 * state 3 times in a row, we know the link is up.
2946 */
2947 for (i = 0; i < 3; i++) {
2948 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2949 break;
2950 }
2951
2952 if (i != 3) {
2953 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2954 return;
2955 }
2956
2957 /* Turn the GP0 interrupt back on. */
2958 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2959 SK_XM_READ_2(sc_if, XM_ISR);
2960 mii_tick(mii);
2961 callout_stop(&sc_if->sk_tick_ch);
2962 }
2963
2964 static void
sk_yukon_tick(xsc_if)2965 sk_yukon_tick(xsc_if)
2966 void *xsc_if;
2967 {
2968 struct sk_if_softc *sc_if;
2969 struct mii_data *mii;
2970
2971 sc_if = xsc_if;
2972 mii = device_get_softc(sc_if->sk_miibus);
2973
2974 mii_tick(mii);
2975 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2976 }
2977
2978 static void
sk_intr_bcom(sc_if)2979 sk_intr_bcom(sc_if)
2980 struct sk_if_softc *sc_if;
2981 {
2982 struct mii_data *mii;
2983 struct ifnet *ifp;
2984 int status;
2985 mii = device_get_softc(sc_if->sk_miibus);
2986 ifp = sc_if->sk_ifp;
2987
2988 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2989
2990 /*
2991 * Read the PHY interrupt register to make sure
2992 * we clear any pending interrupts.
2993 */
2994 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2995
2996 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2997 sk_init_xmac(sc_if);
2998 return;
2999 }
3000
3001 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3002 int lstat;
3003 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3004 BRGPHY_MII_AUXSTS);
3005
3006 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3007 mii_mediachg(mii);
3008 /* Turn off the link LED. */
3009 SK_IF_WRITE_1(sc_if, 0,
3010 SK_LINKLED1_CTL, SK_LINKLED_OFF);
3011 sc_if->sk_link = 0;
3012 } else if (status & BRGPHY_ISR_LNK_CHG) {
3013 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3014 BRGPHY_MII_IMR, 0xFF00);
3015 mii_tick(mii);
3016 sc_if->sk_link = 1;
3017 /* Turn on the link LED. */
3018 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3019 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3020 SK_LINKLED_BLINK_OFF);
3021 } else {
3022 mii_tick(mii);
3023 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3024 }
3025 }
3026
3027 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3028
3029 return;
3030 }
3031
3032 static void
sk_intr_xmac(sc_if)3033 sk_intr_xmac(sc_if)
3034 struct sk_if_softc *sc_if;
3035 {
3036 struct sk_softc *sc;
3037 u_int16_t status;
3038
3039 sc = sc_if->sk_softc;
3040 status = SK_XM_READ_2(sc_if, XM_ISR);
3041
3042 /*
3043 * Link has gone down. Start MII tick timeout to
3044 * watch for link resync.
3045 */
3046 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3047 if (status & XM_ISR_GP0_SET) {
3048 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3049 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3050 }
3051
3052 if (status & XM_ISR_AUTONEG_DONE) {
3053 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3054 }
3055 }
3056
3057 if (status & XM_IMR_TX_UNDERRUN)
3058 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3059
3060 if (status & XM_IMR_RX_OVERRUN)
3061 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3062
3063 status = SK_XM_READ_2(sc_if, XM_ISR);
3064
3065 return;
3066 }
3067
3068 static void
sk_intr_yukon(sc_if)3069 sk_intr_yukon(sc_if)
3070 struct sk_if_softc *sc_if;
3071 {
3072 u_int8_t status;
3073
3074 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3075 /* RX overrun */
3076 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3077 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3078 SK_RFCTL_RX_FIFO_OVER);
3079 }
3080 /* TX underrun */
3081 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3082 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3083 SK_TFCTL_TX_FIFO_UNDER);
3084 }
3085 }
3086
3087 static void
sk_intr(xsc)3088 sk_intr(xsc)
3089 void *xsc;
3090 {
3091 struct sk_softc *sc = xsc;
3092 struct sk_if_softc *sc_if0, *sc_if1;
3093 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
3094 u_int32_t status;
3095
3096 SK_LOCK(sc);
3097
3098 status = CSR_READ_4(sc, SK_ISSR);
3099 if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3100 goto done_locked;
3101
3102 sc_if0 = sc->sk_if[SK_PORT_A];
3103 sc_if1 = sc->sk_if[SK_PORT_B];
3104
3105 if (sc_if0 != NULL)
3106 ifp0 = sc_if0->sk_ifp;
3107 if (sc_if1 != NULL)
3108 ifp1 = sc_if1->sk_ifp;
3109
3110 for (; (status &= sc->sk_intrmask) != 0;) {
3111 /* Handle receive interrupts first. */
3112 if (status & SK_ISR_RX1_EOF) {
3113 if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3114 sk_jumbo_rxeof(sc_if0);
3115 else
3116 sk_rxeof(sc_if0);
3117 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3118 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3119 }
3120 if (status & SK_ISR_RX2_EOF) {
3121 if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3122 sk_jumbo_rxeof(sc_if1);
3123 else
3124 sk_rxeof(sc_if1);
3125 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3126 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3127 }
3128
3129 /* Then transmit interrupts. */
3130 if (status & SK_ISR_TX1_S_EOF) {
3131 sk_txeof(sc_if0);
3132 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3133 }
3134 if (status & SK_ISR_TX2_S_EOF) {
3135 sk_txeof(sc_if1);
3136 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3137 }
3138
3139 /* Then MAC interrupts. */
3140 if (status & SK_ISR_MAC1 &&
3141 ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3142 if (sc->sk_type == SK_GENESIS)
3143 sk_intr_xmac(sc_if0);
3144 else
3145 sk_intr_yukon(sc_if0);
3146 }
3147
3148 if (status & SK_ISR_MAC2 &&
3149 ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3150 if (sc->sk_type == SK_GENESIS)
3151 sk_intr_xmac(sc_if1);
3152 else
3153 sk_intr_yukon(sc_if1);
3154 }
3155
3156 if (status & SK_ISR_EXTERNAL_REG) {
3157 if (ifp0 != NULL &&
3158 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3159 sk_intr_bcom(sc_if0);
3160 if (ifp1 != NULL &&
3161 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3162 sk_intr_bcom(sc_if1);
3163 }
3164 status = CSR_READ_4(sc, SK_ISSR);
3165 }
3166
3167 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3168
3169 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3170 sk_start_locked(ifp0);
3171 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3172 sk_start_locked(ifp1);
3173
3174 done_locked:
3175 SK_UNLOCK(sc);
3176 }
3177
3178 static void
sk_init_xmac(sc_if)3179 sk_init_xmac(sc_if)
3180 struct sk_if_softc *sc_if;
3181 {
3182 struct sk_softc *sc;
3183 struct ifnet *ifp;
3184 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2];
3185 static const struct sk_bcom_hack bhack[] = {
3186 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3187 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3188 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3189 { 0, 0 } };
3190
3191 SK_IF_LOCK_ASSERT(sc_if);
3192
3193 sc = sc_if->sk_softc;
3194 ifp = sc_if->sk_ifp;
3195
3196 /* Unreset the XMAC. */
3197 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3198 DELAY(1000);
3199
3200 /* Reset the XMAC's internal state. */
3201 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3202
3203 /* Save the XMAC II revision */
3204 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3205
3206 /*
3207 * Perform additional initialization for external PHYs,
3208 * namely for the 1000baseTX cards that use the XMAC's
3209 * GMII mode.
3210 */
3211 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3212 int i = 0;
3213 u_int32_t val;
3214
3215 /* Take PHY out of reset. */
3216 val = sk_win_read_4(sc, SK_GPIO);
3217 if (sc_if->sk_port == SK_PORT_A)
3218 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3219 else
3220 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3221 sk_win_write_4(sc, SK_GPIO, val);
3222
3223 /* Enable GMII mode on the XMAC. */
3224 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3225
3226 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3227 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3228 DELAY(10000);
3229 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3230 BRGPHY_MII_IMR, 0xFFF0);
3231
3232 /*
3233 * Early versions of the BCM5400 apparently have
3234 * a bug that requires them to have their reserved
3235 * registers initialized to some magic values. I don't
3236 * know what the numbers do, I'm just the messenger.
3237 */
3238 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3239 == 0x6041) {
3240 while(bhack[i].reg) {
3241 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3242 bhack[i].reg, bhack[i].val);
3243 i++;
3244 }
3245 }
3246 }
3247
3248 /* Set station address */
3249 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3250 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3251 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3252 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3253 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3254
3255 if (ifp->if_flags & IFF_BROADCAST) {
3256 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3257 } else {
3258 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3259 }
3260
3261 /* We don't need the FCS appended to the packet. */
3262 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3263
3264 /* We want short frames padded to 60 bytes. */
3265 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3266
3267 /*
3268 * Enable the reception of all error frames. This is is
3269 * a necessary evil due to the design of the XMAC. The
3270 * XMAC's receive FIFO is only 8K in size, however jumbo
3271 * frames can be up to 9000 bytes in length. When bad
3272 * frame filtering is enabled, the XMAC's RX FIFO operates
3273 * in 'store and forward' mode. For this to work, the
3274 * entire frame has to fit into the FIFO, but that means
3275 * that jumbo frames larger than 8192 bytes will be
3276 * truncated. Disabling all bad frame filtering causes
3277 * the RX FIFO to operate in streaming mode, in which
3278 * case the XMAC will start transferring frames out of the
3279 * RX FIFO as soon as the FIFO threshold is reached.
3280 */
3281 if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3282 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3283 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3284 XM_MODE_RX_INRANGELEN);
3285 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3286 } else
3287 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3288
3289 /*
3290 * Bump up the transmit threshold. This helps hold off transmit
3291 * underruns when we're blasting traffic from both ports at once.
3292 */
3293 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3294
3295 /* Set Rx filter */
3296 sk_rxfilter_genesis(sc_if);
3297
3298 /* Clear and enable interrupts */
3299 SK_XM_READ_2(sc_if, XM_ISR);
3300 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3301 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3302 else
3303 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3304
3305 /* Configure MAC arbiter */
3306 switch(sc_if->sk_xmac_rev) {
3307 case XM_XMAC_REV_B2:
3308 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3309 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3310 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3311 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3312 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3313 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3314 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3315 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3316 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3317 break;
3318 case XM_XMAC_REV_C1:
3319 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3320 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3321 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3322 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3323 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3324 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3325 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3326 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3327 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3328 break;
3329 default:
3330 break;
3331 }
3332 sk_win_write_2(sc, SK_MACARB_CTL,
3333 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3334
3335 sc_if->sk_link = 1;
3336
3337 return;
3338 }
3339
3340 static void
sk_init_yukon(sc_if)3341 sk_init_yukon(sc_if)
3342 struct sk_if_softc *sc_if;
3343 {
3344 u_int32_t phy, v;
3345 u_int16_t reg;
3346 struct sk_softc *sc;
3347 struct ifnet *ifp;
3348 u_int8_t *eaddr;
3349 int i;
3350
3351 SK_IF_LOCK_ASSERT(sc_if);
3352
3353 sc = sc_if->sk_softc;
3354 ifp = sc_if->sk_ifp;
3355
3356 if (sc->sk_type == SK_YUKON_LITE &&
3357 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3358 /*
3359 * Workaround code for COMA mode, set PHY reset.
3360 * Otherwise it will not correctly take chip out of
3361 * powerdown (coma)
3362 */
3363 v = sk_win_read_4(sc, SK_GPIO);
3364 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3365 sk_win_write_4(sc, SK_GPIO, v);
3366 }
3367
3368 /* GMAC and GPHY Reset */
3369 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3370 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3371 DELAY(1000);
3372
3373 if (sc->sk_type == SK_YUKON_LITE &&
3374 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3375 /*
3376 * Workaround code for COMA mode, clear PHY reset
3377 */
3378 v = sk_win_read_4(sc, SK_GPIO);
3379 v |= SK_GPIO_DIR9;
3380 v &= ~SK_GPIO_DAT9;
3381 sk_win_write_4(sc, SK_GPIO, v);
3382 }
3383
3384 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3385 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3386
3387 if (sc->sk_coppertype)
3388 phy |= SK_GPHY_COPPER;
3389 else
3390 phy |= SK_GPHY_FIBER;
3391
3392 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3393 DELAY(1000);
3394 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3395 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3396 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3397
3398 /* unused read of the interrupt source register */
3399 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3400
3401 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3402
3403 /* MIB Counter Clear Mode set */
3404 reg |= YU_PAR_MIB_CLR;
3405 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3406
3407 /* MIB Counter Clear Mode clear */
3408 reg &= ~YU_PAR_MIB_CLR;
3409 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3410
3411 /* receive control reg */
3412 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3413
3414 /* transmit parameter register */
3415 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3416 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3417
3418 /* serial mode register */
3419 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3420 if (ifp->if_mtu > SK_MAX_FRAMELEN)
3421 reg |= YU_SMR_MFL_JUMBO;
3422 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3423
3424 /* Setup Yukon's station address */
3425 eaddr = IF_LLADDR(sc_if->sk_ifp);
3426 for (i = 0; i < 3; i++)
3427 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3428 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3429 /* Set GMAC source address of flow control. */
3430 for (i = 0; i < 3; i++)
3431 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3432 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3433 /* Set GMAC virtual address. */
3434 for (i = 0; i < 3; i++)
3435 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3436 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3437
3438 /* Set Rx filter */
3439 sk_rxfilter_yukon(sc_if);
3440
3441 /* enable interrupt mask for counter overflows */
3442 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3443 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3444 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3445
3446 /* Configure RX MAC FIFO Flush Mask */
3447 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3448 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3449 YU_RXSTAT_JABBER;
3450 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3451
3452 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3453 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3454 v = SK_TFCTL_OPERATION_ON;
3455 else
3456 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3457 /* Configure RX MAC FIFO */
3458 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3459 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3460
3461 /* Increase flush threshould to 64 bytes */
3462 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3463 SK_RFCTL_FIFO_THRESHOLD + 1);
3464
3465 /* Configure TX MAC FIFO */
3466 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3467 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3468 }
3469
3470 /*
3471 * Note that to properly initialize any part of the GEnesis chip,
3472 * you first have to take it out of reset mode.
3473 */
3474 static void
sk_init(xsc)3475 sk_init(xsc)
3476 void *xsc;
3477 {
3478 struct sk_if_softc *sc_if = xsc;
3479
3480 SK_IF_LOCK(sc_if);
3481 sk_init_locked(sc_if);
3482 SK_IF_UNLOCK(sc_if);
3483
3484 return;
3485 }
3486
3487 static void
sk_init_locked(sc_if)3488 sk_init_locked(sc_if)
3489 struct sk_if_softc *sc_if;
3490 {
3491 struct sk_softc *sc;
3492 struct ifnet *ifp;
3493 struct mii_data *mii;
3494 u_int16_t reg;
3495 u_int32_t imr;
3496 int error;
3497
3498 SK_IF_LOCK_ASSERT(sc_if);
3499
3500 ifp = sc_if->sk_ifp;
3501 sc = sc_if->sk_softc;
3502 mii = device_get_softc(sc_if->sk_miibus);
3503
3504 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3505 return;
3506
3507 /* Cancel pending I/O and free all RX/TX buffers. */
3508 sk_stop(sc_if);
3509
3510 if (sc->sk_type == SK_GENESIS) {
3511 /* Configure LINK_SYNC LED */
3512 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3513 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3514 SK_LINKLED_LINKSYNC_ON);
3515
3516 /* Configure RX LED */
3517 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3518 SK_RXLEDCTL_COUNTER_START);
3519
3520 /* Configure TX LED */
3521 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3522 SK_TXLEDCTL_COUNTER_START);
3523 }
3524
3525 /*
3526 * Configure descriptor poll timer
3527 *
3528 * SK-NET GENESIS data sheet says that possibility of losing Start
3529 * transmit command due to CPU/cache related interim storage problems
3530 * under certain conditions. The document recommends a polling
3531 * mechanism to send a Start transmit command to initiate transfer
3532 * of ready descriptors regulary. To cope with this issue sk(4) now
3533 * enables descriptor poll timer to initiate descriptor processing
3534 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3535 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3536 * command instead of waiting for next descriptor polling time.
3537 * The same rule may apply to Rx side too but it seems that is not
3538 * needed at the moment.
3539 * Since sk(4) uses descriptor polling as a last resort there is no
3540 * need to set smaller polling time than maximum allowable one.
3541 */
3542 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3543
3544 /* Configure I2C registers */
3545
3546 /* Configure XMAC(s) */
3547 switch (sc->sk_type) {
3548 case SK_GENESIS:
3549 sk_init_xmac(sc_if);
3550 break;
3551 case SK_YUKON:
3552 case SK_YUKON_LITE:
3553 case SK_YUKON_LP:
3554 sk_init_yukon(sc_if);
3555 break;
3556 }
3557 mii_mediachg(mii);
3558
3559 if (sc->sk_type == SK_GENESIS) {
3560 /* Configure MAC FIFOs */
3561 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3562 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3563 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3564
3565 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3566 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3567 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3568 }
3569
3570 /* Configure transmit arbiter(s) */
3571 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3572 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3573
3574 /* Configure RAMbuffers */
3575 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3576 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3577 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3578 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3579 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3580 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3581
3582 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3583 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3584 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3585 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3586 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3587 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3588 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3589
3590 /* Configure BMUs */
3591 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3592 if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3593 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3594 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3595 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3596 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3597 } else {
3598 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3599 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3600 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3601 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3602 }
3603
3604 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3605 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3606 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3607 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3608 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3609
3610 /* Init descriptors */
3611 if (ifp->if_mtu > SK_MAX_FRAMELEN)
3612 error = sk_init_jumbo_rx_ring(sc_if);
3613 else
3614 error = sk_init_rx_ring(sc_if);
3615 if (error != 0) {
3616 device_printf(sc_if->sk_if_dev,
3617 "initialization failed: no memory for rx buffers\n");
3618 sk_stop(sc_if);
3619 return;
3620 }
3621 sk_init_tx_ring(sc_if);
3622
3623 /* Set interrupt moderation if changed via sysctl. */
3624 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3625 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3626 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3627 sc->sk_int_ticks));
3628 if (bootverbose)
3629 device_printf(sc_if->sk_if_dev,
3630 "interrupt moderation is %d us.\n",
3631 sc->sk_int_mod);
3632 }
3633
3634 /* Configure interrupt handling */
3635 CSR_READ_4(sc, SK_ISSR);
3636 if (sc_if->sk_port == SK_PORT_A)
3637 sc->sk_intrmask |= SK_INTRS1;
3638 else
3639 sc->sk_intrmask |= SK_INTRS2;
3640
3641 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3642
3643 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3644
3645 /* Start BMUs. */
3646 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3647
3648 switch(sc->sk_type) {
3649 case SK_GENESIS:
3650 /* Enable XMACs TX and RX state machines */
3651 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3652 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3653 break;
3654 case SK_YUKON:
3655 case SK_YUKON_LITE:
3656 case SK_YUKON_LP:
3657 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3658 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3659 #if 0
3660 /* XXX disable 100Mbps and full duplex mode? */
3661 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3662 #endif
3663 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3664 }
3665
3666 /* Activate descriptor polling timer */
3667 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3668 /* start transfer of Tx descriptors */
3669 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3670
3671 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3672 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3673
3674 switch (sc->sk_type) {
3675 case SK_YUKON:
3676 case SK_YUKON_LITE:
3677 case SK_YUKON_LP:
3678 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3679 break;
3680 }
3681
3682 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3683
3684 return;
3685 }
3686
3687 static void
sk_stop(sc_if)3688 sk_stop(sc_if)
3689 struct sk_if_softc *sc_if;
3690 {
3691 int i;
3692 struct sk_softc *sc;
3693 struct sk_txdesc *txd;
3694 struct sk_rxdesc *rxd;
3695 struct sk_rxdesc *jrxd;
3696 struct ifnet *ifp;
3697 u_int32_t val;
3698
3699 SK_IF_LOCK_ASSERT(sc_if);
3700 sc = sc_if->sk_softc;
3701 ifp = sc_if->sk_ifp;
3702
3703 callout_stop(&sc_if->sk_tick_ch);
3704 callout_stop(&sc_if->sk_watchdog_ch);
3705
3706 /* stop Tx descriptor polling timer */
3707 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3708 /* stop transfer of Tx descriptors */
3709 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3710 for (i = 0; i < SK_TIMEOUT; i++) {
3711 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3712 if ((val & SK_TXBMU_TX_STOP) == 0)
3713 break;
3714 DELAY(1);
3715 }
3716 if (i == SK_TIMEOUT)
3717 device_printf(sc_if->sk_if_dev,
3718 "can not stop transfer of Tx descriptor\n");
3719 /* stop transfer of Rx descriptors */
3720 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3721 for (i = 0; i < SK_TIMEOUT; i++) {
3722 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3723 if ((val & SK_RXBMU_RX_STOP) == 0)
3724 break;
3725 DELAY(1);
3726 }
3727 if (i == SK_TIMEOUT)
3728 device_printf(sc_if->sk_if_dev,
3729 "can not stop transfer of Rx descriptor\n");
3730
3731 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3732 /* Put PHY back into reset. */
3733 val = sk_win_read_4(sc, SK_GPIO);
3734 if (sc_if->sk_port == SK_PORT_A) {
3735 val |= SK_GPIO_DIR0;
3736 val &= ~SK_GPIO_DAT0;
3737 } else {
3738 val |= SK_GPIO_DIR2;
3739 val &= ~SK_GPIO_DAT2;
3740 }
3741 sk_win_write_4(sc, SK_GPIO, val);
3742 }
3743
3744 /* Turn off various components of this interface. */
3745 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3746 switch (sc->sk_type) {
3747 case SK_GENESIS:
3748 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3749 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3750 break;
3751 case SK_YUKON:
3752 case SK_YUKON_LITE:
3753 case SK_YUKON_LP:
3754 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3755 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3756 break;
3757 }
3758 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3759 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3760 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3761 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3762 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3763 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3764 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3765 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3766 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3767
3768 /* Disable interrupts */
3769 if (sc_if->sk_port == SK_PORT_A)
3770 sc->sk_intrmask &= ~SK_INTRS1;
3771 else
3772 sc->sk_intrmask &= ~SK_INTRS2;
3773 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3774
3775 SK_XM_READ_2(sc_if, XM_ISR);
3776 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3777
3778 /* Free RX and TX mbufs still in the queues. */
3779 for (i = 0; i < SK_RX_RING_CNT; i++) {
3780 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3781 if (rxd->rx_m != NULL) {
3782 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3783 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3784 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3785 rxd->rx_dmamap);
3786 m_freem(rxd->rx_m);
3787 rxd->rx_m = NULL;
3788 }
3789 }
3790 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3791 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3792 if (jrxd->rx_m != NULL) {
3793 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3794 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3795 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3796 jrxd->rx_dmamap);
3797 m_freem(jrxd->rx_m);
3798 jrxd->rx_m = NULL;
3799 }
3800 }
3801 for (i = 0; i < SK_TX_RING_CNT; i++) {
3802 txd = &sc_if->sk_cdata.sk_txdesc[i];
3803 if (txd->tx_m != NULL) {
3804 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3805 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3806 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3807 txd->tx_dmamap);
3808 m_freem(txd->tx_m);
3809 txd->tx_m = NULL;
3810 }
3811 }
3812
3813 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3814
3815 return;
3816 }
3817
3818 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3819 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3820 {
3821 int error, value;
3822
3823 if (!arg1)
3824 return (EINVAL);
3825 value = *(int *)arg1;
3826 error = sysctl_handle_int(oidp, &value, 0, req);
3827 if (error || !req->newptr)
3828 return (error);
3829 if (value < low || value > high)
3830 return (EINVAL);
3831 *(int *)arg1 = value;
3832 return (0);
3833 }
3834
3835 static int
sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)3836 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3837 {
3838 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3839 }
3840