1 /*-
2 * Copyright (c) 2000-03 ICP vortex GmbH
3 * Copyright (c) 2002-03 Intel Corporation
4 * Copyright (c) 2003 Adaptec Inc.
5 * All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 /*
36 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver
37 *
38 * Written by: Achim Leubner <achim.leubner@intel.com>
39 * Written by: Achim Leubner <achim_leubner@adaptec.com>
40 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
41 *
42 * TODO:
43 */
44
45 /* #include "opt_iir.h" */
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/endian.h>
50 #include <sys/kernel.h>
51 #include <sys/lock.h>
52 #include <sys/mutex.h>
53 #include <sys/module.h>
54 #include <sys/bus.h>
55
56 #include <machine/bus.h>
57 #include <machine/resource.h>
58 #include <sys/rman.h>
59
60 #include <dev/pci/pcireg.h>
61 #include <dev/pci/pcivar.h>
62
63 #include <cam/scsi/scsi_all.h>
64
65 #include <dev/iir/iir.h>
66
67 /* Mapping registers for various areas */
68 #define PCI_DPMEM PCIR_BAR(0)
69
70 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
71 #define GDT_PCI_PRODUCT_FC 0x200
72
73 /* PCI SRAM structure */
74 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */
75 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */
76 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
77 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */
78 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */
79 #define GDT_SRAM_SZ 0x40
80
81 /* DPRAM PCI controllers */
82 #define GDT_DPR_IF 0x00 /* interface area */
83 #define GDT_6SR (0xff0 - GDT_SRAM_SZ)
84 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */
85 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */
86 #define GDT_EVENT 0xff8 /* u_int8_t, release event */
87 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */
88 #define GDT_DPRAM_SZ 0x1000
89
90 /* PLX register structure (new PCI controllers) */
91 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
92 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */
93 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */
94 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */
95 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */
96 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */
97 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */
98 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */
99 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */
100 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */
101 #define GDT_PLX_SZ 0x80
102
103 /* DPRAM new PCI controllers */
104 #define GDT_IC 0x00 /* interface */
105 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ)
106 /* SRAM structure */
107 #define GDT_PCINEW_SZ 0x4000
108
109 /* i960 register structure (PCI MPR controllers) */
110 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */
111 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */
112 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */
113 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */
114 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */
115 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */
116 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */
117 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */
118 #define GDT_SEVERITY 0xefc /* u_int8_t, event severity */
119 #define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */
120 #define GDT_I960_SZ 0x1000
121
122 /* DPRAM PCI MPR controllers */
123 #define GDT_I960R 0x00 /* 4KB i960 registers */
124 #define GDT_MPR_IC GDT_I960_SZ
125 /* i960 register area */
126 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
127 /* DPRAM struct. */
128 #define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ)
129
130 static int iir_pci_probe(device_t dev);
131 static int iir_pci_attach(device_t dev);
132
133 void gdt_pci_enable_intr(struct gdt_softc *);
134
135 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
136 u_int8_t gdt_mpr_get_status(struct gdt_softc *);
137 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
138 void gdt_mpr_release_event(struct gdt_softc *);
139 void gdt_mpr_set_sema0(struct gdt_softc *);
140 int gdt_mpr_test_busy(struct gdt_softc *);
141
142 static device_method_t iir_pci_methods[] = {
143 /* Device interface */
144 DEVMETHOD(device_probe, iir_pci_probe),
145 DEVMETHOD(device_attach, iir_pci_attach),
146 { 0, 0}
147 };
148
149
150 static driver_t iir_pci_driver =
151 {
152 "iir",
153 iir_pci_methods,
154 sizeof(struct gdt_softc)
155 };
156
157 static devclass_t iir_devclass;
158
159 DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0);
160 MODULE_DEPEND(iir, pci, 1, 1, 1);
161 MODULE_DEPEND(iir, cam, 1, 1, 1);
162
163 static int
iir_pci_probe(device_t dev)164 iir_pci_probe(device_t dev)
165 {
166 if (pci_get_vendor(dev) == INTEL_VENDOR_ID_IIR &&
167 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) {
168 device_set_desc(dev, "Intel Integrated RAID Controller");
169 return (BUS_PROBE_DEFAULT);
170 }
171 if (pci_get_vendor(dev) == GDT_VENDOR_ID &&
172 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN &&
173 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) ||
174 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) {
175 device_set_desc(dev, "ICP Disk Array Controller");
176 return (BUS_PROBE_DEFAULT);
177 }
178 return (ENXIO);
179 }
180
181
182 static int
iir_pci_attach(device_t dev)183 iir_pci_attach(device_t dev)
184 {
185 struct gdt_softc *gdt;
186 struct resource *irq = NULL;
187 int retries, rid, error = 0;
188 void *ih;
189 u_int8_t protocol;
190
191 gdt = device_get_softc(dev);
192 mtx_init(&gdt->sc_lock, "iir", NULL, MTX_DEF);
193
194 /* map DPMEM */
195 rid = PCI_DPMEM;
196 gdt->sc_dpmem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
197 if (gdt->sc_dpmem == NULL) {
198 device_printf(dev, "can't allocate register resources\n");
199 error = ENOMEM;
200 goto err;
201 }
202
203 /* get IRQ */
204 rid = 0;
205 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
206 RF_ACTIVE | RF_SHAREABLE);
207 if (irq == NULL) {
208 device_printf(dev, "can't find IRQ value\n");
209 error = ENOMEM;
210 goto err;
211 }
212
213 gdt->sc_devnode = dev;
214 gdt->sc_init_level = 0;
215 gdt->sc_hanum = device_get_unit(dev);
216 gdt->sc_bus = pci_get_bus(dev);
217 gdt->sc_slot = pci_get_slot(dev);
218 gdt->sc_vendor = pci_get_vendor(dev);
219 gdt->sc_device = pci_get_device(dev);
220 gdt->sc_subdevice = pci_get_subdevice(dev);
221 gdt->sc_class = GDT_MPR;
222 /* no FC ctr.
223 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
224 gdt->sc_class |= GDT_FC;
225 */
226
227 /* initialize RP controller */
228 /* check and reset interface area */
229 bus_write_4(gdt->sc_dpmem, GDT_MPR_IC, htole32(GDT_MPR_MAGIC));
230 if (bus_read_4(gdt->sc_dpmem, GDT_MPR_IC) != htole32(GDT_MPR_MAGIC)) {
231 device_printf(dev, "cannot access DPMEM at 0x%jx (shadowed?)\n",
232 rman_get_start(gdt->sc_dpmem));
233 error = ENXIO;
234 goto err;
235 }
236 bus_set_region_4(gdt->sc_dpmem, GDT_I960_SZ, htole32(0), GDT_MPR_SZ >> 2);
237
238 /* Disable everything */
239 bus_write_1(gdt->sc_dpmem, GDT_EDOOR_EN,
240 bus_read_1(gdt->sc_dpmem, GDT_EDOOR_EN) | 4);
241 bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
242 bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS, 0);
243 bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_CMD_INDEX, 0);
244
245 bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO,
246 htole32(rman_get_start(gdt->sc_dpmem)));
247 bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_CMD_INDX, 0xff);
248 bus_write_1(gdt->sc_dpmem, GDT_MPR_LDOOR, 1);
249
250 DELAY(20);
251 retries = GDT_RETRIES;
252 while (bus_read_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
253 if (--retries == 0) {
254 device_printf(dev, "DEINIT failed\n");
255 error = ENXIO;
256 goto err;
257 }
258 DELAY(1);
259 }
260
261 protocol = (uint8_t)le32toh(bus_read_4(gdt->sc_dpmem,
262 GDT_MPR_IC + GDT_S_INFO));
263 bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS, 0);
264 if (protocol != GDT_PROTOCOL_VERSION) {
265 device_printf(dev, "unsupported protocol %d\n", protocol);
266 error = ENXIO;
267 goto err;
268 }
269
270 /* special command to controller BIOS */
271 bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO, htole32(0));
272 bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t),
273 htole32(0));
274 bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
275 htole32(1));
276 bus_write_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
277 htole32(0));
278 bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_CMD_INDX, 0xfe);
279 bus_write_1(gdt->sc_dpmem, GDT_MPR_LDOOR, 1);
280
281 DELAY(20);
282 retries = GDT_RETRIES;
283 while (bus_read_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
284 if (--retries == 0) {
285 device_printf(dev, "initialization error\n");
286 error = ENXIO;
287 goto err;
288 }
289 DELAY(1);
290 }
291
292 bus_write_1(gdt->sc_dpmem, GDT_MPR_IC + GDT_S_STATUS, 0);
293
294 gdt->sc_ic_all_size = GDT_MPR_SZ;
295
296 gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
297 gdt->sc_get_status = gdt_mpr_get_status;
298 gdt->sc_intr = gdt_mpr_intr;
299 gdt->sc_release_event = gdt_mpr_release_event;
300 gdt->sc_set_sema0 = gdt_mpr_set_sema0;
301 gdt->sc_test_busy = gdt_mpr_test_busy;
302
303 /* Allocate a dmatag representing the capabilities of this attachment */
304 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev),
305 /*alignemnt*/1, /*boundary*/0,
306 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
307 /*highaddr*/BUS_SPACE_MAXADDR,
308 /*filter*/NULL, /*filterarg*/NULL,
309 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
310 /*nsegments*/BUS_SPACE_UNRESTRICTED,
311 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
312 /*flags*/0, /*lockfunc*/busdma_lock_mutex,
313 /*lockarg*/&gdt->sc_lock, &gdt->sc_parent_dmat) != 0) {
314 error = ENXIO;
315 goto err;
316 }
317 gdt->sc_init_level++;
318
319 if (iir_init(gdt) != 0) {
320 iir_free(gdt);
321 error = ENXIO;
322 goto err;
323 }
324
325 /* Register with the XPT */
326 iir_attach(gdt);
327
328 /* associate interrupt handler */
329 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM | INTR_MPSAFE,
330 NULL, iir_intr, gdt, &ih )) {
331 device_printf(dev, "Unable to register interrupt handler\n");
332 error = ENXIO;
333 goto err;
334 }
335
336 gdt_pci_enable_intr(gdt);
337 return (0);
338
339 err:
340 if (irq)
341 bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
342
343 if (gdt->sc_dpmem)
344 bus_release_resource( dev, SYS_RES_MEMORY, rid, gdt->sc_dpmem );
345 mtx_destroy(&gdt->sc_lock);
346
347 return (error);
348 }
349
350
351 /* Enable interrupts */
352 void
gdt_pci_enable_intr(struct gdt_softc * gdt)353 gdt_pci_enable_intr(struct gdt_softc *gdt)
354 {
355 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
356
357 switch(GDT_CLASS(gdt)) {
358 case GDT_MPR:
359 bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
360 bus_write_1(gdt->sc_dpmem, GDT_EDOOR_EN,
361 bus_read_1(gdt->sc_dpmem, GDT_EDOOR_EN) & ~4);
362 break;
363 }
364 }
365
366
367 /*
368 * MPR PCI controller-specific functions
369 */
370
371 void
gdt_mpr_copy_cmd(struct gdt_softc * gdt,struct gdt_ccb * gccb)372 gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *gccb)
373 {
374 u_int16_t cp_count = roundup(gccb->gc_cmd_len, sizeof (u_int32_t));
375 u_int16_t dp_offset = gdt->sc_cmd_off;
376 u_int16_t cmd_no = gdt->sc_cmd_cnt++;
377
378 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
379
380 gdt->sc_cmd_off += cp_count;
381
382 bus_write_region_4(gdt->sc_dpmem, GDT_MPR_IC + GDT_DPR_CMD + dp_offset,
383 (u_int32_t *)gccb->gc_cmd, cp_count >> 2);
384 bus_write_2(gdt->sc_dpmem,
385 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
386 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset));
387 bus_write_2(gdt->sc_dpmem,
388 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
389 htole16(gccb->gc_service));
390 }
391
392 u_int8_t
gdt_mpr_get_status(struct gdt_softc * gdt)393 gdt_mpr_get_status(struct gdt_softc *gdt)
394 {
395 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
396
397 return bus_read_1(gdt->sc_dpmem, GDT_MPR_EDOOR);
398 }
399
400 void
gdt_mpr_intr(struct gdt_softc * gdt,struct gdt_intr_ctx * ctx)401 gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
402 {
403 int i;
404
405 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
406
407 bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
408
409 if (ctx->istatus & 0x80) { /* error flag */
410 ctx->istatus &= ~0x80;
411 ctx->cmd_status = bus_read_2(gdt->sc_dpmem, GDT_MPR_STATUS);
412 } else /* no error */
413 ctx->cmd_status = GDT_S_OK;
414
415 ctx->info = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO);
416 ctx->service = bus_read_2(gdt->sc_dpmem, GDT_MPR_SERVICE);
417 ctx->info2 = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO + sizeof (u_int32_t));
418
419 /* event string */
420 if (ctx->istatus == GDT_ASYNCINDEX) {
421 if (ctx->service != GDT_SCREENSERVICE &&
422 (gdt->sc_fw_vers & 0xff) >= 0x1a) {
423 gdt->sc_dvr.severity = bus_read_1(gdt->sc_dpmem, GDT_SEVERITY);
424 for (i = 0; i < 256; ++i) {
425 gdt->sc_dvr.event_string[i] = bus_read_1(gdt->sc_dpmem,
426 GDT_EVT_BUF + i);
427 if (gdt->sc_dvr.event_string[i] == 0)
428 break;
429 }
430 }
431 }
432 bus_write_1(gdt->sc_dpmem, GDT_MPR_SEMA1, 0);
433 }
434
435 void
gdt_mpr_release_event(struct gdt_softc * gdt)436 gdt_mpr_release_event(struct gdt_softc *gdt)
437 {
438 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
439
440 bus_write_1(gdt->sc_dpmem, GDT_MPR_LDOOR, 1);
441 }
442
443 void
gdt_mpr_set_sema0(struct gdt_softc * gdt)444 gdt_mpr_set_sema0(struct gdt_softc *gdt)
445 {
446 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
447
448 bus_write_1(gdt->sc_dpmem, GDT_MPR_SEMA0, 1);
449 }
450
451 int
gdt_mpr_test_busy(struct gdt_softc * gdt)452 gdt_mpr_test_busy(struct gdt_softc *gdt)
453 {
454 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
455
456 return (bus_read_1(gdt->sc_dpmem, GDT_MPR_SEMA0) & 1);
457 }
458