1 /*- 2 * Copyright (c) 1998, 2001 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 #ifndef __IICONF_H 29 #define __IICONF_H 30 31 #include <sys/queue.h> 32 #include <dev/iicbus/iic.h> 33 34 35 #define IICPRI (PZERO+8) /* XXX sleep/wakeup queue priority */ 36 37 #define LSB 0x1 38 39 /* 40 * Options affecting iicbus_request_bus() 41 */ 42 #define IIC_DONTWAIT 0 43 #define IIC_NOINTR 0 44 #define IIC_WAIT 0x1 45 #define IIC_INTR 0x2 46 #define IIC_INTRWAIT (IIC_INTR | IIC_WAIT) 47 #define IIC_RECURSIVE 0x4 48 49 /* 50 * i2c modes 51 */ 52 #define IIC_MASTER 0x1 53 #define IIC_SLAVE 0x2 54 #define IIC_POLLED 0x4 55 56 /* 57 * i2c speed 58 */ 59 #define IIC_UNKNOWN 0x0 60 #define IIC_SLOW 0x1 61 #define IIC_FAST 0x2 62 #define IIC_FASTEST 0x3 63 64 #define IIC_LAST_READ 0x1 65 66 /* 67 * callback index 68 */ 69 #define IIC_REQUEST_BUS 0x1 70 #define IIC_RELEASE_BUS 0x2 71 72 /* 73 * interrupt events 74 */ 75 #define INTR_GENERAL 0x1 /* general call received */ 76 #define INTR_START 0x2 /* the I2C interface is addressed */ 77 #define INTR_STOP 0x3 /* stop condition received */ 78 #define INTR_RECEIVE 0x4 /* character received */ 79 #define INTR_TRANSMIT 0x5 /* character to transmit */ 80 #define INTR_ERROR 0x6 /* error */ 81 #define INTR_NOACK 0x7 /* no ack from master receiver */ 82 83 /* 84 * adapter layer errors 85 */ 86 #define IIC_NOERR 0x0 /* no error occurred */ 87 #define IIC_EBUSERR 0x1 /* bus error (hardware not in expected state) */ 88 #define IIC_ENOACK 0x2 /* ack not received until timeout */ 89 #define IIC_ETIMEOUT 0x3 /* timeout */ 90 #define IIC_EBUSBSY 0x4 /* bus busy (reserved by another client) */ 91 #define IIC_ESTATUS 0x5 /* status error */ 92 #define IIC_EUNDERFLOW 0x6 /* slave ready for more data */ 93 #define IIC_EOVERFLOW 0x7 /* too much data */ 94 #define IIC_ENOTSUPP 0x8 /* request not supported */ 95 #define IIC_ENOADDR 0x9 /* no address assigned to the interface */ 96 #define IIC_ERESOURCE 0xa /* resources (memory, whatever) unavailable */ 97 98 /* 99 * Note that all iicbus functions return IIC_Exxxxx status values, 100 * except iic2errno() (obviously) and iicbus_started() (returns bool). 101 */ 102 extern int iic2errno(int); 103 extern int iicbus_request_bus(device_t, device_t, int); 104 extern int iicbus_release_bus(device_t, device_t); 105 extern device_t iicbus_alloc_bus(device_t); 106 107 extern void iicbus_intr(device_t, int, char *); 108 109 extern int iicbus_null_repeated_start(device_t, u_char); 110 extern int iicbus_null_callback(device_t, int, caddr_t); 111 112 #define iicbus_reset(bus,speed,addr,oldaddr) \ 113 (IICBUS_RESET(device_get_parent(bus), speed, addr, oldaddr)) 114 115 /* basic I2C operations */ 116 extern int iicbus_started(device_t); 117 extern int iicbus_start(device_t, u_char, int); 118 extern int iicbus_stop(device_t); 119 extern int iicbus_repeated_start(device_t, u_char, int); 120 extern int iicbus_write(device_t, const char *, int, int *, int); 121 extern int iicbus_read(device_t, char *, int, int *, int, int); 122 123 /* single byte read/write functions, start/stop not managed */ 124 extern int iicbus_write_byte(device_t, char, int); 125 extern int iicbus_read_byte(device_t, char *, int); 126 127 /* Read/write operations with start/stop conditions managed */ 128 extern int iicbus_block_write(device_t, u_char, char *, int, int *); 129 extern int iicbus_block_read(device_t, u_char, char *, int, int *); 130 131 /* vectors of iic operations to pass to bridge */ 132 int iicbus_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs); 133 int iicbus_transfer_excl(device_t bus, struct iic_msg *msgs, uint32_t nmsgs, 134 int how); 135 int iicbus_transfer_gen(device_t bus, struct iic_msg *msgs, uint32_t nmsgs); 136 137 /* 138 * Simple register read/write routines, but the "register" can be any size. 139 * The transfers are done with iicbus_transfer_excl(). Reads use a repeat-start 140 * between sending the address and reading; writes use a single start/stop. 141 */ 142 int iicdev_readfrom(device_t _slavedev, uint8_t _regaddr, void *_buffer, 143 uint16_t _buflen, int _waithow); 144 int iicdev_writeto(device_t _slavedev, uint8_t _regaddr, void *_buffer, 145 uint16_t _buflen, int _waithow); 146 147 #define IICBUS_MODVER 1 148 #define IICBUS_MINVER 1 149 #define IICBUS_MAXVER 1 150 #define IICBUS_PREFVER IICBUS_MODVER 151 152 extern driver_t iicbb_driver; 153 extern devclass_t iicbb_devclass; 154 155 #define IICBB_MODVER 1 156 #define IICBB_MINVER 1 157 #define IICBB_MAXVER 1 158 #define IICBB_PREFVER IICBB_MODVER 159 160 #endif 161