1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <dev/drm2/drmP.h>
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "atom.h"
36 #include "rs690d.h"
37
rs690_mc_wait_for_idle(struct radeon_device * rdev)38 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
39 {
40 unsigned i;
41 uint32_t tmp;
42
43 for (i = 0; i < rdev->usec_timeout; i++) {
44 /* read MC_STATUS */
45 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
46 if (G_000090_MC_SYSTEM_IDLE(tmp))
47 return 0;
48 udelay(1);
49 }
50 return -1;
51 }
52
rs690_gpu_init(struct radeon_device * rdev)53 static void rs690_gpu_init(struct radeon_device *rdev)
54 {
55 /* FIXME: is this correct ? */
56 r420_pipes_init(rdev);
57 if (rs690_mc_wait_for_idle(rdev)) {
58 DRM_ERROR("Failed to wait MC idle while "
59 "programming pipes. Bad things might happen.\n");
60 }
61 }
62
63 union igp_info {
64 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
65 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
66 };
67
rs690_pm_info(struct radeon_device * rdev)68 void rs690_pm_info(struct radeon_device *rdev)
69 {
70 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
71 union igp_info *info;
72 uint16_t data_offset;
73 uint8_t frev, crev;
74 fixed20_12 tmp;
75
76 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
77 &frev, &crev, &data_offset)) {
78 info = (union igp_info *)((uintptr_t)rdev->mode_info.atom_context->bios + data_offset);
79
80 /* Get various system informations from bios */
81 switch (crev) {
82 case 1:
83 tmp.full = dfixed_const(100);
84 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
85 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
86 if (le16_to_cpu(info->info.usK8MemoryClock))
87 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
88 else if (rdev->clock.default_mclk) {
89 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
90 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
91 } else
92 rdev->pm.igp_system_mclk.full = dfixed_const(400);
93 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
94 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
95 break;
96 case 2:
97 tmp.full = dfixed_const(100);
98 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
99 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
100 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
101 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
102 else if (rdev->clock.default_mclk)
103 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
104 else
105 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
106 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
107 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
108 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
109 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
110 break;
111 default:
112 /* We assume the slower possible clock ie worst case */
113 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
114 rdev->pm.igp_system_mclk.full = dfixed_const(200);
115 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
116 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
117 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
118 break;
119 }
120 } else {
121 /* We assume the slower possible clock ie worst case */
122 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
123 rdev->pm.igp_system_mclk.full = dfixed_const(200);
124 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
125 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
126 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
127 }
128 /* Compute various bandwidth */
129 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
130 tmp.full = dfixed_const(4);
131 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
132 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
133 * = ht_clk * ht_width / 5
134 */
135 tmp.full = dfixed_const(5);
136 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
137 rdev->pm.igp_ht_link_width);
138 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
139 if (tmp.full < rdev->pm.max_bandwidth.full) {
140 /* HT link is a limiting factor */
141 rdev->pm.max_bandwidth.full = tmp.full;
142 }
143 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
144 * = (sideport_clk * 14) / 10
145 */
146 tmp.full = dfixed_const(14);
147 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
148 tmp.full = dfixed_const(10);
149 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
150 }
151
rs690_mc_init(struct radeon_device * rdev)152 static void rs690_mc_init(struct radeon_device *rdev)
153 {
154 u64 base;
155
156 rs400_gart_adjust_size(rdev);
157 rdev->mc.vram_is_ddr = true;
158 rdev->mc.vram_width = 128;
159 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
160 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
161 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
162 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
163 rdev->mc.visible_vram_size = rdev->mc.aper_size;
164 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
165 base = G_000100_MC_FB_START(base) << 16;
166 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
167 rs690_pm_info(rdev);
168 radeon_vram_location(rdev, &rdev->mc, base);
169 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
170 radeon_gtt_location(rdev, &rdev->mc);
171 radeon_update_bandwidth_info(rdev);
172 }
173
rs690_line_buffer_adjust(struct radeon_device * rdev,struct drm_display_mode * mode1,struct drm_display_mode * mode2)174 void rs690_line_buffer_adjust(struct radeon_device *rdev,
175 struct drm_display_mode *mode1,
176 struct drm_display_mode *mode2)
177 {
178 u32 tmp;
179
180 /*
181 * Line Buffer Setup
182 * There is a single line buffer shared by both display controllers.
183 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
184 * the display controllers. The paritioning can either be done
185 * manually or via one of four preset allocations specified in bits 1:0:
186 * 0 - line buffer is divided in half and shared between crtc
187 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
188 * 2 - D1 gets the whole buffer
189 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
190 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
191 * allocation mode. In manual allocation mode, D1 always starts at 0,
192 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
193 */
194 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
195 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
196 /* auto */
197 if (mode1 && mode2) {
198 if (mode1->hdisplay > mode2->hdisplay) {
199 if (mode1->hdisplay > 2560)
200 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
201 else
202 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
203 } else if (mode2->hdisplay > mode1->hdisplay) {
204 if (mode2->hdisplay > 2560)
205 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
206 else
207 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
208 } else
209 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
210 } else if (mode1) {
211 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
212 } else if (mode2) {
213 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
214 }
215 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
216 }
217
218 struct rs690_watermark {
219 u32 lb_request_fifo_depth;
220 fixed20_12 num_line_pair;
221 fixed20_12 estimated_width;
222 fixed20_12 worst_case_latency;
223 fixed20_12 consumption_rate;
224 fixed20_12 active_time;
225 fixed20_12 dbpp;
226 fixed20_12 priority_mark_max;
227 fixed20_12 priority_mark;
228 fixed20_12 sclk;
229 };
230
rs690_crtc_bandwidth_compute(struct radeon_device * rdev,struct radeon_crtc * crtc,struct rs690_watermark * wm)231 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
232 struct radeon_crtc *crtc,
233 struct rs690_watermark *wm)
234 {
235 struct drm_display_mode *mode = &crtc->base.mode;
236 fixed20_12 a, b, c;
237 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
238 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
239
240 if (!crtc->base.enabled) {
241 /* FIXME: wouldn't it better to set priority mark to maximum */
242 wm->lb_request_fifo_depth = 4;
243 return;
244 }
245
246 if (crtc->vsc.full > dfixed_const(2))
247 wm->num_line_pair.full = dfixed_const(2);
248 else
249 wm->num_line_pair.full = dfixed_const(1);
250
251 b.full = dfixed_const(mode->crtc_hdisplay);
252 c.full = dfixed_const(256);
253 a.full = dfixed_div(b, c);
254 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
255 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
256 if (a.full < dfixed_const(4)) {
257 wm->lb_request_fifo_depth = 4;
258 } else {
259 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
260 }
261
262 /* Determine consumption rate
263 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
264 * vtaps = number of vertical taps,
265 * vsc = vertical scaling ratio, defined as source/destination
266 * hsc = horizontal scaling ration, defined as source/destination
267 */
268 a.full = dfixed_const(mode->clock);
269 b.full = dfixed_const(1000);
270 a.full = dfixed_div(a, b);
271 pclk.full = dfixed_div(b, a);
272 if (crtc->rmx_type != RMX_OFF) {
273 b.full = dfixed_const(2);
274 if (crtc->vsc.full > b.full)
275 b.full = crtc->vsc.full;
276 b.full = dfixed_mul(b, crtc->hsc);
277 c.full = dfixed_const(2);
278 b.full = dfixed_div(b, c);
279 consumption_time.full = dfixed_div(pclk, b);
280 } else {
281 consumption_time.full = pclk.full;
282 }
283 a.full = dfixed_const(1);
284 wm->consumption_rate.full = dfixed_div(a, consumption_time);
285
286
287 /* Determine line time
288 * LineTime = total time for one line of displayhtotal
289 * LineTime = total number of horizontal pixels
290 * pclk = pixel clock period(ns)
291 */
292 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
293 line_time.full = dfixed_mul(a, pclk);
294
295 /* Determine active time
296 * ActiveTime = time of active region of display within one line,
297 * hactive = total number of horizontal active pixels
298 * htotal = total number of horizontal pixels
299 */
300 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
301 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
302 wm->active_time.full = dfixed_mul(line_time, b);
303 wm->active_time.full = dfixed_div(wm->active_time, a);
304
305 /* Maximun bandwidth is the minimun bandwidth of all component */
306 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
307 if (rdev->mc.igp_sideport_enabled) {
308 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
309 rdev->pm.sideport_bandwidth.full)
310 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
311 read_delay_latency.full = dfixed_const(370 * 800);
312 a.full = dfixed_const(1000);
313 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
314 read_delay_latency.full = dfixed_div(read_delay_latency, b);
315 read_delay_latency.full = dfixed_mul(read_delay_latency, a);
316 } else {
317 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
318 rdev->pm.k8_bandwidth.full)
319 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
320 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
321 rdev->pm.ht_bandwidth.full)
322 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
323 read_delay_latency.full = dfixed_const(5000);
324 }
325
326 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
327 a.full = dfixed_const(16);
328 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
329 a.full = dfixed_const(1000);
330 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
331 /* Determine chunk time
332 * ChunkTime = the time it takes the DCP to send one chunk of data
333 * to the LB which consists of pipeline delay and inter chunk gap
334 * sclk = system clock(ns)
335 */
336 a.full = dfixed_const(256 * 13);
337 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
338 a.full = dfixed_const(10);
339 chunk_time.full = dfixed_div(chunk_time, a);
340
341 /* Determine the worst case latency
342 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
343 * WorstCaseLatency = worst case time from urgent to when the MC starts
344 * to return data
345 * READ_DELAY_IDLE_MAX = constant of 1us
346 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
347 * which consists of pipeline delay and inter chunk gap
348 */
349 if (dfixed_trunc(wm->num_line_pair) > 1) {
350 a.full = dfixed_const(3);
351 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
352 wm->worst_case_latency.full += read_delay_latency.full;
353 } else {
354 a.full = dfixed_const(2);
355 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
356 wm->worst_case_latency.full += read_delay_latency.full;
357 }
358
359 /* Determine the tolerable latency
360 * TolerableLatency = Any given request has only 1 line time
361 * for the data to be returned
362 * LBRequestFifoDepth = Number of chunk requests the LB can
363 * put into the request FIFO for a display
364 * LineTime = total time for one line of display
365 * ChunkTime = the time it takes the DCP to send one chunk
366 * of data to the LB which consists of
367 * pipeline delay and inter chunk gap
368 */
369 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
370 tolerable_latency.full = line_time.full;
371 } else {
372 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
373 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
374 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
375 tolerable_latency.full = line_time.full - tolerable_latency.full;
376 }
377 /* We assume worst case 32bits (4 bytes) */
378 wm->dbpp.full = dfixed_const(4 * 8);
379
380 /* Determine the maximum priority mark
381 * width = viewport width in pixels
382 */
383 a.full = dfixed_const(16);
384 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
385 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
386 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
387
388 /* Determine estimated width */
389 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
390 estimated_width.full = dfixed_div(estimated_width, consumption_time);
391 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
392 wm->priority_mark.full = dfixed_const(10);
393 } else {
394 a.full = dfixed_const(16);
395 wm->priority_mark.full = dfixed_div(estimated_width, a);
396 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
397 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
398 }
399 }
400
rs690_bandwidth_update(struct radeon_device * rdev)401 void rs690_bandwidth_update(struct radeon_device *rdev)
402 {
403 struct drm_display_mode *mode0 = NULL;
404 struct drm_display_mode *mode1 = NULL;
405 struct rs690_watermark wm0;
406 struct rs690_watermark wm1;
407 u32 tmp;
408 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
409 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
410 fixed20_12 priority_mark02, priority_mark12, fill_rate;
411 fixed20_12 a, b;
412
413 radeon_update_display_priority(rdev);
414
415 if (rdev->mode_info.crtcs[0]->base.enabled)
416 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
417 if (rdev->mode_info.crtcs[1]->base.enabled)
418 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
419 /*
420 * Set display0/1 priority up in the memory controller for
421 * modes if the user specifies HIGH for displaypriority
422 * option.
423 */
424 if ((rdev->disp_priority == 2) &&
425 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
426 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
427 tmp &= C_000104_MC_DISP0R_INIT_LAT;
428 tmp &= C_000104_MC_DISP1R_INIT_LAT;
429 if (mode0)
430 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
431 if (mode1)
432 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
433 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
434 }
435 rs690_line_buffer_adjust(rdev, mode0, mode1);
436
437 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
438 WREG32(R_006C9C_DCP_CONTROL, 0);
439 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
440 WREG32(R_006C9C_DCP_CONTROL, 2);
441
442 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
443 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
444
445 tmp = (wm0.lb_request_fifo_depth - 1);
446 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
447 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
448
449 if (mode0 && mode1) {
450 if (dfixed_trunc(wm0.dbpp) > 64)
451 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
452 else
453 a.full = wm0.num_line_pair.full;
454 if (dfixed_trunc(wm1.dbpp) > 64)
455 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
456 else
457 b.full = wm1.num_line_pair.full;
458 a.full += b.full;
459 fill_rate.full = dfixed_div(wm0.sclk, a);
460 if (wm0.consumption_rate.full > fill_rate.full) {
461 b.full = wm0.consumption_rate.full - fill_rate.full;
462 b.full = dfixed_mul(b, wm0.active_time);
463 a.full = dfixed_mul(wm0.worst_case_latency,
464 wm0.consumption_rate);
465 a.full = a.full + b.full;
466 b.full = dfixed_const(16 * 1000);
467 priority_mark02.full = dfixed_div(a, b);
468 } else {
469 a.full = dfixed_mul(wm0.worst_case_latency,
470 wm0.consumption_rate);
471 b.full = dfixed_const(16 * 1000);
472 priority_mark02.full = dfixed_div(a, b);
473 }
474 if (wm1.consumption_rate.full > fill_rate.full) {
475 b.full = wm1.consumption_rate.full - fill_rate.full;
476 b.full = dfixed_mul(b, wm1.active_time);
477 a.full = dfixed_mul(wm1.worst_case_latency,
478 wm1.consumption_rate);
479 a.full = a.full + b.full;
480 b.full = dfixed_const(16 * 1000);
481 priority_mark12.full = dfixed_div(a, b);
482 } else {
483 a.full = dfixed_mul(wm1.worst_case_latency,
484 wm1.consumption_rate);
485 b.full = dfixed_const(16 * 1000);
486 priority_mark12.full = dfixed_div(a, b);
487 }
488 if (wm0.priority_mark.full > priority_mark02.full)
489 priority_mark02.full = wm0.priority_mark.full;
490 if (wm0.priority_mark_max.full > priority_mark02.full)
491 priority_mark02.full = wm0.priority_mark_max.full;
492 if (wm1.priority_mark.full > priority_mark12.full)
493 priority_mark12.full = wm1.priority_mark.full;
494 if (wm1.priority_mark_max.full > priority_mark12.full)
495 priority_mark12.full = wm1.priority_mark_max.full;
496 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
497 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
498 if (rdev->disp_priority == 2) {
499 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
500 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
501 }
502 } else if (mode0) {
503 if (dfixed_trunc(wm0.dbpp) > 64)
504 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
505 else
506 a.full = wm0.num_line_pair.full;
507 fill_rate.full = dfixed_div(wm0.sclk, a);
508 if (wm0.consumption_rate.full > fill_rate.full) {
509 b.full = wm0.consumption_rate.full - fill_rate.full;
510 b.full = dfixed_mul(b, wm0.active_time);
511 a.full = dfixed_mul(wm0.worst_case_latency,
512 wm0.consumption_rate);
513 a.full = a.full + b.full;
514 b.full = dfixed_const(16 * 1000);
515 priority_mark02.full = dfixed_div(a, b);
516 } else {
517 a.full = dfixed_mul(wm0.worst_case_latency,
518 wm0.consumption_rate);
519 b.full = dfixed_const(16 * 1000);
520 priority_mark02.full = dfixed_div(a, b);
521 }
522 if (wm0.priority_mark.full > priority_mark02.full)
523 priority_mark02.full = wm0.priority_mark.full;
524 if (wm0.priority_mark_max.full > priority_mark02.full)
525 priority_mark02.full = wm0.priority_mark_max.full;
526 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
527 if (rdev->disp_priority == 2)
528 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
529 } else if (mode1) {
530 if (dfixed_trunc(wm1.dbpp) > 64)
531 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
532 else
533 a.full = wm1.num_line_pair.full;
534 fill_rate.full = dfixed_div(wm1.sclk, a);
535 if (wm1.consumption_rate.full > fill_rate.full) {
536 b.full = wm1.consumption_rate.full - fill_rate.full;
537 b.full = dfixed_mul(b, wm1.active_time);
538 a.full = dfixed_mul(wm1.worst_case_latency,
539 wm1.consumption_rate);
540 a.full = a.full + b.full;
541 b.full = dfixed_const(16 * 1000);
542 priority_mark12.full = dfixed_div(a, b);
543 } else {
544 a.full = dfixed_mul(wm1.worst_case_latency,
545 wm1.consumption_rate);
546 b.full = dfixed_const(16 * 1000);
547 priority_mark12.full = dfixed_div(a, b);
548 }
549 if (wm1.priority_mark.full > priority_mark12.full)
550 priority_mark12.full = wm1.priority_mark.full;
551 if (wm1.priority_mark_max.full > priority_mark12.full)
552 priority_mark12.full = wm1.priority_mark_max.full;
553 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
554 if (rdev->disp_priority == 2)
555 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
556 }
557
558 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
559 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
560 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
561 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
562 }
563
rs690_mc_rreg(struct radeon_device * rdev,uint32_t reg)564 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
565 {
566 uint32_t r;
567
568 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
569 r = RREG32(R_00007C_MC_DATA);
570 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
571 return r;
572 }
573
rs690_mc_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)574 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
575 {
576 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
577 S_000078_MC_IND_WR_EN(1));
578 WREG32(R_00007C_MC_DATA, v);
579 WREG32(R_000078_MC_INDEX, 0x7F);
580 }
581
rs690_mc_program(struct radeon_device * rdev)582 static void rs690_mc_program(struct radeon_device *rdev)
583 {
584 struct rv515_mc_save save;
585
586 /* Stops all mc clients */
587 rv515_mc_stop(rdev, &save);
588
589 /* Wait for mc idle */
590 if (rs690_mc_wait_for_idle(rdev))
591 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
592 /* Program MC, should be a 32bits limited address space */
593 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
594 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
595 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
596 WREG32(R_000134_HDP_FB_LOCATION,
597 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
598
599 rv515_mc_resume(rdev, &save);
600 }
601
rs690_startup(struct radeon_device * rdev)602 static int rs690_startup(struct radeon_device *rdev)
603 {
604 int r;
605
606 rs690_mc_program(rdev);
607 /* Resume clock */
608 rv515_clock_startup(rdev);
609 /* Initialize GPU configuration (# pipes, ...) */
610 rs690_gpu_init(rdev);
611 /* Initialize GART (initialize after TTM so we can allocate
612 * memory through TTM but finalize after TTM) */
613 r = rs400_gart_enable(rdev);
614 if (r)
615 return r;
616
617 /* allocate wb buffer */
618 r = radeon_wb_init(rdev);
619 if (r)
620 return r;
621
622 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
623 if (r) {
624 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
625 return r;
626 }
627
628 /* Enable IRQ */
629 rs600_irq_set(rdev);
630 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
631 /* 1M ring buffer */
632 r = r100_cp_init(rdev, 1024 * 1024);
633 if (r) {
634 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
635 return r;
636 }
637
638 r = radeon_ib_pool_init(rdev);
639 if (r) {
640 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
641 return r;
642 }
643
644 r = r600_audio_init(rdev);
645 if (r) {
646 dev_err(rdev->dev, "failed initializing audio\n");
647 return r;
648 }
649
650 return 0;
651 }
652
rs690_resume(struct radeon_device * rdev)653 int rs690_resume(struct radeon_device *rdev)
654 {
655 int r;
656
657 /* Make sur GART are not working */
658 rs400_gart_disable(rdev);
659 /* Resume clock before doing reset */
660 rv515_clock_startup(rdev);
661 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
662 if (radeon_asic_reset(rdev)) {
663 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
664 RREG32(R_000E40_RBBM_STATUS),
665 RREG32(R_0007C0_CP_STAT));
666 }
667 /* post */
668 atom_asic_init(rdev->mode_info.atom_context);
669 /* Resume clock after posting */
670 rv515_clock_startup(rdev);
671 /* Initialize surface registers */
672 radeon_surface_init(rdev);
673
674 rdev->accel_working = true;
675 r = rs690_startup(rdev);
676 if (r) {
677 rdev->accel_working = false;
678 }
679 return r;
680 }
681
rs690_suspend(struct radeon_device * rdev)682 int rs690_suspend(struct radeon_device *rdev)
683 {
684 r600_audio_fini(rdev);
685 r100_cp_disable(rdev);
686 radeon_wb_disable(rdev);
687 rs600_irq_disable(rdev);
688 rs400_gart_disable(rdev);
689 return 0;
690 }
691
rs690_fini(struct radeon_device * rdev)692 void rs690_fini(struct radeon_device *rdev)
693 {
694 r600_audio_fini(rdev);
695 r100_cp_fini(rdev);
696 radeon_wb_fini(rdev);
697 radeon_ib_pool_fini(rdev);
698 radeon_gem_fini(rdev);
699 rs400_gart_fini(rdev);
700 radeon_irq_kms_fini(rdev);
701 radeon_fence_driver_fini(rdev);
702 radeon_bo_fini(rdev);
703 radeon_atombios_fini(rdev);
704 free(rdev->bios, DRM_MEM_DRIVER);
705 rdev->bios = NULL;
706 }
707
rs690_init(struct radeon_device * rdev)708 int rs690_init(struct radeon_device *rdev)
709 {
710 int r;
711
712 /* Disable VGA */
713 rv515_vga_render_disable(rdev);
714 /* Initialize scratch registers */
715 radeon_scratch_init(rdev);
716 /* Initialize surface registers */
717 radeon_surface_init(rdev);
718 /* restore some register to sane defaults */
719 r100_restore_sanity(rdev);
720 /* TODO: disable VGA need to use VGA request */
721 /* BIOS*/
722 if (!radeon_get_bios(rdev)) {
723 if (ASIC_IS_AVIVO(rdev))
724 return -EINVAL;
725 }
726 if (rdev->is_atom_bios) {
727 r = radeon_atombios_init(rdev);
728 if (r)
729 return r;
730 } else {
731 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
732 return -EINVAL;
733 }
734 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
735 if (radeon_asic_reset(rdev)) {
736 dev_warn(rdev->dev,
737 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
738 RREG32(R_000E40_RBBM_STATUS),
739 RREG32(R_0007C0_CP_STAT));
740 }
741 /* check if cards are posted or not */
742 if (radeon_boot_test_post_card(rdev) == false)
743 return -EINVAL;
744
745 /* Initialize clocks */
746 radeon_get_clock_info(rdev->ddev);
747 /* initialize memory controller */
748 rs690_mc_init(rdev);
749 rv515_debugfs(rdev);
750 /* Fence driver */
751 r = radeon_fence_driver_init(rdev);
752 if (r)
753 return r;
754 r = radeon_irq_kms_init(rdev);
755 if (r)
756 return r;
757 /* Memory manager */
758 r = radeon_bo_init(rdev);
759 if (r)
760 return r;
761 r = rs400_gart_init(rdev);
762 if (r)
763 return r;
764 rs600_set_safe_registers(rdev);
765
766 rdev->accel_working = true;
767 r = rs690_startup(rdev);
768 if (r) {
769 /* Somethings want wront with the accel init stop accel */
770 dev_err(rdev->dev, "Disabling GPU acceleration\n");
771 r100_cp_fini(rdev);
772 radeon_wb_fini(rdev);
773 radeon_ib_pool_fini(rdev);
774 rs400_gart_fini(rdev);
775 radeon_irq_kms_fini(rdev);
776 rdev->accel_working = false;
777 }
778 return 0;
779 }
780