1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/lock.h>
34 #include <sys/mutex.h>
35 #include <sys/rman.h>
36
37 #include <machine/bus.h>
38
39 #include <dev/extres/clk/clk.h>
40
41 #include <gnu/dts/include/dt-bindings/clock/tegra124-car.h>
42 #include "tegra124_car.h"
43
44 /* #define TEGRA_PLL_DEBUG */
45 #ifdef TEGRA_PLL_DEBUG
46 #define dprintf(...) printf(__VA_ARGS__)
47 #else
48 #define dprintf(...)
49 #endif
50
51 /* All PLLs. */
52 enum pll_type {
53 PLL_M,
54 PLL_X,
55 PLL_C,
56 PLL_C2,
57 PLL_C3,
58 PLL_C4,
59 PLL_P,
60 PLL_A,
61 PLL_U,
62 PLL_D,
63 PLL_D2,
64 PLL_DP,
65 PLL_E,
66 PLL_REFE};
67
68 /* Common base register bits. */
69 #define PLL_BASE_BYPASS (1U << 31)
70 #define PLL_BASE_ENABLE (1 << 30)
71 #define PLL_BASE_REFDISABLE (1 << 29)
72 #define PLL_BASE_LOCK (1 << 27)
73 #define PLL_BASE_DIVM_SHIFT 0
74 #define PLL_BASE_DIVN_SHIFT 8
75
76 #define PLLRE_MISC_LOCK (1 << 24)
77
78 #define PLL_MISC_LOCK_ENABLE (1 << 18)
79 #define PLLC_MISC_LOCK_ENABLE (1 << 24)
80 #define PLLDU_MISC_LOCK_ENABLE (1 << 22)
81 #define PLLRE_MISC_LOCK_ENABLE (1 << 30)
82 #define PLLSS_MISC_LOCK_ENABLE (1 << 30)
83
84 #define PLLC_IDDQ_BIT 26
85 #define PLLX_IDDQ_BIT 3
86 #define PLLRE_IDDQ_BIT 16
87 #define PLLSS_IDDQ_BIT 19
88
89 #define PLL_LOCK_TIMEOUT 5000
90
91 /* Post divider <-> register value mapping. */
92 struct pdiv_table {
93 uint32_t divider; /* real divider */
94 uint32_t value; /* register value */
95 };
96
97 /* Bits definition of M, N and P fields. */
98 struct mnp_bits {
99 uint32_t m_width;
100 uint32_t n_width;
101 uint32_t p_width;
102 uint32_t p_shift;
103 };
104
105 struct clk_pll_def {
106 struct clknode_init_def clkdef;
107 enum pll_type type;
108 uint32_t base_reg;
109 uint32_t misc_reg;
110 uint32_t lock_mask;
111 uint32_t lock_enable;
112 uint32_t iddq_reg;
113 uint32_t iddq_mask;
114 uint32_t flags;
115 struct pdiv_table *pdiv_table;
116 struct mnp_bits mnp_bits;
117 };
118
119 #define PLL(_id, cname, pname) \
120 .clkdef.id = _id, \
121 .clkdef.name = cname, \
122 .clkdef.parent_names = (const char *[]){pname}, \
123 .clkdef.parent_cnt = 1, \
124 .clkdef.flags = CLK_NODE_STATIC_STRINGS
125
126 /* Tegra K1 PLLs
127 PLLM: Clock source for EMC 2x clock
128 PLLX: Clock source for the fast CPU cluster and the shadow CPU
129 PLLC: Clock source for general use
130 PLLC2: Clock source for engine scaling
131 PLLC3: Clock source for engine scaling
132 PLLC4: Clock source for ISP/VI units
133 PLLP: Clock source for most peripherals
134 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
135 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
136 PLLD: Clock sources for the DSI and display subsystem
137 PLLD2: Clock sources for the DSI and display subsystem
138 refPLLe:
139 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
140 PLLDP: Clock source for eDP/LVDS (spread spectrum)
141
142 DFLLCPU: DFLL clock source for the fast CPU cluster
143 GPCPLL: Clock source for the GPU
144 */
145
146 static struct pdiv_table pllm_map[] = {
147 {1, 0},
148 {2, 1},
149 {0, 0}
150 };
151
152 static struct pdiv_table pllxc_map[] = {
153 { 1, 0},
154 { 2, 1},
155 { 3, 2},
156 { 4, 3},
157 { 5, 4},
158 { 6, 5},
159 { 8, 6},
160 {10, 7},
161 {12, 8},
162 {16, 9},
163 {12, 10},
164 {16, 11},
165 {20, 12},
166 {24, 13},
167 {32, 14},
168 { 0, 0}
169 };
170
171 static struct pdiv_table pllc_map[] = {
172 { 1, 0},
173 { 2, 1},
174 { 3, 2},
175 { 4, 3},
176 { 6, 4},
177 { 8, 5},
178 {12, 6},
179 {16, 7},
180 { 0, 0}
181 };
182
183 static struct pdiv_table pll12g_ssd_esd_map[] = {
184 { 1, 0},
185 { 2, 1},
186 { 3, 2},
187 { 4, 3},
188 { 5, 4},
189 { 6, 5},
190 { 8, 6},
191 {10, 7},
192 {12, 8},
193 {16, 9},
194 {12, 10},
195 {16, 11},
196 {20, 12},
197 {24, 13},
198 {32, 14},
199 { 0, 0}
200 };
201
202 static struct pdiv_table pllu_map[] = {
203 {1, 1},
204 {2, 0},
205 {0, 0}
206 };
207
208 static struct pdiv_table pllrefe_map[] = {
209 {1, 0},
210 {2, 1},
211 {3, 2},
212 {4, 3},
213 {5, 4},
214 {6, 5},
215 {0, 0},
216 };
217
218 static struct clk_pll_def pll_clks[] = {
219 /* PLLM: 880 MHz Clock source for EMC 2x clock */
220 {
221 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
222 .type = PLL_M,
223 .base_reg = PLLM_BASE,
224 .misc_reg = PLLM_MISC,
225 .lock_mask = PLL_BASE_LOCK,
226 .lock_enable = PLL_MISC_LOCK_ENABLE,
227 .pdiv_table = pllm_map,
228 .mnp_bits = {8, 8, 1, 20},
229 },
230 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */
231 {
232 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
233 .type = PLL_X,
234 .base_reg = PLLX_BASE,
235 .misc_reg = PLLX_MISC,
236 .lock_mask = PLL_BASE_LOCK,
237 .lock_enable = PLL_MISC_LOCK_ENABLE,
238 .iddq_reg = PLLX_MISC3,
239 .iddq_mask = 1 << PLLX_IDDQ_BIT,
240 .pdiv_table = pllxc_map,
241 .mnp_bits = {8, 8, 4, 20},
242 },
243 /* PLLC: 600 MHz Clock source for general use */
244 {
245 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
246 .type = PLL_C,
247 .base_reg = PLLC_BASE,
248 .misc_reg = PLLC_MISC,
249 .lock_mask = PLL_BASE_LOCK,
250 .lock_enable = PLLC_MISC_LOCK_ENABLE,
251 .iddq_reg = PLLC_MISC,
252 .iddq_mask = 1 << PLLC_IDDQ_BIT,
253 .pdiv_table = pllc_map,
254 .mnp_bits = {8, 8, 4, 20},
255 },
256 /* PLLC2: 600 MHz Clock source for engine scaling */
257 {
258 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
259 .type = PLL_C2,
260 .base_reg = PLLC2_BASE,
261 .misc_reg = PLLC2_MISC,
262 .lock_mask = PLL_BASE_LOCK,
263 .lock_enable = PLL_MISC_LOCK_ENABLE,
264 .pdiv_table = pllc_map,
265 .mnp_bits = {2, 8, 3, 20},
266 },
267 /* PLLC3: 600 MHz Clock source for engine scaling */
268 {
269 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
270 .type = PLL_C3,
271 .base_reg = PLLC3_BASE,
272 .misc_reg = PLLC3_MISC,
273 .lock_mask = PLL_BASE_LOCK,
274 .lock_enable = PLL_MISC_LOCK_ENABLE,
275 .pdiv_table = pllc_map,
276 .mnp_bits = {2, 8, 3, 20},
277 },
278 /* PLLC4: 600 MHz Clock source for ISP/VI units */
279 {
280 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),
281 .type = PLL_C4,
282 .base_reg = PLLC4_BASE,
283 .misc_reg = PLLC4_MISC,
284 .lock_mask = PLL_BASE_LOCK,
285 .lock_enable = PLLSS_MISC_LOCK_ENABLE,
286 .iddq_reg = PLLC4_BASE,
287 .iddq_mask = 1 << PLLSS_IDDQ_BIT,
288 .pdiv_table = pll12g_ssd_esd_map,
289 .mnp_bits = {8, 8, 4, 20},
290 },
291 /* PLLP: 408 MHz Clock source for most peripherals */
292 {
293 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
294 .type = PLL_P,
295 .base_reg = PLLP_BASE,
296 .misc_reg = PLLP_MISC,
297 .lock_mask = PLL_BASE_LOCK,
298 .lock_enable = PLL_MISC_LOCK_ENABLE,
299 .mnp_bits = {5, 10, 3, 20},
300 },
301 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */
302 {
303 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
304 .type = PLL_A,
305 .base_reg = PLLA_BASE,
306 .misc_reg = PLLA_MISC,
307 .lock_mask = PLL_BASE_LOCK,
308 .lock_enable = PLL_MISC_LOCK_ENABLE,
309 .mnp_bits = {5, 10, 3, 20},
310 },
311 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
312 {
313 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),
314 .type = PLL_U,
315 .base_reg = PLLU_BASE,
316 .misc_reg = PLLU_MISC,
317 .lock_mask = PLL_BASE_LOCK,
318 .lock_enable = PLLDU_MISC_LOCK_ENABLE,
319 .pdiv_table = pllu_map,
320 .mnp_bits = {5, 10, 1, 20},
321 },
322 /* PLLD: 600 MHz Clock sources for the DSI and display subsystem */
323 {
324 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"),
325 .type = PLL_D,
326 .base_reg = PLLD_BASE,
327 .misc_reg = PLLD_MISC,
328 .lock_mask = PLL_BASE_LOCK,
329 .lock_enable = PLL_MISC_LOCK_ENABLE,
330 .mnp_bits = {5, 11, 3, 20},
331 },
332 /* PLLD2: 600 MHz Clock sources for the DSI and display subsystem */
333 {
334 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
335 .type = PLL_D2,
336 .base_reg = PLLD2_BASE,
337 .misc_reg = PLLD2_MISC,
338 .lock_mask = PLL_BASE_LOCK,
339 .lock_enable = PLLSS_MISC_LOCK_ENABLE,
340 .iddq_reg = PLLD2_BASE,
341 .iddq_mask = 1 << PLLSS_IDDQ_BIT,
342 .pdiv_table = pll12g_ssd_esd_map,
343 .mnp_bits = {8, 8, 4, 20},
344 },
345 /* refPLLe: */
346 {
347 PLL(0, "pllREFE_out", "osc_div_clk"),
348 .type = PLL_REFE,
349 .base_reg = PLLRE_BASE,
350 .misc_reg = PLLRE_MISC,
351 .lock_mask = PLLRE_MISC_LOCK,
352 .lock_enable = PLLRE_MISC_LOCK_ENABLE,
353 .iddq_reg = PLLRE_MISC,
354 .iddq_mask = 1 << PLLRE_IDDQ_BIT,
355 .pdiv_table = pllrefe_map,
356 .mnp_bits = {8, 8, 4, 16},
357 },
358 /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */
359 {
360 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"),
361 .type = PLL_E,
362 .base_reg = PLLE_BASE,
363 .misc_reg = PLLE_MISC,
364 .lock_mask = PLLE_MISC_LOCK,
365 .lock_enable = PLLE_MISC_LOCK_ENABLE,
366 .mnp_bits = {8, 8, 4, 24},
367 },
368 /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */
369 {
370 PLL(0, "pllDP_out0", "pllDP_src"),
371 .type = PLL_DP,
372 .base_reg = PLLDP_BASE,
373 .misc_reg = PLLDP_MISC,
374 .lock_mask = PLL_BASE_LOCK,
375 .lock_enable = PLLSS_MISC_LOCK_ENABLE,
376 .iddq_reg = PLLDP_BASE,
377 .iddq_mask = 1 << PLLSS_IDDQ_BIT,
378 .pdiv_table = pll12g_ssd_esd_map,
379 .mnp_bits = {8, 8, 4, 20},
380 },
381 };
382
383 static int tegra124_pll_init(struct clknode *clk, device_t dev);
384 static int tegra124_pll_set_gate(struct clknode *clk, bool enable);
385 static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq);
386 static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin,
387 uint64_t *fout, int flags, int *stop);
388 struct pll_sc {
389 device_t clkdev;
390 enum pll_type type;
391 uint32_t base_reg;
392 uint32_t misc_reg;
393 uint32_t lock_mask;
394 uint32_t lock_enable;
395 uint32_t iddq_reg;
396 uint32_t iddq_mask;
397 uint32_t flags;
398 struct pdiv_table *pdiv_table;
399 struct mnp_bits mnp_bits;
400 };
401
402 static clknode_method_t tegra124_pll_methods[] = {
403 /* Device interface */
404 CLKNODEMETHOD(clknode_init, tegra124_pll_init),
405 CLKNODEMETHOD(clknode_set_gate, tegra124_pll_set_gate),
406 CLKNODEMETHOD(clknode_recalc_freq, tegra124_pll_recalc),
407 CLKNODEMETHOD(clknode_set_freq, tegra124_pll_set_freq),
408 CLKNODEMETHOD_END
409 };
410 DEFINE_CLASS_1(tegra124_pll, tegra124_pll_class, tegra124_pll_methods,
411 sizeof(struct pll_sc), clknode_class);
412
413 static int
pll_enable(struct pll_sc * sc)414 pll_enable(struct pll_sc *sc)
415 {
416 uint32_t reg;
417
418
419 RD4(sc, sc->base_reg, ®);
420 if (sc->type != PLL_E)
421 reg &= ~PLL_BASE_BYPASS;
422 reg |= PLL_BASE_ENABLE;
423 WR4(sc, sc->base_reg, reg);
424 return (0);
425 }
426
427 static int
pll_disable(struct pll_sc * sc)428 pll_disable(struct pll_sc *sc)
429 {
430 uint32_t reg;
431
432 RD4(sc, sc->base_reg, ®);
433 if (sc->type != PLL_E)
434 reg |= PLL_BASE_BYPASS;
435 reg &= ~PLL_BASE_ENABLE;
436 WR4(sc, sc->base_reg, reg);
437 return (0);
438 }
439
440 static uint32_t
pdiv_to_reg(struct pll_sc * sc,uint32_t p_div)441 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div)
442 {
443 struct pdiv_table *tbl;
444
445 tbl = sc->pdiv_table;
446 if (tbl == NULL)
447 return (ffs(p_div) - 1);
448
449 while (tbl->divider != 0) {
450 if (p_div <= tbl->divider)
451 return (tbl->value);
452 tbl++;
453 }
454 return (0xFFFFFFFF);
455 }
456
457 static uint32_t
reg_to_pdiv(struct pll_sc * sc,uint32_t reg)458 reg_to_pdiv(struct pll_sc *sc, uint32_t reg)
459 {
460 struct pdiv_table *tbl;
461
462 tbl = sc->pdiv_table;
463 if (tbl == NULL)
464 return (1 << reg);
465
466 while (tbl->divider) {
467 if (reg == tbl->value)
468 return (tbl->divider);
469 tbl++;
470 }
471 return (0);
472 }
473
474 static uint32_t
get_masked(uint32_t val,uint32_t shift,uint32_t width)475 get_masked(uint32_t val, uint32_t shift, uint32_t width)
476 {
477
478 return ((val >> shift) & ((1 << width) - 1));
479 }
480
481 static uint32_t
set_masked(uint32_t val,uint32_t v,uint32_t shift,uint32_t width)482 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width)
483 {
484
485 val &= ~(((1 << width) - 1) << shift);
486 val |= (v & ((1 << width) - 1)) << shift;
487 return (val);
488 }
489
490 static void
get_divisors(struct pll_sc * sc,uint32_t * m,uint32_t * n,uint32_t * p)491 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p)
492 {
493 uint32_t val;
494 struct mnp_bits *mnp_bits;
495
496 mnp_bits = &sc->mnp_bits;
497 RD4(sc, sc->base_reg, &val);
498 *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
499 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
500 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width);
501 }
502
503 static uint32_t
set_divisors(struct pll_sc * sc,uint32_t val,uint32_t m,uint32_t n,uint32_t p)504 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n,
505 uint32_t p)
506 {
507 struct mnp_bits *mnp_bits;
508
509 mnp_bits = &sc->mnp_bits;
510 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
511 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
512 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);
513 return (val);
514 }
515
516 static bool
is_locked(struct pll_sc * sc)517 is_locked(struct pll_sc *sc)
518 {
519 uint32_t reg;
520
521 switch (sc->type) {
522 case PLL_REFE:
523 RD4(sc, sc->misc_reg, ®);
524 reg &= PLLRE_MISC_LOCK;
525 break;
526
527 case PLL_E:
528 RD4(sc, sc->misc_reg, ®);
529 reg &= PLLE_MISC_LOCK;
530 break;
531
532 default:
533 RD4(sc, sc->base_reg, ®);
534 reg &= PLL_BASE_LOCK;
535 break;
536 }
537 return (reg != 0);
538 }
539
540 static int
wait_for_lock(struct pll_sc * sc)541 wait_for_lock(struct pll_sc *sc)
542 {
543 int i;
544
545 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) {
546 if (is_locked(sc))
547 break;
548 DELAY(10);
549 }
550 if (i <= 0) {
551 printf("PLL lock timeout\n");
552 return (ETIMEDOUT);
553 }
554 return (0);
555 }
556
557 static int
plle_enable(struct pll_sc * sc)558 plle_enable(struct pll_sc *sc)
559 {
560 uint32_t reg;
561 int rv;
562 struct mnp_bits *mnp_bits;
563 uint32_t pll_m = 1;
564 uint32_t pll_n = 200;
565 uint32_t pll_p = 13;
566 uint32_t pll_cml = 13;
567
568 mnp_bits = &sc->mnp_bits;
569
570
571 /* Disable lock override. */
572 RD4(sc, sc->base_reg, ®);
573 reg &= ~PLLE_BASE_LOCK_OVERRIDE;
574 WR4(sc, sc->base_reg, reg);
575
576 RD4(sc, PLLE_AUX, ®);
577 reg |= PLLE_AUX_ENABLE_SWCTL;
578 reg &= ~PLLE_AUX_SEQ_ENABLE;
579 WR4(sc, PLLE_AUX, reg);
580 DELAY(10);
581
582 RD4(sc, sc->misc_reg, ®);
583 reg |= PLLE_MISC_LOCK_ENABLE;
584 reg |= PLLE_MISC_IDDQ_SWCTL;
585 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
586 reg |= PLLE_MISC_PTS;
587 reg |= PLLE_MISC_VREG_BG_CTRL_MASK;
588 reg |= PLLE_MISC_VREG_CTRL_MASK;
589 WR4(sc, sc->misc_reg, reg);
590 DELAY(10);
591
592 RD4(sc, PLLE_SS_CNTL, ®);
593 reg |= PLLE_SS_CNTL_DISABLE;
594 WR4(sc, PLLE_SS_CNTL, reg);
595
596 RD4(sc, sc->base_reg, ®);
597 reg = set_divisors(sc, reg, pll_m, pll_n, pll_p);
598 reg &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
599 reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT;
600 WR4(sc, sc->base_reg, reg);
601 DELAY(10);
602
603 pll_enable(sc);
604 rv = wait_for_lock(sc);
605 if (rv != 0)
606 return (rv);
607
608 RD4(sc, PLLE_SS_CNTL, ®);
609 reg &= ~PLLE_SS_CNTL_SSCCENTER;
610 reg &= ~PLLE_SS_CNTL_SSCINVERT;
611 reg &= ~PLLE_SS_CNTL_COEFFICIENTS_MASK;
612 reg |= PLLE_SS_CNTL_COEFFICIENTS_VAL;
613 WR4(sc, PLLE_SS_CNTL, reg);
614 reg &= ~PLLE_SS_CNTL_SSCBYP;
615 reg &= ~PLLE_SS_CNTL_BYPASS_SS;
616 WR4(sc, PLLE_SS_CNTL, reg);
617 DELAY(10);
618
619 reg &= ~PLLE_SS_CNTL_INTERP_RESET;
620 WR4(sc, PLLE_SS_CNTL, reg);
621 DELAY(10);
622
623 /* HW control of brick pll. */
624 RD4(sc, sc->misc_reg, ®);
625 reg &= ~PLLE_MISC_IDDQ_SWCTL;
626 WR4(sc, sc->misc_reg, reg);
627
628 RD4(sc, PLLE_AUX, ®);
629 reg |= PLLE_AUX_USE_LOCKDET;
630 reg |= PLLE_AUX_SEQ_START_STATE;
631 reg &= ~PLLE_AUX_ENABLE_SWCTL;
632 reg &= ~PLLE_AUX_SS_SWCTL;
633 WR4(sc, PLLE_AUX, reg);
634 reg |= PLLE_AUX_SEQ_START_STATE;
635 DELAY(10);
636 reg |= PLLE_AUX_SEQ_ENABLE;
637 WR4(sc, PLLE_AUX, reg);
638
639 RD4(sc, XUSBIO_PLL_CFG0, ®);
640 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
641 reg |= XUSBIO_PLL_CFG0_SEQ_START_STATE;
642 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
643 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
644 WR4(sc, XUSBIO_PLL_CFG0, reg);
645 DELAY(10);
646
647 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
648 WR4(sc, XUSBIO_PLL_CFG0, reg);
649
650
651 /* Enable HW control and unreset SATA PLL. */
652 RD4(sc, SATA_PLL_CFG0, ®);
653 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
654 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE;
655 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
656 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL;
657 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE;
658 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE;
659 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE;
660 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE;
661 reg |= SATA_PLL_CFG0_SEQ_START_STATE;
662 WR4(sc, SATA_PLL_CFG0, reg);
663 DELAY(10);
664 reg |= SATA_PLL_CFG0_SEQ_ENABLE;
665 WR4(sc, SATA_PLL_CFG0, reg);
666
667 /* Enable HW control of PCIe PLL. */
668 RD4(sc, PCIE_PLL_CFG0, ®);
669 reg |= PCIE_PLL_CFG0_SEQ_ENABLE;
670 WR4(sc, PCIE_PLL_CFG0, reg);
671
672 return (0);
673 }
674
675 static int
tegra124_pll_set_gate(struct clknode * clknode,bool enable)676 tegra124_pll_set_gate(struct clknode *clknode, bool enable)
677 {
678 int rv;
679 struct pll_sc *sc;
680
681 sc = clknode_get_softc(clknode);
682 if (enable == 0) {
683 rv = pll_disable(sc);
684 return(rv);
685 }
686
687 if (sc->type == PLL_E)
688 rv = plle_enable(sc);
689 else
690 rv = pll_enable(sc);
691 return (rv);
692 }
693
694 static int
pll_set_std(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags,uint32_t m,uint32_t n,uint32_t p)695 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
696 uint32_t m, uint32_t n, uint32_t p)
697 {
698 uint32_t reg;
699 struct mnp_bits *mnp_bits;
700 int rv;
701
702 mnp_bits = &sc->mnp_bits;
703 if (m >= (1 << mnp_bits->m_width))
704 return (ERANGE);
705 if (n >= (1 << mnp_bits->n_width))
706 return (ERANGE);
707 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
708 return (ERANGE);
709
710 if (flags & CLK_SET_DRYRUN) {
711 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
712 (*fout != (((fin / m) * n) /p)))
713 return (ERANGE);
714
715 *fout = ((fin / m) * n) /p;
716
717 return (0);
718 }
719
720 pll_disable(sc);
721
722 /* take pll out of IDDQ */
723 if (sc->iddq_reg != 0)
724 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0);
725
726 RD4(sc, sc->base_reg, ®);
727 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
728 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
729 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
730 mnp_bits->p_width);
731 WR4(sc, sc->base_reg, reg);
732
733 /* Enable PLL. */
734 RD4(sc, sc->base_reg, ®);
735 reg |= PLL_BASE_ENABLE;
736 WR4(sc, sc->base_reg, reg);
737
738 /* Enable lock detection. */
739 RD4(sc, sc->misc_reg, ®);
740 reg |= sc->lock_enable;
741 WR4(sc, sc->misc_reg, reg);
742
743 rv = wait_for_lock(sc);
744 if (rv != 0) {
745 /* Disable PLL */
746 RD4(sc, sc->base_reg, ®);
747 reg &= ~PLL_BASE_ENABLE;
748 WR4(sc, sc->base_reg, reg);
749 return (rv);
750 }
751 RD4(sc, sc->misc_reg, ®);
752
753 pll_enable(sc);
754 *fout = ((fin / m) * n) / p;
755 return 0;
756 }
757
758 static int
plla_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)759 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
760 {
761 uint32_t m, n, p;
762
763 p = 1;
764 m = 5;
765 n = (*fout * p * m + fin / 2)/ fin;
766 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
767 return (pll_set_std(sc, fin, fout, flags, m, n, p));
768 }
769
770 static int
pllc_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)771 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
772 {
773 uint32_t m, n, p;
774
775 p = 2;
776 m = 1;
777 n = (*fout * p * m + fin / 2)/ fin;
778 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
779 return (pll_set_std( sc, fin, fout, flags, m, n, p));
780 }
781
782 /*
783 * PLLD2 is used as source for pixel clock for HDMI.
784 * We must be able to set it frequency very flexibly and
785 * precisely (within 5% tolerance limit allowed by HDMI specs).
786 *
787 * For this reason, it is necessary to search the full state space.
788 * Fortunately, thanks to early cycle terminations, performance
789 * is within acceptable limits.
790 */
791 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */
792 #define PLLD2_PFD_MAX 38000000 /* 38 MHz */
793 #define PLLD2_VCO_MIN 600000000 /* 600 MHz */
794 #define PLLD2_VCO_MAX 1200000000 /* 1.2 GHz */
795
796 static int
plld2_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)797 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
798 {
799 uint32_t m, n, p;
800 uint32_t best_m, best_n, best_p;
801 uint64_t vco, pfd;
802 int64_t err, best_err;
803 struct mnp_bits *mnp_bits;
804 struct pdiv_table *tbl;
805 int p_idx, rv;
806
807 mnp_bits = &sc->mnp_bits;
808 tbl = sc->pdiv_table;
809 best_err = INT64_MAX;
810
811 for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) {
812 p = tbl[p_idx].divider;
813
814 /* Check constraints */
815 vco = *fout * p;
816 if (vco < PLLD2_VCO_MIN)
817 continue;
818 if (vco > PLLD2_VCO_MAX)
819 break;
820
821 for (m = 1; m < (1 << mnp_bits->m_width); m++) {
822 n = (*fout * p * m + fin / 2) / fin;
823
824 /* Check constraints */
825 if (n == 0)
826 continue;
827 if (n >= (1 << mnp_bits->n_width))
828 break;
829 vco = (fin * n) / m;
830 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN)
831 continue;
832 pfd = fin / m;
833 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN)
834 continue;
835
836 /* Constraints passed, save best result */
837 err = *fout - vco / p;
838 if (err < 0)
839 err = -err;
840 if (err < best_err) {
841 best_err = err;
842 best_p = p;
843 best_m = m;
844 best_n = n;
845 }
846 if (err == 0)
847 goto done;
848 }
849 }
850 done:
851 /*
852 * HDMI specification allows 5% pixel clock tolerance,
853 * we will by a slightly stricter
854 */
855 if (best_err > ((*fout * 100) / 4))
856 return (ERANGE);
857
858 if (flags & CLK_SET_DRYRUN)
859 return (0);
860 rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p);
861 /* XXXX Panic for rv == ERANGE ? */
862 return (rv);
863 }
864
865 static int
pllrefe_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)866 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
867 {
868 uint32_t m, n, p;
869
870 m = 1;
871 p = 1;
872 n = *fout * p * m / fin;
873 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
874 return (pll_set_std(sc, fin, fout, flags, m, n, p));
875 }
876
877 static int
pllx_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)878 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
879 {
880 uint32_t reg;
881 uint32_t m, n, p;
882 struct mnp_bits *mnp_bits;
883 int rv;
884
885 mnp_bits = &sc->mnp_bits;
886
887 p = 1;
888 m = 1;
889 n = (*fout * p * m + fin / 2)/ fin;
890 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
891
892 if (m >= (1 << mnp_bits->m_width))
893 return (ERANGE);
894 if (n >= (1 << mnp_bits->n_width))
895 return (ERANGE);
896 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
897 return (ERANGE);
898
899 if (flags & CLK_SET_DRYRUN) {
900 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
901 (*fout != (((fin / m) * n) /p)))
902 return (ERANGE);
903 *fout = ((fin / m) * n) /p;
904 return (0);
905 }
906
907 /* PLLX doesn't have bypass, disable it first. */
908 RD4(sc, sc->base_reg, ®);
909 reg &= ~PLL_BASE_ENABLE;
910 WR4(sc, sc->base_reg, reg);
911
912 /* Set PLL. */
913 RD4(sc, sc->base_reg, ®);
914 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
915 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
916 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
917 mnp_bits->p_width);
918 WR4(sc, sc->base_reg, reg);
919 RD4(sc, sc->base_reg, ®);
920 DELAY(100);
921
922 /* Enable lock detection. */
923 RD4(sc, sc->misc_reg, ®);
924 reg |= sc->lock_enable;
925 WR4(sc, sc->misc_reg, reg);
926
927 /* Enable PLL. */
928 RD4(sc, sc->base_reg, ®);
929 reg |= PLL_BASE_ENABLE;
930 WR4(sc, sc->base_reg, reg);
931
932 rv = wait_for_lock(sc);
933 if (rv != 0) {
934 /* Disable PLL */
935 RD4(sc, sc->base_reg, ®);
936 reg &= ~PLL_BASE_ENABLE;
937 WR4(sc, sc->base_reg, reg);
938 return (rv);
939 }
940 RD4(sc, sc->misc_reg, ®);
941
942 *fout = ((fin / m) * n) / p;
943 return (0);
944 }
945
946 static int
tegra124_pll_set_freq(struct clknode * clknode,uint64_t fin,uint64_t * fout,int flags,int * stop)947 tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout,
948 int flags, int *stop)
949 {
950 *stop = 1;
951 int rv;
952 struct pll_sc *sc;
953
954 sc = clknode_get_softc(clknode);
955 dprintf("%s: %s requested freq: %llu, input freq: %llu\n", __func__,
956 clknode_get_name(clknode), *fout, fin);
957 switch (sc->type) {
958 case PLL_A:
959 rv = plla_set_freq(sc, fin, fout, flags);
960 break;
961 case PLL_C:
962 rv = pllc_set_freq(sc, fin, fout, flags);
963 break;
964 case PLL_D2:
965 rv = plld2_set_freq(sc, fin, fout, flags);
966 break;
967
968 case PLL_REFE:
969 rv = pllrefe_set_freq(sc, fin, fout, flags);
970 break;
971
972 case PLL_X:
973 rv = pllx_set_freq(sc, fin, fout, flags);
974 break;
975
976 case PLL_U:
977 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */
978 rv = 0;
979 else
980 rv = ERANGE;
981 break;
982 default:
983 rv = ENXIO;
984 break;
985 }
986
987 return (rv);
988 }
989
990
991 static int
tegra124_pll_init(struct clknode * clk,device_t dev)992 tegra124_pll_init(struct clknode *clk, device_t dev)
993 {
994 struct pll_sc *sc;
995 uint32_t reg;
996
997 sc = clknode_get_softc(clk);
998
999 /* If PLL is enabled, enable lock detect too. */
1000 RD4(sc, sc->base_reg, ®);
1001 if (reg & PLL_BASE_ENABLE) {
1002 RD4(sc, sc->misc_reg, ®);
1003 reg |= sc->lock_enable;
1004 WR4(sc, sc->misc_reg, reg);
1005 }
1006 if (sc->type == PLL_REFE) {
1007 RD4(sc, sc->misc_reg, ®);
1008 reg &= ~(1 << 29); /* Diasble lock override */
1009 WR4(sc, sc->misc_reg, reg);
1010 }
1011
1012 clknode_init_parent_idx(clk, 0);
1013 return(0);
1014 }
1015
1016 static int
tegra124_pll_recalc(struct clknode * clk,uint64_t * freq)1017 tegra124_pll_recalc(struct clknode *clk, uint64_t *freq)
1018 {
1019 struct pll_sc *sc;
1020 uint32_t m, n, p, pr;
1021 uint32_t reg, misc_reg;
1022 int locked;
1023
1024 sc = clknode_get_softc(clk);
1025
1026 RD4(sc, sc->base_reg, ®);
1027 RD4(sc, sc->misc_reg, &misc_reg);
1028
1029 get_divisors(sc, &m, &n, &pr);
1030 if (sc->type != PLL_E)
1031 p = reg_to_pdiv(sc, pr);
1032 else
1033 p = 2 * (pr - 1);
1034 locked = is_locked(sc);
1035
1036 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): "
1037 "e: %d, r: %d, o: %d - %s\n", __func__,
1038 clknode_get_name(clk), reg, misc_reg, m, n, p, pr,
1039 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1,
1040 locked ? "locked" : "unlocked");
1041
1042 if ((m == 0) || (n == 0) || (p == 0)) {
1043 *freq = 0;
1044 return (EINVAL);
1045 }
1046 *freq = ((*freq / m) * n) / p;
1047 return (0);
1048 }
1049
1050 static int
pll_register(struct clkdom * clkdom,struct clk_pll_def * clkdef)1051 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef)
1052 {
1053 struct clknode *clk;
1054 struct pll_sc *sc;
1055
1056 clk = clknode_create(clkdom, &tegra124_pll_class, &clkdef->clkdef);
1057 if (clk == NULL)
1058 return (ENXIO);
1059
1060 sc = clknode_get_softc(clk);
1061 sc->clkdev = clknode_get_device(clk);
1062 sc->type = clkdef->type;
1063 sc->base_reg = clkdef->base_reg;
1064 sc->misc_reg = clkdef->misc_reg;
1065 sc->lock_mask = clkdef->lock_mask;
1066 sc->lock_enable = clkdef->lock_enable;
1067 sc->iddq_reg = clkdef->iddq_reg;
1068 sc->iddq_mask = clkdef->iddq_mask;
1069 sc->flags = clkdef->flags;
1070 sc->pdiv_table = clkdef->pdiv_table;
1071 sc->mnp_bits = clkdef->mnp_bits;
1072 clknode_register(clkdom, clk);
1073 return (0);
1074 }
1075
config_utmi_pll(struct tegra124_car_softc * sc)1076 static void config_utmi_pll(struct tegra124_car_softc *sc)
1077 {
1078 uint32_t reg;
1079 /*
1080 * XXX Simplified UTMIP settings for 12MHz base clock.
1081 */
1082 #define ENABLE_DELAY_COUNT 0x02
1083 #define STABLE_COUNT 0x2F
1084 #define ACTIVE_DELAY_COUNT 0x04
1085 #define XTAL_FREQ_COUNT 0x76
1086
1087 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®);
1088 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1089 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT);
1090 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1091 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT);
1092 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1093 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1094 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1095 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);
1096
1097 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1098 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1099 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT);
1100 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1101 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT);
1102 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1103 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1104 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1105 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1106 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1107
1108 /* Prepare UTMIP requencer. */
1109 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1110 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1111 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1112 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1113 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1114
1115 /* Powerup UTMIP. */
1116 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1117 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1118 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1119 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1120 DELAY(10);
1121
1122 /* SW override for UTMIPLL */
1123 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1124 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1125 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1126 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1127 DELAY(10);
1128
1129 /* HW control of UTMIPLL. */
1130 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1131 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1132 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1133 }
1134
1135 void
tegra124_init_plls(struct tegra124_car_softc * sc)1136 tegra124_init_plls(struct tegra124_car_softc *sc)
1137 {
1138 int i, rv;
1139
1140 for (i = 0; i < nitems(pll_clks); i++) {
1141 rv = pll_register(sc->clkdom, pll_clks + i);
1142 if (rv != 0)
1143 panic("pll_register failed");
1144 }
1145 config_utmi_pll(sc);
1146
1147 }
1148