1 /*-
2 * Copyright (c) 2013 Alexander Fedorov
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
39 #include <sys/rman.h>
40 #include <sys/sysctl.h>
41
42 #include <machine/bus.h>
43
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46
47 #include <dev/mmc/bridge.h>
48 #include <dev/mmc/mmcbrvar.h>
49
50 #include <arm/allwinner/a10_mmc.h>
51 #include <dev/extres/clk/clk.h>
52 #include <dev/extres/hwreset/hwreset.h>
53
54 #define A10_MMC_MEMRES 0
55 #define A10_MMC_IRQRES 1
56 #define A10_MMC_RESSZ 2
57 #define A10_MMC_DMA_SEGS ((MAXPHYS / PAGE_SIZE) + 1)
58 #define A10_MMC_DMA_MAX_SIZE 0x2000
59 #define A10_MMC_DMA_FTRGLEVEL 0x20070008
60 #define A10_MMC_RESET_RETRY 1000
61
62 #define CARD_ID_FREQUENCY 400000
63
64 static struct ofw_compat_data compat_data[] = {
65 {"allwinner,sun4i-a10-mmc", 1},
66 {"allwinner,sun5i-a13-mmc", 1},
67 {NULL, 0}
68 };
69
70 struct a10_mmc_softc {
71 device_t a10_dev;
72 clk_t a10_clk_ahb;
73 clk_t a10_clk_mmc;
74 hwreset_t a10_rst_ahb;
75 int a10_bus_busy;
76 int a10_resid;
77 int a10_timeout;
78 struct callout a10_timeoutc;
79 struct mmc_host a10_host;
80 struct mmc_request * a10_req;
81 struct mtx a10_mtx;
82 struct resource * a10_res[A10_MMC_RESSZ];
83 uint32_t a10_intr;
84 uint32_t a10_intr_wait;
85 void * a10_intrhand;
86
87 /* Fields required for DMA access. */
88 bus_addr_t a10_dma_desc_phys;
89 bus_dmamap_t a10_dma_map;
90 bus_dma_tag_t a10_dma_tag;
91 void * a10_dma_desc;
92 bus_dmamap_t a10_dma_buf_map;
93 bus_dma_tag_t a10_dma_buf_tag;
94 int a10_dma_map_err;
95 };
96
97 static struct resource_spec a10_mmc_res_spec[] = {
98 { SYS_RES_MEMORY, 0, RF_ACTIVE },
99 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
100 { -1, 0, 0 }
101 };
102
103 static int a10_mmc_probe(device_t);
104 static int a10_mmc_attach(device_t);
105 static int a10_mmc_detach(device_t);
106 static int a10_mmc_setup_dma(struct a10_mmc_softc *);
107 static int a10_mmc_reset(struct a10_mmc_softc *);
108 static void a10_mmc_intr(void *);
109 static int a10_mmc_update_clock(struct a10_mmc_softc *, uint32_t);
110
111 static int a10_mmc_update_ios(device_t, device_t);
112 static int a10_mmc_request(device_t, device_t, struct mmc_request *);
113 static int a10_mmc_get_ro(device_t, device_t);
114 static int a10_mmc_acquire_host(device_t, device_t);
115 static int a10_mmc_release_host(device_t, device_t);
116
117 #define A10_MMC_LOCK(_sc) mtx_lock(&(_sc)->a10_mtx)
118 #define A10_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->a10_mtx)
119 #define A10_MMC_READ_4(_sc, _reg) \
120 bus_read_4((_sc)->a10_res[A10_MMC_MEMRES], _reg)
121 #define A10_MMC_WRITE_4(_sc, _reg, _value) \
122 bus_write_4((_sc)->a10_res[A10_MMC_MEMRES], _reg, _value)
123
124 static int
a10_mmc_probe(device_t dev)125 a10_mmc_probe(device_t dev)
126 {
127
128 if (!ofw_bus_status_okay(dev))
129 return (ENXIO);
130 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
131 return (ENXIO);
132
133 device_set_desc(dev, "Allwinner Integrated MMC/SD controller");
134
135 return (BUS_PROBE_DEFAULT);
136 }
137
138 static int
a10_mmc_attach(device_t dev)139 a10_mmc_attach(device_t dev)
140 {
141 device_t child;
142 struct a10_mmc_softc *sc;
143 struct sysctl_ctx_list *ctx;
144 struct sysctl_oid_list *tree;
145 uint32_t bus_width;
146 phandle_t node;
147 int error;
148
149 node = ofw_bus_get_node(dev);
150 sc = device_get_softc(dev);
151 sc->a10_dev = dev;
152 sc->a10_req = NULL;
153 if (bus_alloc_resources(dev, a10_mmc_res_spec, sc->a10_res) != 0) {
154 device_printf(dev, "cannot allocate device resources\n");
155 return (ENXIO);
156 }
157 if (bus_setup_intr(dev, sc->a10_res[A10_MMC_IRQRES],
158 INTR_TYPE_MISC | INTR_MPSAFE, NULL, a10_mmc_intr, sc,
159 &sc->a10_intrhand)) {
160 bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res);
161 device_printf(dev, "cannot setup interrupt handler\n");
162 return (ENXIO);
163 }
164 mtx_init(&sc->a10_mtx, device_get_nameunit(sc->a10_dev), "a10_mmc",
165 MTX_DEF);
166 callout_init_mtx(&sc->a10_timeoutc, &sc->a10_mtx, 0);
167
168 /* De-assert reset */
169 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->a10_rst_ahb) == 0) {
170 error = hwreset_deassert(sc->a10_rst_ahb);
171 if (error != 0) {
172 device_printf(dev, "cannot de-assert reset\n");
173 goto fail;
174 }
175 }
176
177 /* Activate the module clock. */
178 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->a10_clk_ahb);
179 if (error != 0) {
180 device_printf(dev, "cannot get ahb clock\n");
181 goto fail;
182 }
183 error = clk_enable(sc->a10_clk_ahb);
184 if (error != 0) {
185 device_printf(dev, "cannot enable ahb clock\n");
186 goto fail;
187 }
188 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->a10_clk_mmc);
189 if (error != 0) {
190 device_printf(dev, "cannot get mmc clock\n");
191 goto fail;
192 }
193 error = clk_set_freq(sc->a10_clk_mmc, CARD_ID_FREQUENCY,
194 CLK_SET_ROUND_DOWN);
195 if (error != 0) {
196 device_printf(dev, "cannot init mmc clock\n");
197 goto fail;
198 }
199 error = clk_enable(sc->a10_clk_mmc);
200 if (error != 0) {
201 device_printf(dev, "cannot enable mmc clock\n");
202 goto fail;
203 }
204
205 sc->a10_timeout = 10;
206 ctx = device_get_sysctl_ctx(dev);
207 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
208 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
209 &sc->a10_timeout, 0, "Request timeout in seconds");
210
211 /* Hardware reset */
212 A10_MMC_WRITE_4(sc, A10_MMC_HWRST, 1);
213 DELAY(100);
214 A10_MMC_WRITE_4(sc, A10_MMC_HWRST, 0);
215 DELAY(500);
216
217 /* Soft Reset controller. */
218 if (a10_mmc_reset(sc) != 0) {
219 device_printf(dev, "cannot reset the controller\n");
220 goto fail;
221 }
222
223 if (a10_mmc_setup_dma(sc) != 0) {
224 device_printf(sc->a10_dev, "Couldn't setup DMA!\n");
225 goto fail;
226 }
227
228 if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0)
229 bus_width = 4;
230
231 sc->a10_host.f_min = 400000;
232 sc->a10_host.f_max = 52000000;
233 sc->a10_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
234 sc->a10_host.mode = mode_sd;
235 sc->a10_host.caps = MMC_CAP_HSPEED;
236 if (bus_width >= 4)
237 sc->a10_host.caps |= MMC_CAP_4_BIT_DATA;
238 if (bus_width >= 8)
239 sc->a10_host.caps |= MMC_CAP_8_BIT_DATA;
240
241 child = device_add_child(dev, "mmc", -1);
242 if (child == NULL) {
243 device_printf(dev, "attaching MMC bus failed!\n");
244 goto fail;
245 }
246 if (device_probe_and_attach(child) != 0) {
247 device_printf(dev, "attaching MMC child failed!\n");
248 device_delete_child(dev, child);
249 goto fail;
250 }
251
252 return (0);
253
254 fail:
255 callout_drain(&sc->a10_timeoutc);
256 mtx_destroy(&sc->a10_mtx);
257 bus_teardown_intr(dev, sc->a10_res[A10_MMC_IRQRES], sc->a10_intrhand);
258 bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res);
259
260 return (ENXIO);
261 }
262
263 static int
a10_mmc_detach(device_t dev)264 a10_mmc_detach(device_t dev)
265 {
266
267 return (EBUSY);
268 }
269
270 static void
a10_dma_desc_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int err)271 a10_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
272 {
273 struct a10_mmc_softc *sc;
274
275 sc = (struct a10_mmc_softc *)arg;
276 if (err) {
277 sc->a10_dma_map_err = err;
278 return;
279 }
280 sc->a10_dma_desc_phys = segs[0].ds_addr;
281 }
282
283 static int
a10_mmc_setup_dma(struct a10_mmc_softc * sc)284 a10_mmc_setup_dma(struct a10_mmc_softc *sc)
285 {
286 int dma_desc_size, error;
287
288 /* Allocate the DMA descriptor memory. */
289 dma_desc_size = sizeof(struct a10_mmc_dma_desc) * A10_MMC_DMA_SEGS;
290 error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev),
291 A10_MMC_DMA_ALIGN, 0,
292 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
293 dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->a10_dma_tag);
294 if (error)
295 return (error);
296 error = bus_dmamem_alloc(sc->a10_dma_tag, &sc->a10_dma_desc,
297 BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->a10_dma_map);
298 if (error)
299 return (error);
300
301 error = bus_dmamap_load(sc->a10_dma_tag, sc->a10_dma_map,
302 sc->a10_dma_desc, dma_desc_size, a10_dma_desc_cb, sc, 0);
303 if (error)
304 return (error);
305 if (sc->a10_dma_map_err)
306 return (sc->a10_dma_map_err);
307
308 /* Create the DMA map for data transfers. */
309 error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev),
310 A10_MMC_DMA_ALIGN, 0,
311 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
312 A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS, A10_MMC_DMA_SEGS,
313 A10_MMC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL,
314 &sc->a10_dma_buf_tag);
315 if (error)
316 return (error);
317 error = bus_dmamap_create(sc->a10_dma_buf_tag, 0,
318 &sc->a10_dma_buf_map);
319 if (error)
320 return (error);
321
322 return (0);
323 }
324
325 static void
a10_dma_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int err)326 a10_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
327 {
328 int i;
329 struct a10_mmc_dma_desc *dma_desc;
330 struct a10_mmc_softc *sc;
331
332 sc = (struct a10_mmc_softc *)arg;
333 sc->a10_dma_map_err = err;
334
335 if (err)
336 return;
337
338 dma_desc = sc->a10_dma_desc;
339 for (i = 0; i < nsegs; i++) {
340 dma_desc[i].buf_size = segs[i].ds_len;
341 dma_desc[i].buf_addr = segs[i].ds_addr;
342 dma_desc[i].config = A10_MMC_DMA_CONFIG_CH |
343 A10_MMC_DMA_CONFIG_OWN;
344 if (i == 0)
345 dma_desc[i].config |= A10_MMC_DMA_CONFIG_FD;
346 if (i < (nsegs - 1)) {
347 dma_desc[i].config |= A10_MMC_DMA_CONFIG_DIC;
348 dma_desc[i].next = sc->a10_dma_desc_phys +
349 ((i + 1) * sizeof(struct a10_mmc_dma_desc));
350 } else {
351 dma_desc[i].config |= A10_MMC_DMA_CONFIG_LD |
352 A10_MMC_DMA_CONFIG_ER;
353 dma_desc[i].next = 0;
354 }
355 }
356 }
357
358 static int
a10_mmc_prepare_dma(struct a10_mmc_softc * sc)359 a10_mmc_prepare_dma(struct a10_mmc_softc *sc)
360 {
361 bus_dmasync_op_t sync_op;
362 int error;
363 struct mmc_command *cmd;
364 uint32_t val;
365
366 cmd = sc->a10_req->cmd;
367 if (cmd->data->len > A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS)
368 return (EFBIG);
369 error = bus_dmamap_load(sc->a10_dma_buf_tag, sc->a10_dma_buf_map,
370 cmd->data->data, cmd->data->len, a10_dma_cb, sc, 0);
371 if (error)
372 return (error);
373 if (sc->a10_dma_map_err)
374 return (sc->a10_dma_map_err);
375
376 if (cmd->data->flags & MMC_DATA_WRITE)
377 sync_op = BUS_DMASYNC_PREWRITE;
378 else
379 sync_op = BUS_DMASYNC_PREREAD;
380 bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map, sync_op);
381 bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_PREWRITE);
382
383 /* Enable DMA */
384 val = A10_MMC_READ_4(sc, A10_MMC_GCTL);
385 val &= ~A10_MMC_CTRL_FIFO_AC_MOD;
386 val |= A10_MMC_CTRL_DMA_ENB;
387 A10_MMC_WRITE_4(sc, A10_MMC_GCTL, val);
388
389 /* Reset DMA */
390 val |= A10_MMC_CTRL_DMA_RST;
391 A10_MMC_WRITE_4(sc, A10_MMC_GCTL, val);
392
393 A10_MMC_WRITE_4(sc, A10_MMC_DMAC, A10_MMC_DMAC_IDMAC_SOFT_RST);
394 A10_MMC_WRITE_4(sc, A10_MMC_DMAC,
395 A10_MMC_DMAC_IDMAC_IDMA_ON | A10_MMC_DMAC_IDMAC_FIX_BURST);
396
397 /* Enable RX or TX DMA interrupt */
398 if (cmd->data->flags & MMC_DATA_WRITE)
399 val |= A10_MMC_IDST_TX_INT;
400 else
401 val |= A10_MMC_IDST_RX_INT;
402 A10_MMC_WRITE_4(sc, A10_MMC_IDIE, val);
403
404 /* Set DMA descritptor list address */
405 A10_MMC_WRITE_4(sc, A10_MMC_DLBA, sc->a10_dma_desc_phys);
406
407 /* FIFO trigger level */
408 A10_MMC_WRITE_4(sc, A10_MMC_FWLR, A10_MMC_DMA_FTRGLEVEL);
409
410 return (0);
411 }
412
413 static int
a10_mmc_reset(struct a10_mmc_softc * sc)414 a10_mmc_reset(struct a10_mmc_softc *sc)
415 {
416 int timeout;
417
418 A10_MMC_WRITE_4(sc, A10_MMC_GCTL, A10_MMC_RESET);
419 timeout = 1000;
420 while (--timeout > 0) {
421 if ((A10_MMC_READ_4(sc, A10_MMC_GCTL) & A10_MMC_RESET) == 0)
422 break;
423 DELAY(100);
424 }
425 if (timeout == 0)
426 return (ETIMEDOUT);
427
428 /* Set the timeout. */
429 A10_MMC_WRITE_4(sc, A10_MMC_TMOR,
430 A10_MMC_TMOR_DTO_LMT_SHIFT(A10_MMC_TMOR_DTO_LMT_MASK) |
431 A10_MMC_TMOR_RTO_LMT_SHIFT(A10_MMC_TMOR_RTO_LMT_MASK));
432
433 /* Clear pending interrupts. */
434 A10_MMC_WRITE_4(sc, A10_MMC_RISR, 0xffffffff);
435 A10_MMC_WRITE_4(sc, A10_MMC_IDST, 0xffffffff);
436 /* Unmask interrupts. */
437 A10_MMC_WRITE_4(sc, A10_MMC_IMKR,
438 A10_MMC_INT_CMD_DONE | A10_MMC_INT_ERR_BIT |
439 A10_MMC_INT_DATA_OVER | A10_MMC_INT_AUTO_STOP_DONE);
440 /* Enable interrupts and AHB access. */
441 A10_MMC_WRITE_4(sc, A10_MMC_GCTL,
442 A10_MMC_READ_4(sc, A10_MMC_GCTL) | A10_MMC_CTRL_INT_ENB);
443
444 return (0);
445 }
446
447 static void
a10_mmc_req_done(struct a10_mmc_softc * sc)448 a10_mmc_req_done(struct a10_mmc_softc *sc)
449 {
450 struct mmc_command *cmd;
451 struct mmc_request *req;
452 uint32_t val, mask;
453 int retry;
454
455 cmd = sc->a10_req->cmd;
456 if (cmd->error != MMC_ERR_NONE) {
457 /* Reset the FIFO and DMA engines. */
458 mask = A10_MMC_CTRL_FIFO_RST | A10_MMC_CTRL_DMA_RST;
459 val = A10_MMC_READ_4(sc, A10_MMC_GCTL);
460 A10_MMC_WRITE_4(sc, A10_MMC_GCTL, val | mask);
461
462 retry = A10_MMC_RESET_RETRY;
463 while (--retry > 0) {
464 val = A10_MMC_READ_4(sc, A10_MMC_GCTL);
465 if ((val & mask) == 0)
466 break;
467 DELAY(10);
468 }
469 if (retry == 0)
470 device_printf(sc->a10_dev,
471 "timeout resetting DMA/FIFO\n");
472 a10_mmc_update_clock(sc, 1);
473 }
474
475 req = sc->a10_req;
476 callout_stop(&sc->a10_timeoutc);
477 sc->a10_req = NULL;
478 sc->a10_intr = 0;
479 sc->a10_resid = 0;
480 sc->a10_dma_map_err = 0;
481 sc->a10_intr_wait = 0;
482 req->done(req);
483 }
484
485 static void
a10_mmc_req_ok(struct a10_mmc_softc * sc)486 a10_mmc_req_ok(struct a10_mmc_softc *sc)
487 {
488 int timeout;
489 struct mmc_command *cmd;
490 uint32_t status;
491
492 timeout = 1000;
493 while (--timeout > 0) {
494 status = A10_MMC_READ_4(sc, A10_MMC_STAR);
495 if ((status & A10_MMC_STAR_CARD_BUSY) == 0)
496 break;
497 DELAY(1000);
498 }
499 cmd = sc->a10_req->cmd;
500 if (timeout == 0) {
501 cmd->error = MMC_ERR_FAILED;
502 a10_mmc_req_done(sc);
503 return;
504 }
505 if (cmd->flags & MMC_RSP_PRESENT) {
506 if (cmd->flags & MMC_RSP_136) {
507 cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP3);
508 cmd->resp[1] = A10_MMC_READ_4(sc, A10_MMC_RESP2);
509 cmd->resp[2] = A10_MMC_READ_4(sc, A10_MMC_RESP1);
510 cmd->resp[3] = A10_MMC_READ_4(sc, A10_MMC_RESP0);
511 } else
512 cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP0);
513 }
514 /* All data has been transferred ? */
515 if (cmd->data != NULL && (sc->a10_resid << 2) < cmd->data->len)
516 cmd->error = MMC_ERR_FAILED;
517 a10_mmc_req_done(sc);
518 }
519
520 static void
a10_mmc_timeout(void * arg)521 a10_mmc_timeout(void *arg)
522 {
523 struct a10_mmc_softc *sc;
524
525 sc = (struct a10_mmc_softc *)arg;
526 if (sc->a10_req != NULL) {
527 device_printf(sc->a10_dev, "controller timeout\n");
528 sc->a10_req->cmd->error = MMC_ERR_TIMEOUT;
529 a10_mmc_req_done(sc);
530 } else
531 device_printf(sc->a10_dev,
532 "Spurious timeout - no active request\n");
533 }
534
535 static void
a10_mmc_intr(void * arg)536 a10_mmc_intr(void *arg)
537 {
538 bus_dmasync_op_t sync_op;
539 struct a10_mmc_softc *sc;
540 struct mmc_data *data;
541 uint32_t idst, imask, rint;
542
543 sc = (struct a10_mmc_softc *)arg;
544 A10_MMC_LOCK(sc);
545 rint = A10_MMC_READ_4(sc, A10_MMC_RISR);
546 idst = A10_MMC_READ_4(sc, A10_MMC_IDST);
547 imask = A10_MMC_READ_4(sc, A10_MMC_IMKR);
548 if (idst == 0 && imask == 0 && rint == 0) {
549 A10_MMC_UNLOCK(sc);
550 return;
551 }
552 #ifdef DEBUG
553 device_printf(sc->a10_dev, "idst: %#x, imask: %#x, rint: %#x\n",
554 idst, imask, rint);
555 #endif
556 if (sc->a10_req == NULL) {
557 device_printf(sc->a10_dev,
558 "Spurious interrupt - no active request, rint: 0x%08X\n",
559 rint);
560 goto end;
561 }
562 if (rint & A10_MMC_INT_ERR_BIT) {
563 device_printf(sc->a10_dev, "error rint: 0x%08X\n", rint);
564 if (rint & A10_MMC_INT_RESP_TIMEOUT)
565 sc->a10_req->cmd->error = MMC_ERR_TIMEOUT;
566 else
567 sc->a10_req->cmd->error = MMC_ERR_FAILED;
568 a10_mmc_req_done(sc);
569 goto end;
570 }
571 if (idst & A10_MMC_IDST_ERROR) {
572 device_printf(sc->a10_dev, "error idst: 0x%08x\n", idst);
573 sc->a10_req->cmd->error = MMC_ERR_FAILED;
574 a10_mmc_req_done(sc);
575 goto end;
576 }
577
578 sc->a10_intr |= rint;
579 data = sc->a10_req->cmd->data;
580 if (data != NULL && (idst & A10_MMC_IDST_COMPLETE) != 0) {
581 if (data->flags & MMC_DATA_WRITE)
582 sync_op = BUS_DMASYNC_POSTWRITE;
583 else
584 sync_op = BUS_DMASYNC_POSTREAD;
585 bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map,
586 sync_op);
587 bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map,
588 BUS_DMASYNC_POSTWRITE);
589 bus_dmamap_unload(sc->a10_dma_buf_tag, sc->a10_dma_buf_map);
590 sc->a10_resid = data->len >> 2;
591 }
592 if ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait)
593 a10_mmc_req_ok(sc);
594
595 end:
596 A10_MMC_WRITE_4(sc, A10_MMC_IDST, idst);
597 A10_MMC_WRITE_4(sc, A10_MMC_RISR, rint);
598 A10_MMC_UNLOCK(sc);
599 }
600
601 static int
a10_mmc_request(device_t bus,device_t child,struct mmc_request * req)602 a10_mmc_request(device_t bus, device_t child, struct mmc_request *req)
603 {
604 int blksz;
605 struct a10_mmc_softc *sc;
606 struct mmc_command *cmd;
607 uint32_t cmdreg;
608 int err;
609
610 sc = device_get_softc(bus);
611 A10_MMC_LOCK(sc);
612 if (sc->a10_req) {
613 A10_MMC_UNLOCK(sc);
614 return (EBUSY);
615 }
616 sc->a10_req = req;
617 cmd = req->cmd;
618 cmdreg = A10_MMC_CMDR_LOAD;
619 if (cmd->opcode == MMC_GO_IDLE_STATE)
620 cmdreg |= A10_MMC_CMDR_SEND_INIT_SEQ;
621 if (cmd->flags & MMC_RSP_PRESENT)
622 cmdreg |= A10_MMC_CMDR_RESP_RCV;
623 if (cmd->flags & MMC_RSP_136)
624 cmdreg |= A10_MMC_CMDR_LONG_RESP;
625 if (cmd->flags & MMC_RSP_CRC)
626 cmdreg |= A10_MMC_CMDR_CHK_RESP_CRC;
627
628 sc->a10_intr = 0;
629 sc->a10_resid = 0;
630 sc->a10_intr_wait = A10_MMC_INT_CMD_DONE;
631 cmd->error = MMC_ERR_NONE;
632 if (cmd->data != NULL) {
633 sc->a10_intr_wait |= A10_MMC_INT_DATA_OVER;
634 cmdreg |= A10_MMC_CMDR_DATA_TRANS | A10_MMC_CMDR_WAIT_PRE_OVER;
635 if (cmd->data->flags & MMC_DATA_MULTI) {
636 cmdreg |= A10_MMC_CMDR_STOP_CMD_FLAG;
637 sc->a10_intr_wait |= A10_MMC_INT_AUTO_STOP_DONE;
638 }
639 if (cmd->data->flags & MMC_DATA_WRITE)
640 cmdreg |= A10_MMC_CMDR_DIR_WRITE;
641 blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
642 A10_MMC_WRITE_4(sc, A10_MMC_BKSR, blksz);
643 A10_MMC_WRITE_4(sc, A10_MMC_BYCR, cmd->data->len);
644
645 err = a10_mmc_prepare_dma(sc);
646 if (err != 0)
647 device_printf(sc->a10_dev, "prepare_dma failed: %d\n", err);
648 }
649
650 A10_MMC_WRITE_4(sc, A10_MMC_CAGR, cmd->arg);
651 A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg | cmd->opcode);
652 callout_reset(&sc->a10_timeoutc, sc->a10_timeout * hz,
653 a10_mmc_timeout, sc);
654 A10_MMC_UNLOCK(sc);
655
656 return (0);
657 }
658
659 static int
a10_mmc_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)660 a10_mmc_read_ivar(device_t bus, device_t child, int which,
661 uintptr_t *result)
662 {
663 struct a10_mmc_softc *sc;
664
665 sc = device_get_softc(bus);
666 switch (which) {
667 default:
668 return (EINVAL);
669 case MMCBR_IVAR_BUS_MODE:
670 *(int *)result = sc->a10_host.ios.bus_mode;
671 break;
672 case MMCBR_IVAR_BUS_WIDTH:
673 *(int *)result = sc->a10_host.ios.bus_width;
674 break;
675 case MMCBR_IVAR_CHIP_SELECT:
676 *(int *)result = sc->a10_host.ios.chip_select;
677 break;
678 case MMCBR_IVAR_CLOCK:
679 *(int *)result = sc->a10_host.ios.clock;
680 break;
681 case MMCBR_IVAR_F_MIN:
682 *(int *)result = sc->a10_host.f_min;
683 break;
684 case MMCBR_IVAR_F_MAX:
685 *(int *)result = sc->a10_host.f_max;
686 break;
687 case MMCBR_IVAR_HOST_OCR:
688 *(int *)result = sc->a10_host.host_ocr;
689 break;
690 case MMCBR_IVAR_MODE:
691 *(int *)result = sc->a10_host.mode;
692 break;
693 case MMCBR_IVAR_OCR:
694 *(int *)result = sc->a10_host.ocr;
695 break;
696 case MMCBR_IVAR_POWER_MODE:
697 *(int *)result = sc->a10_host.ios.power_mode;
698 break;
699 case MMCBR_IVAR_VDD:
700 *(int *)result = sc->a10_host.ios.vdd;
701 break;
702 case MMCBR_IVAR_CAPS:
703 *(int *)result = sc->a10_host.caps;
704 break;
705 case MMCBR_IVAR_MAX_DATA:
706 *(int *)result = 65535;
707 break;
708 }
709
710 return (0);
711 }
712
713 static int
a10_mmc_write_ivar(device_t bus,device_t child,int which,uintptr_t value)714 a10_mmc_write_ivar(device_t bus, device_t child, int which,
715 uintptr_t value)
716 {
717 struct a10_mmc_softc *sc;
718
719 sc = device_get_softc(bus);
720 switch (which) {
721 default:
722 return (EINVAL);
723 case MMCBR_IVAR_BUS_MODE:
724 sc->a10_host.ios.bus_mode = value;
725 break;
726 case MMCBR_IVAR_BUS_WIDTH:
727 sc->a10_host.ios.bus_width = value;
728 break;
729 case MMCBR_IVAR_CHIP_SELECT:
730 sc->a10_host.ios.chip_select = value;
731 break;
732 case MMCBR_IVAR_CLOCK:
733 sc->a10_host.ios.clock = value;
734 break;
735 case MMCBR_IVAR_MODE:
736 sc->a10_host.mode = value;
737 break;
738 case MMCBR_IVAR_OCR:
739 sc->a10_host.ocr = value;
740 break;
741 case MMCBR_IVAR_POWER_MODE:
742 sc->a10_host.ios.power_mode = value;
743 break;
744 case MMCBR_IVAR_VDD:
745 sc->a10_host.ios.vdd = value;
746 break;
747 /* These are read-only */
748 case MMCBR_IVAR_CAPS:
749 case MMCBR_IVAR_HOST_OCR:
750 case MMCBR_IVAR_F_MIN:
751 case MMCBR_IVAR_F_MAX:
752 case MMCBR_IVAR_MAX_DATA:
753 return (EINVAL);
754 }
755
756 return (0);
757 }
758
759 static int
a10_mmc_update_clock(struct a10_mmc_softc * sc,uint32_t clkon)760 a10_mmc_update_clock(struct a10_mmc_softc *sc, uint32_t clkon)
761 {
762 uint32_t cmdreg;
763 int retry;
764 uint32_t ckcr;
765
766 ckcr = A10_MMC_READ_4(sc, A10_MMC_CKCR);
767 ckcr &= ~(A10_MMC_CKCR_CCLK_ENB | A10_MMC_CKCR_CCLK_CTRL);
768
769 if (clkon)
770 ckcr |= A10_MMC_CKCR_CCLK_ENB;
771
772 A10_MMC_WRITE_4(sc, A10_MMC_CKCR, ckcr);
773
774 cmdreg = A10_MMC_CMDR_LOAD | A10_MMC_CMDR_PRG_CLK |
775 A10_MMC_CMDR_WAIT_PRE_OVER;
776 A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg);
777 retry = 0xfffff;
778 while (--retry > 0) {
779 if ((A10_MMC_READ_4(sc, A10_MMC_CMDR) & A10_MMC_CMDR_LOAD) == 0) {
780 A10_MMC_WRITE_4(sc, A10_MMC_RISR, 0xffffffff);
781 return (0);
782 }
783 DELAY(10);
784 }
785 A10_MMC_WRITE_4(sc, A10_MMC_RISR, 0xffffffff);
786 device_printf(sc->a10_dev, "timeout updating clock\n");
787
788 return (ETIMEDOUT);
789 }
790
791 static int
a10_mmc_update_ios(device_t bus,device_t child)792 a10_mmc_update_ios(device_t bus, device_t child)
793 {
794 int error;
795 struct a10_mmc_softc *sc;
796 struct mmc_ios *ios;
797 uint32_t ckcr;
798
799 sc = device_get_softc(bus);
800
801 ios = &sc->a10_host.ios;
802
803 /* Set the bus width. */
804 switch (ios->bus_width) {
805 case bus_width_1:
806 A10_MMC_WRITE_4(sc, A10_MMC_BWDR, A10_MMC_BWDR1);
807 break;
808 case bus_width_4:
809 A10_MMC_WRITE_4(sc, A10_MMC_BWDR, A10_MMC_BWDR4);
810 break;
811 case bus_width_8:
812 A10_MMC_WRITE_4(sc, A10_MMC_BWDR, A10_MMC_BWDR8);
813 break;
814 }
815
816 if (ios->clock) {
817
818 /* Disable clock */
819 error = a10_mmc_update_clock(sc, 0);
820 if (error != 0)
821 return (error);
822
823 /* Reset the divider. */
824 ckcr = A10_MMC_READ_4(sc, A10_MMC_CKCR);
825 ckcr &= ~A10_MMC_CKCR_CCLK_DIV;
826 A10_MMC_WRITE_4(sc, A10_MMC_CKCR, ckcr);
827
828 /* Set the MMC clock. */
829 error = clk_set_freq(sc->a10_clk_mmc, ios->clock,
830 CLK_SET_ROUND_DOWN);
831 if (error != 0) {
832 device_printf(sc->a10_dev,
833 "failed to set frequency to %u Hz: %d\n",
834 ios->clock, error);
835 return (error);
836 }
837
838 /* Enable clock. */
839 error = a10_mmc_update_clock(sc, 1);
840 if (error != 0)
841 return (error);
842 }
843
844
845 return (0);
846 }
847
848 static int
a10_mmc_get_ro(device_t bus,device_t child)849 a10_mmc_get_ro(device_t bus, device_t child)
850 {
851
852 return (0);
853 }
854
855 static int
a10_mmc_acquire_host(device_t bus,device_t child)856 a10_mmc_acquire_host(device_t bus, device_t child)
857 {
858 struct a10_mmc_softc *sc;
859 int error;
860
861 sc = device_get_softc(bus);
862 A10_MMC_LOCK(sc);
863 while (sc->a10_bus_busy) {
864 error = msleep(sc, &sc->a10_mtx, PCATCH, "mmchw", 0);
865 if (error != 0) {
866 A10_MMC_UNLOCK(sc);
867 return (error);
868 }
869 }
870 sc->a10_bus_busy++;
871 A10_MMC_UNLOCK(sc);
872
873 return (0);
874 }
875
876 static int
a10_mmc_release_host(device_t bus,device_t child)877 a10_mmc_release_host(device_t bus, device_t child)
878 {
879 struct a10_mmc_softc *sc;
880
881 sc = device_get_softc(bus);
882 A10_MMC_LOCK(sc);
883 sc->a10_bus_busy--;
884 wakeup(sc);
885 A10_MMC_UNLOCK(sc);
886
887 return (0);
888 }
889
890 static device_method_t a10_mmc_methods[] = {
891 /* Device interface */
892 DEVMETHOD(device_probe, a10_mmc_probe),
893 DEVMETHOD(device_attach, a10_mmc_attach),
894 DEVMETHOD(device_detach, a10_mmc_detach),
895
896 /* Bus interface */
897 DEVMETHOD(bus_read_ivar, a10_mmc_read_ivar),
898 DEVMETHOD(bus_write_ivar, a10_mmc_write_ivar),
899
900 /* MMC bridge interface */
901 DEVMETHOD(mmcbr_update_ios, a10_mmc_update_ios),
902 DEVMETHOD(mmcbr_request, a10_mmc_request),
903 DEVMETHOD(mmcbr_get_ro, a10_mmc_get_ro),
904 DEVMETHOD(mmcbr_acquire_host, a10_mmc_acquire_host),
905 DEVMETHOD(mmcbr_release_host, a10_mmc_release_host),
906
907 DEVMETHOD_END
908 };
909
910 static devclass_t a10_mmc_devclass;
911
912 static driver_t a10_mmc_driver = {
913 "a10_mmc",
914 a10_mmc_methods,
915 sizeof(struct a10_mmc_softc),
916 };
917
918 DRIVER_MODULE(a10_mmc, simplebus, a10_mmc_driver, a10_mmc_devclass, NULL,
919 NULL);
920 MMC_DECLARE_BRIDGE(a10_mmc);
921