1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/lock.h>
36 #include <sys/kernel.h>
37 #include <sys/mutex.h>
38 #include <sys/sysctl.h>
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcireg.h>
41 #include <vm/vm.h>
42 #include <vm/pmap.h>
43 #include <machine/pci_cfgreg.h>
44
45 enum {
46 CFGMECH_NONE = 0,
47 CFGMECH_1,
48 CFGMECH_PCIE,
49 };
50
51 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
52 int bytes);
53 static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
54 unsigned reg, unsigned bytes);
55 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
56 unsigned reg, int data, unsigned bytes);
57 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
58 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
59
60 SYSCTL_DECL(_hw_pci);
61
62 static int cfgmech;
63 static vm_offset_t pcie_base;
64 static int pcie_minbus, pcie_maxbus;
65 static uint32_t pcie_badslots;
66 static struct mtx pcicfg_mtx;
67 MTX_SYSINIT(pcicfg_mtx, &pcicfg_mtx, "pcicfg_mtx", MTX_SPIN);
68 static int mcfg_enable = 1;
69 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
70 "Enable support for PCI-e memory mapped config access");
71
72 /*
73 * Initialise access to PCI configuration space
74 */
75 int
pci_cfgregopen(void)76 pci_cfgregopen(void)
77 {
78 uint64_t pciebar;
79 uint16_t did, vid;
80
81 if (cfgmech != CFGMECH_NONE)
82 return (1);
83 cfgmech = CFGMECH_1;
84
85 /*
86 * Grope around in the PCI config space to see if this is a
87 * chipset that is capable of doing memory-mapped config cycles.
88 * This also implies that it can do PCIe extended config cycles.
89 */
90
91 /* Check for supported chipsets */
92 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
93 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
94 switch (vid) {
95 case 0x8086:
96 switch (did) {
97 case 0x3590:
98 case 0x3592:
99 /* Intel 7520 or 7320 */
100 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
101 pcie_cfgregopen(pciebar, 0, 255);
102 break;
103 case 0x2580:
104 case 0x2584:
105 case 0x2590:
106 /* Intel 915, 925, or 915GM */
107 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
108 pcie_cfgregopen(pciebar, 0, 255);
109 break;
110 }
111 }
112
113 return (1);
114 }
115
116 static uint32_t
pci_docfgregread(int bus,int slot,int func,int reg,int bytes)117 pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
118 {
119
120 if (cfgmech == CFGMECH_PCIE &&
121 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
122 (bus != 0 || !(1 << slot & pcie_badslots)))
123 return (pciereg_cfgread(bus, slot, func, reg, bytes));
124 else
125 return (pcireg_cfgread(bus, slot, func, reg, bytes));
126 }
127
128 /*
129 * Read configuration space register
130 */
131 u_int32_t
pci_cfgregread(int bus,int slot,int func,int reg,int bytes)132 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
133 {
134 uint32_t line;
135
136 if (cfgmech == CFGMECH_NONE)
137 return (0xffffffff);
138
139 /*
140 * Some BIOS writers seem to want to ignore the spec and put
141 * 0 in the intline rather than 255 to indicate none. Some use
142 * numbers in the range 128-254 to indicate something strange and
143 * apparently undocumented anywhere. Assume these are completely bogus
144 * and map them to 255, which the rest of the PCI code recognizes as
145 * as an invalid IRQ.
146 */
147 if (reg == PCIR_INTLINE && bytes == 1) {
148 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
149 if (line == 0 || line >= 128)
150 line = PCI_INVALID_IRQ;
151 return (line);
152 }
153 return (pci_docfgregread(bus, slot, func, reg, bytes));
154 }
155
156 /*
157 * Write configuration space register
158 */
159 void
pci_cfgregwrite(int bus,int slot,int func,int reg,u_int32_t data,int bytes)160 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
161 {
162
163 if (cfgmech == CFGMECH_NONE)
164 return;
165
166 if (cfgmech == CFGMECH_PCIE &&
167 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
168 (bus != 0 || !(1 << slot & pcie_badslots)))
169 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
170 else
171 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
172 }
173
174 /*
175 * Configuration space access using direct register operations
176 */
177
178 /* enable configuration space accesses and return data port address */
179 static int
pci_cfgenable(unsigned bus,unsigned slot,unsigned func,int reg,int bytes)180 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
181 {
182 int dataport = 0;
183
184 if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
185 (unsigned)reg <= PCI_REGMAX && bytes != 3 &&
186 (unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) {
187 outl(CONF1_ADDR_PORT, (1U << 31) | (bus << 16) | (slot << 11)
188 | (func << 8) | (reg & ~0x03));
189 dataport = CONF1_DATA_PORT + (reg & 0x03);
190 }
191 return (dataport);
192 }
193
194 /* disable configuration space accesses */
195 static void
pci_cfgdisable(void)196 pci_cfgdisable(void)
197 {
198
199 /*
200 * Do nothing. Writing a 0 to the address port can apparently
201 * confuse some bridges and cause spurious access failures.
202 */
203 }
204
205 static int
pcireg_cfgread(int bus,int slot,int func,int reg,int bytes)206 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
207 {
208 int data = -1;
209 int port;
210
211 mtx_lock_spin(&pcicfg_mtx);
212 port = pci_cfgenable(bus, slot, func, reg, bytes);
213 if (port != 0) {
214 switch (bytes) {
215 case 1:
216 data = inb(port);
217 break;
218 case 2:
219 data = inw(port);
220 break;
221 case 4:
222 data = inl(port);
223 break;
224 }
225 pci_cfgdisable();
226 }
227 mtx_unlock_spin(&pcicfg_mtx);
228 return (data);
229 }
230
231 static void
pcireg_cfgwrite(int bus,int slot,int func,int reg,int data,int bytes)232 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
233 {
234 int port;
235
236 mtx_lock_spin(&pcicfg_mtx);
237 port = pci_cfgenable(bus, slot, func, reg, bytes);
238 if (port != 0) {
239 switch (bytes) {
240 case 1:
241 outb(port, data);
242 break;
243 case 2:
244 outw(port, data);
245 break;
246 case 4:
247 outl(port, data);
248 break;
249 }
250 pci_cfgdisable();
251 }
252 mtx_unlock_spin(&pcicfg_mtx);
253 }
254
255 int
pcie_cfgregopen(uint64_t base,uint8_t minbus,uint8_t maxbus)256 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
257 {
258 uint32_t val1, val2;
259 int slot;
260
261 if (!mcfg_enable)
262 return (0);
263
264 if (minbus != 0)
265 return (0);
266
267 if (bootverbose)
268 printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
269 base);
270
271 /* XXX: We should make sure this really fits into the direct map. */
272 pcie_base = (vm_offset_t)pmap_mapdev_pciecfg(base, (maxbus + 1) << 20);
273 pcie_minbus = minbus;
274 pcie_maxbus = maxbus;
275 cfgmech = CFGMECH_PCIE;
276
277 /*
278 * On some AMD systems, some of the devices on bus 0 are
279 * inaccessible using memory-mapped PCI config access. Walk
280 * bus 0 looking for such devices. For these devices, we will
281 * fall back to using type 1 config access instead.
282 */
283 if (pci_cfgregopen() != 0) {
284 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
285 val1 = pcireg_cfgread(0, slot, 0, 0, 4);
286 if (val1 == 0xffffffff)
287 continue;
288
289 val2 = pciereg_cfgread(0, slot, 0, 0, 4);
290 if (val2 != val1)
291 pcie_badslots |= (1 << slot);
292 }
293 }
294
295 return (1);
296 }
297
298 #define PCIE_VADDR(base, reg, bus, slot, func) \
299 ((base) + \
300 ((((bus) & 0xff) << 20) | \
301 (((slot) & 0x1f) << 15) | \
302 (((func) & 0x7) << 12) | \
303 ((reg) & 0xfff)))
304
305 /*
306 * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h
307 * have a requirement that all accesses to the memory mapped PCI configuration
308 * space are done using AX class of registers.
309 * Since other vendors do not currently have any contradicting requirements
310 * the AMD access pattern is applied universally.
311 */
312
313 static int
pciereg_cfgread(int bus,unsigned slot,unsigned func,unsigned reg,unsigned bytes)314 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
315 unsigned bytes)
316 {
317 vm_offset_t va;
318 int data = -1;
319
320 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
321 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
322 return (-1);
323
324 va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
325
326 switch (bytes) {
327 case 4:
328 __asm("movl %1, %0" : "=a" (data)
329 : "m" (*(volatile uint32_t *)va));
330 break;
331 case 2:
332 __asm("movzwl %1, %0" : "=a" (data)
333 : "m" (*(volatile uint16_t *)va));
334 break;
335 case 1:
336 __asm("movzbl %1, %0" : "=a" (data)
337 : "m" (*(volatile uint8_t *)va));
338 break;
339 }
340
341 return (data);
342 }
343
344 static void
pciereg_cfgwrite(int bus,unsigned slot,unsigned func,unsigned reg,int data,unsigned bytes)345 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
346 unsigned bytes)
347 {
348 vm_offset_t va;
349
350 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
351 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
352 return;
353
354 va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
355
356 switch (bytes) {
357 case 4:
358 __asm("movl %1, %0" : "=m" (*(volatile uint32_t *)va)
359 : "a" (data));
360 break;
361 case 2:
362 __asm("movw %1, %0" : "=m" (*(volatile uint16_t *)va)
363 : "a" ((uint16_t)data));
364 break;
365 case 1:
366 __asm("movb %1, %0" : "=m" (*(volatile uint8_t *)va)
367 : "a" ((uint8_t)data));
368 break;
369 }
370 }
371