1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org>
6 * Copyright (c) 2005 - 2009 Marius Strobl <marius@FreeBSD.org>
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice unmodified, this list of conditions, and the following
14 * disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/ofw_pcibus.c 330938 2018-03-14 19:04:40Z jhb $");
33
34 #include "opt_ofw_pci.h"
35
36 #include <sys/param.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39 #include <sys/libkern.h>
40 #include <sys/module.h>
41 #include <sys/pciio.h>
42
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_pci.h>
45 #include <dev/ofw/openfirm.h>
46
47 #include <machine/bus.h>
48 #ifndef SUN4V
49 #include <machine/bus_common.h>
50 #include <machine/iommureg.h>
51 #endif
52 #include <machine/resource.h>
53
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pci_private.h>
57
58 #include <sparc64/pci/ofw_pci.h>
59
60 #include "pcib_if.h"
61 #include "pci_if.h"
62
63 /* Helper functions */
64 static void ofw_pcibus_setup_device(device_t bridge, uint32_t clock,
65 u_int busno, u_int slot, u_int func);
66
67 /* Methods */
68 static bus_child_deleted_t ofw_pcibus_child_deleted;
69 static bus_child_pnpinfo_str_t ofw_pcibus_pnpinfo_str;
70 static device_attach_t ofw_pcibus_attach;
71 static device_probe_t ofw_pcibus_probe;
72 static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
73 static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
74
75 static device_method_t ofw_pcibus_methods[] = {
76 /* Device interface */
77 DEVMETHOD(device_probe, ofw_pcibus_probe),
78 DEVMETHOD(device_attach, ofw_pcibus_attach),
79
80 /* Bus interface */
81 DEVMETHOD(bus_child_deleted, ofw_pcibus_child_deleted),
82 DEVMETHOD(bus_child_pnpinfo_str, ofw_pcibus_pnpinfo_str),
83
84 /* PCI interface */
85 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
86
87 /* ofw_bus interface */
88 DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo),
89 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
90 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
91 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
92 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
93 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
94
95 DEVMETHOD_END
96 };
97
98 struct ofw_pcibus_devinfo {
99 struct pci_devinfo opd_dinfo;
100 struct ofw_bus_devinfo opd_obdinfo;
101 };
102
103 static devclass_t pci_devclass;
104
105 DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods,
106 sizeof(struct pci_softc), pci_driver);
107 EARLY_DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0,
108 BUS_PASS_BUS);
109 MODULE_VERSION(ofw_pcibus, 1);
110 MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
111
112 static int
ofw_pcibus_probe(device_t dev)113 ofw_pcibus_probe(device_t dev)
114 {
115
116 if (ofw_bus_get_node(dev) == -1)
117 return (ENXIO);
118 device_set_desc(dev, "OFW PCI bus");
119
120 return (0);
121 }
122
123 /*
124 * Perform miscellaneous setups the firmware usually does not do for us.
125 */
126 static void
ofw_pcibus_setup_device(device_t bridge,uint32_t clock,u_int busno,u_int slot,u_int func)127 ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
128 u_int slot, u_int func)
129 {
130 #define CS_READ(n, w) \
131 PCIB_READ_CONFIG(bridge, busno, slot, func, (n), (w))
132 #define CS_WRITE(n, v, w) \
133 PCIB_WRITE_CONFIG(bridge, busno, slot, func, (n), (v), (w))
134
135 #ifndef SUN4V
136 uint32_t reg;
137
138 /*
139 * Initialize the latency timer register for busmaster devices to
140 * work properly. This is another task which the firmware doesn't
141 * always perform. The Min_Gnt register can be used to compute its
142 * recommended value: it contains the desired latency in units of
143 * 1/4 us assuming a clock rate of 33MHz. To calculate the correct
144 * latency timer value, the clock frequency of the bus (defaulting
145 * to 33MHz) should be used and no wait states assumed.
146 * For bridges, we additionally set up the bridge control and the
147 * secondary latency registers.
148 */
149 if ((CS_READ(PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) ==
150 PCIM_HDRTYPE_BRIDGE) {
151 reg = CS_READ(PCIR_BRIDGECTL_1, 1);
152 reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE |
153 PCIB_BCR_PERR_ENABLE;
154 #ifdef OFW_PCI_DEBUG
155 device_printf(bridge,
156 "bridge %d/%d/%d: control 0x%x -> 0x%x\n",
157 busno, slot, func, CS_READ(PCIR_BRIDGECTL_1, 1), reg);
158 #endif /* OFW_PCI_DEBUG */
159 CS_WRITE(PCIR_BRIDGECTL_1, reg, 1);
160
161 reg = OFW_PCI_LATENCY;
162 #ifdef OFW_PCI_DEBUG
163 device_printf(bridge,
164 "bridge %d/%d/%d: latency timer %d -> %d\n",
165 busno, slot, func, CS_READ(PCIR_SECLAT_1, 1), reg);
166 #endif /* OFW_PCI_DEBUG */
167 CS_WRITE(PCIR_SECLAT_1, reg, 1);
168 } else {
169 reg = CS_READ(PCIR_MINGNT, 1);
170 if ((int)reg > 0) {
171 switch (clock) {
172 case 33000000:
173 reg *= 8;
174 break;
175 case 66000000:
176 reg *= 4;
177 break;
178 }
179 reg = min(reg, 255);
180 } else
181 reg = OFW_PCI_LATENCY;
182 }
183 #ifdef OFW_PCI_DEBUG
184 device_printf(bridge, "device %d/%d/%d: latency timer %d -> %d\n",
185 busno, slot, func, CS_READ(PCIR_LATTIMER, 1), reg);
186 #endif /* OFW_PCI_DEBUG */
187 CS_WRITE(PCIR_LATTIMER, reg, 1);
188
189 /*
190 * Compute a value to write into the cache line size register.
191 * The role of the streaming cache is unclear in write invalidate
192 * transfers, so it is made sure that it's line size is always
193 * reached. Generally, the cache line size is fixed at 64 bytes
194 * by Fireplane/Safari, JBus and UPA.
195 */
196 CS_WRITE(PCIR_CACHELNSZ, STRBUF_LINESZ / sizeof(uint32_t), 1);
197 #endif
198
199 /*
200 * Ensure that ALi M5229 report the actual content of PCIR_PROGIF
201 * and that IDE I/O is force enabled. The former is done in order
202 * to have unique behavior across revisions as some default to
203 * hiding bits 4-6 for compliance with PCI 2.3. The latter is done
204 * as at least revision 0xc8 requires the PCIM_CMD_PORTEN bypass
205 * to be always enabled as otherwise even enabling PCIM_CMD_PORTEN
206 * results in an instant data access trap on Fire-based machines.
207 * Thus these quirks have to be handled before pci(4) adds the maps.
208 * Note that for older revisions bit 0 of register 0x50 enables the
209 * internal IDE function instead of force enabling IDE I/O.
210 */
211 if ((CS_READ(PCIR_VENDOR, 2) == 0x10b9 &&
212 CS_READ(PCIR_DEVICE, 2) == 0x5229))
213 CS_WRITE(0x50, CS_READ(0x50, 1) | 0x3, 1);
214
215 /*
216 * The preset in the intline register is usually wrong. Reset
217 * it to 255, so that the PCI code will reroute the interrupt if
218 * needed.
219 */
220 CS_WRITE(PCIR_INTLINE, PCI_INVALID_IRQ, 1);
221
222 #undef CS_READ
223 #undef CS_WRITE
224 }
225
226 static int
ofw_pcibus_attach(device_t dev)227 ofw_pcibus_attach(device_t dev)
228 {
229 device_t pcib;
230 struct ofw_pci_register pcir;
231 struct ofw_pcibus_devinfo *dinfo;
232 phandle_t node, child;
233 uint32_t clock;
234 u_int busno, domain, func, slot;
235 int error;
236
237 error = pci_attach_common(dev);
238 if (error)
239 return (error);
240 pcib = device_get_parent(dev);
241 domain = pcib_get_domain(dev);
242 busno = pcib_get_bus(dev);
243 node = ofw_bus_get_node(dev);
244
245 /*
246 * Add the PCI side of the host-PCI bridge itself to the bus.
247 * Note that we exclude the host-PCIe bridges here as these
248 * have no configuration space implemented themselves.
249 */
250 if (strcmp(device_get_name(device_get_parent(pcib)), "nexus") == 0 &&
251 ofw_bus_get_type(pcib) != NULL &&
252 strcmp(ofw_bus_get_type(pcib), OFW_TYPE_PCIE) != 0 &&
253 (dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
254 domain, busno, 0, 0, sizeof(*dinfo))) != NULL) {
255 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, node) != 0)
256 pci_freecfg((struct pci_devinfo *)dinfo);
257 else
258 pci_add_child(dev, (struct pci_devinfo *)dinfo);
259 }
260
261 if (OF_getprop(ofw_bus_get_node(pcib), "clock-frequency", &clock,
262 sizeof(clock)) == -1)
263 clock = 33000000;
264 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
265 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
266 continue;
267 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
268 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
269 /* Some OFW device trees contain dupes. */
270 if (pci_find_dbsf(domain, busno, slot, func) != NULL)
271 continue;
272 ofw_pcibus_setup_device(pcib, clock, busno, slot, func);
273 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
274 domain, busno, slot, func, sizeof(*dinfo));
275 if (dinfo == NULL)
276 continue;
277 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
278 0) {
279 pci_freecfg((struct pci_devinfo *)dinfo);
280 continue;
281 }
282 pci_add_child(dev, (struct pci_devinfo *)dinfo);
283 OFW_PCI_SETUP_DEVICE(pcib, dinfo->opd_dinfo.cfg.dev);
284 }
285
286 return (bus_generic_attach(dev));
287 }
288
289 static int
ofw_pcibus_assign_interrupt(device_t dev,device_t child)290 ofw_pcibus_assign_interrupt(device_t dev, device_t child)
291 {
292 ofw_pci_intr_t intr;
293 int isz;
294
295 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
296 sizeof(intr));
297 if (isz != sizeof(intr)) {
298 /* No property; our best guess is the intpin. */
299 intr = pci_get_intpin(child);
300 #ifndef SUN4V
301 } else if (intr >= 255) {
302 /*
303 * A fully specified interrupt (including IGN), as present on
304 * SPARCengine Ultra AX and E450. Extract the INO and return
305 * it.
306 */
307 return (INTINO(intr));
308 #endif
309 }
310 /*
311 * If we got intr from a property, it may or may not be an intpin.
312 * For on-board devices, it frequently is not, and is completely out
313 * of the valid intpin range. For PCI slots, it hopefully is,
314 * otherwise we will have trouble interfacing with non-OFW buses
315 * such as cardbus.
316 * Since we cannot tell which it is without violating layering, we
317 * will always use the route_interrupt method, and treat exceptions
318 * on the level they become apparent.
319 */
320 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
321 }
322
323 static const struct ofw_bus_devinfo *
ofw_pcibus_get_devinfo(device_t bus,device_t dev)324 ofw_pcibus_get_devinfo(device_t bus, device_t dev)
325 {
326 struct ofw_pcibus_devinfo *dinfo;
327
328 dinfo = device_get_ivars(dev);
329 return (&dinfo->opd_obdinfo);
330 }
331
332 static void
ofw_pcibus_child_deleted(device_t dev,device_t child)333 ofw_pcibus_child_deleted(device_t dev, device_t child)
334 {
335 struct ofw_pcibus_devinfo *dinfo;
336
337 dinfo = device_get_ivars(dev);
338 ofw_bus_gen_destroy_devinfo(&dinfo->opd_obdinfo);
339 pci_child_deleted(dev, child);
340 }
341
342 static int
ofw_pcibus_pnpinfo_str(device_t dev,device_t child,char * buf,size_t buflen)343 ofw_pcibus_pnpinfo_str(device_t dev, device_t child, char *buf,
344 size_t buflen)
345 {
346
347 pci_child_pnpinfo_str_method(dev, child, buf, buflen);
348 if (ofw_bus_get_node(child) != -1) {
349 strlcat(buf, " ", buflen); /* Separate info. */
350 ofw_bus_gen_child_pnpinfo_str(dev, child, buf, buflen);
351 }
352
353 return (0);
354 }
355