1 /*-
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: stable/10/sys/mips/nlm/hal/poe.h 233545 2012-03-27 14:05:12Z jchandra $
29 */
30
31 #ifndef __NLM_POE_H__
32 #define __NLM_POE_H__
33
34 /**
35 * @file_name poe.h
36 * @author Netlogic Microsystems
37 * @brief Basic definitions of XLP Packet Order Engine
38 */
39
40 /* POE specific registers */
41 #define POE_CL0_ENQ_SPILL_BASE_LO 0x0
42 #define POE_CL1_ENQ_SPILL_BASE_LO 0x2
43 #define POE_CL2_ENQ_SPILL_BASE_LO 0x4
44 #define POE_CL3_ENQ_SPILL_BASE_LO 0x6
45 #define POE_CL4_ENQ_SPILL_BASE_LO 0x8
46 #define POE_CL5_ENQ_SPILL_BASE_LO 0xa
47 #define POE_CL6_ENQ_SPILL_BASE_LO 0xc
48 #define POE_CL7_ENQ_SPILL_BASE_LO 0xe
49 #define POE_CL0_ENQ_SPILL_BASE_HI 0x1
50 #define POE_CL1_ENQ_SPILL_BASE_HI 0x3
51 #define POE_CL2_ENQ_SPILL_BASE_HI 0x5
52 #define POE_CL3_ENQ_SPILL_BASE_HI 0x7
53 #define POE_CL4_ENQ_SPILL_BASE_HI 0x9
54 #define POE_CL5_ENQ_SPILL_BASE_HI 0xb
55 #define POE_CL6_ENQ_SPILL_BASE_HI 0xd
56 #define POE_CL7_ENQ_SPILL_BASE_HI 0xf
57 #define POE_CL0_DEQ_SPILL_BASE_LO 0x10
58 #define POE_CL1_DEQ_SPILL_BASE_LO 0x12
59 #define POE_CL2_DEQ_SPILL_BASE_LO 0x14
60 #define POE_CL3_DEQ_SPILL_BASE_LO 0x16
61 #define POE_CL4_DEQ_SPILL_BASE_LO 0x18
62 #define POE_CL5_DEQ_SPILL_BASE_LO 0x1a
63 #define POE_CL6_DEQ_SPILL_BASE_LO 0x1c
64 #define POE_CL7_DEQ_SPILL_BASE_LO 0x1e
65 #define POE_CL0_DEQ_SPILL_BASE_HI 0x11
66 #define POE_CL1_DEQ_SPILL_BASE_HI 0x13
67 #define POE_CL2_DEQ_SPILL_BASE_HI 0x15
68 #define POE_CL3_DEQ_SPILL_BASE_HI 0x17
69 #define POE_CL4_DEQ_SPILL_BASE_HI 0x19
70 #define POE_CL5_DEQ_SPILL_BASE_HI 0x1b
71 #define POE_CL6_DEQ_SPILL_BASE_HI 0x1d
72 #define POE_CL7_DEQ_SPILL_BASE_HI 0x1f
73 #define POE_MSG_STORAGE_BASE_ADDR_LO 0x20
74 #define POE_MSG_STORAGE_BASE_ADDR_HI 0x21
75 #define POE_FBP_BASE_ADDR_LO 0x22
76 #define POE_FBP_BASE_ADDR_HI 0x23
77 #define POE_CL0_ENQ_SPILL_MAXLINE_LO 0x24
78 #define POE_CL1_ENQ_SPILL_MAXLINE_LO 0x25
79 #define POE_CL2_ENQ_SPILL_MAXLINE_LO 0x26
80 #define POE_CL3_ENQ_SPILL_MAXLINE_LO 0x27
81 #define POE_CL4_ENQ_SPILL_MAXLINE_LO 0x28
82 #define POE_CL5_ENQ_SPILL_MAXLINE_LO 0x29
83 #define POE_CL6_ENQ_SPILL_MAXLINE_LO 0x2a
84 #define POE_CL7_ENQ_SPILL_MAXLINE_LO 0x2b
85 #define POE_CL0_ENQ_SPILL_MAXLINE_HI 0x2c
86 #define POE_CL1_ENQ_SPILL_MAXLINE_HI 0x2d
87 #define POE_CL2_ENQ_SPILL_MAXLINE_HI 0x2e
88 #define POE_CL3_ENQ_SPILL_MAXLINE_HI 0x2f
89 #define POE_CL4_ENQ_SPILL_MAXLINE_HI 0x30
90 #define POE_CL5_ENQ_SPILL_MAXLINE_HI 0x31
91 #define POE_CL6_ENQ_SPILL_MAXLINE_HI 0x32
92 #define POE_CL7_ENQ_SPILL_MAXLINE_HI 0x33
93 #define POE_MAX_FLOW_MSG0 0x40
94 #define POE_MAX_FLOW_MSG1 0x41
95 #define POE_MAX_FLOW_MSG2 0x42
96 #define POE_MAX_FLOW_MSG3 0x43
97 #define POE_MAX_FLOW_MSG4 0x44
98 #define POE_MAX_FLOW_MSG5 0x45
99 #define POE_MAX_FLOW_MSG6 0x46
100 #define POE_MAX_FLOW_MSG7 0x47
101 #define POE_MAX_MSG_CL0 0x48
102 #define POE_MAX_MSG_CL1 0x49
103 #define POE_MAX_MSG_CL2 0x4a
104 #define POE_MAX_MSG_CL3 0x4b
105 #define POE_MAX_MSG_CL4 0x4c
106 #define POE_MAX_MSG_CL5 0x4d
107 #define POE_MAX_MSG_CL6 0x4e
108 #define POE_MAX_MSG_CL7 0x4f
109 #define POE_MAX_LOC_BUF_STG_CL0 0x50
110 #define POE_MAX_LOC_BUF_STG_CL1 0x51
111 #define POE_MAX_LOC_BUF_STG_CL2 0x52
112 #define POE_MAX_LOC_BUF_STG_CL3 0x53
113 #define POE_MAX_LOC_BUF_STG_CL4 0x54
114 #define POE_MAX_LOC_BUF_STG_CL5 0x55
115 #define POE_MAX_LOC_BUF_STG_CL6 0x56
116 #define POE_MAX_LOC_BUF_STG_CL7 0x57
117 #define POE_ENQ_MSG_COUNT0_SIZE 0x58
118 #define POE_ENQ_MSG_COUNT1_SIZE 0x59
119 #define POE_ENQ_MSG_COUNT2_SIZE 0x5a
120 #define POE_ENQ_MSG_COUNT3_SIZE 0x5b
121 #define POE_ENQ_MSG_COUNT4_SIZE 0x5c
122 #define POE_ENQ_MSG_COUNT5_SIZE 0x5d
123 #define POE_ENQ_MSG_COUNT6_SIZE 0x5e
124 #define POE_ENQ_MSG_COUNT7_SIZE 0x5f
125 #define POE_ERR_MSG_DESCRIP_LO0 0x60
126 #define POE_ERR_MSG_DESCRIP_LO1 0x62
127 #define POE_ERR_MSG_DESCRIP_LO2 0x64
128 #define POE_ERR_MSG_DESCRIP_LO3 0x66
129 #define POE_ERR_MSG_DESCRIP_HI0 0x61
130 #define POE_ERR_MSG_DESCRIP_HI1 0x63
131 #define POE_ERR_MSG_DESCRIP_HI2 0x65
132 #define POE_ERR_MSG_DESCRIP_HI3 0x67
133 #define POE_OOO_MSG_CNT_LO 0x68
134 #define POE_IN_ORDER_MSG_CNT_LO 0x69
135 #define POE_LOC_BUF_STOR_CNT_LO 0x6a
136 #define POE_EXT_BUF_STOR_CNT_LO 0x6b
137 #define POE_LOC_BUF_ALLOC_CNT_LO 0x6c
138 #define POE_EXT_BUF_ALLOC_CNT_LO 0x6d
139 #define POE_OOO_MSG_CNT_HI 0x6e
140 #define POE_IN_ORDER_MSG_CNT_HI 0x6f
141 #define POE_LOC_BUF_STOR_CNT_HI 0x70
142 #define POE_EXT_BUF_STOR_CNT_HI 0x71
143 #define POE_LOC_BUF_ALLOC_CNT_HI 0x72
144 #define POE_EXT_BUF_ALLOC_CNT_HI 0x73
145 #define POE_MODE_ERR_FLOW_ID 0x74
146 #define POE_STATISTICS_ENABLE 0x75
147 #define POE_MAX_SIZE_FLOW 0x76
148 #define POE_MAX_SIZE 0x77
149 #define POE_FBP_SP 0x78
150 #define POE_FBP_SP_EN 0x79
151 #define POE_LOC_ALLOC_EN 0x7a
152 #define POE_EXT_ALLOC_EN 0x7b
153 #define POE_DISTR_0_DROP_CNT 0xc0
154 #define POE_DISTR_1_DROP_CNT 0xc1
155 #define POE_DISTR_2_DROP_CNT 0xc2
156 #define POE_DISTR_3_DROP_CNT 0xc3
157 #define POE_DISTR_4_DROP_CNT 0xc4
158 #define POE_DISTR_5_DROP_CNT 0xc5
159 #define POE_DISTR_6_DROP_CNT 0xc6
160 #define POE_DISTR_7_DROP_CNT 0xc7
161 #define POE_DISTR_8_DROP_CNT 0xc8
162 #define POE_DISTR_9_DROP_CNT 0xc9
163 #define POE_DISTR_10_DROP_CNT 0xca
164 #define POE_DISTR_11_DROP_CNT 0xcb
165 #define POE_DISTR_12_DROP_CNT 0xcc
166 #define POE_DISTR_13_DROP_CNT 0xcd
167 #define POE_DISTR_14_DROP_CNT 0xce
168 #define POE_DISTR_15_DROP_CNT 0xcf
169 #define POE_CLASS_0_DROP_CNT 0xd0
170 #define POE_CLASS_1_DROP_CNT 0xd1
171 #define POE_CLASS_2_DROP_CNT 0xd2
172 #define POE_CLASS_3_DROP_CNT 0xd3
173 #define POE_CLASS_4_DROP_CNT 0xd4
174 #define POE_CLASS_5_DROP_CNT 0xd5
175 #define POE_CLASS_6_DROP_CNT 0xd6
176 #define POE_CLASS_7_DROP_CNT 0xd7
177 #define POE_DISTR_C0_DROP_CNT 0xd8
178 #define POE_DISTR_C1_DROP_CNT 0xd9
179 #define POE_DISTR_C2_DROP_CNT 0xda
180 #define POE_DISTR_C3_DROP_CNT 0xdb
181 #define POE_DISTR_C4_DROP_CNT 0xdc
182 #define POE_DISTR_C5_DROP_CNT 0xdd
183 #define POE_DISTR_C6_DROP_CNT 0xde
184 #define POE_DISTR_C7_DROP_CNT 0xdf
185 #define POE_CPU_DROP_CNT 0xe0
186 #define POE_MAX_FLOW_DROP_CNT 0xe1
187 #define POE_INTERRUPT_VEC 0x140
188 #define POE_INTERRUPT_MASK 0x141
189 #define POE_FATALERR_MASK 0x142
190 #define POE_IDI_CFG 0x143
191 #define POE_TIMEOUT_VALUE 0x144
192 #define POE_CACHE_ALLOC_EN 0x145
193 #define POE_FBP_ECC_ERR_CNT 0x146
194 #define POE_MSG_STRG_ECC_ERR_CNT 0x147
195 #define POE_FID_INFO_ECC_ERR_CNT 0x148
196 #define POE_MSG_INFO_ECC_ERR_CNT 0x149
197 #define POE_LL_ECC_ERR_CNT 0x14a
198 #define POE_SIZE_ECC_ERR_CNT 0x14b
199 #define POE_FMN_TXCR_ECC_ERR_CNT 0x14c
200 #define POE_ENQ_INSPIL_ECC_ERR_CNT 0x14d
201 #define POE_ENQ_OUTSPIL_ECC_ERR_CNT 0x14e
202 #define POE_DEQ_OUTSPIL_ECC_ERR_CNT 0x14f
203 #define POE_ENQ_MSG_SENT 0x150
204 #define POE_ENQ_MSG_CNT 0x151
205 #define POE_FID_RDATA 0x152
206 #define POE_FID_WDATA 0x153
207 #define POE_FID_CMD 0x154
208 #define POE_FID_ADDR 0x155
209 #define POE_MSG_INFO_CMD 0x156
210 #define POE_MSG_INFO_ADDR 0x157
211 #define POE_MSG_INFO_RDATA 0x158
212 #define POE_LL_CMD 0x159
213 #define POE_LL_ADDR 0x15a
214 #define POE_LL_RDATA 0x15b
215 #define POE_MSG_STG_CMD 0x15c
216 #define POE_MSG_STG_ADDR 0x15d
217 #define POE_MSG_STG_RDATA 0x15e
218 #define POE_DISTR_THRESHOLD_0 0x1c0
219 #define POE_DISTR_THRESHOLD_1 0x1c1
220 #define POE_DISTR_THRESHOLD_2 0x1c2
221 #define POE_DISTR_THRESHOLD_3 0x1c3
222 #define POE_DISTR_THRESHOLD_4 0x1c4
223 #define POE_DISTR_THRESHOLD(i) (0x1c0 + (i))
224 #define POE_DISTR_EN 0x1c5
225 #define POE_ENQ_SPILL_THOLD 0x1c8
226 #define POE_DEQ_SPILL_THOLD 0x1c9
227 #define POE_DEQ_SPILL_TIMER 0x1ca
228 #define POE_DISTR_CLASS_DROP_EN 0x1cb
229 #define POE_DISTR_VEC_DROP_EN 0x1cc
230 #define POE_DISTR_DROP_TIMER 0x1cd
231 #define POE_ERROR_LOG_W0 0x1ce
232 #define POE_ERROR_LOG_W1 0x1cf
233 #define POE_ERROR_LOG_W2 0x1d0
234 #define POE_ERR_INJ_CTRL0 0x1d1
235 #define POE_TX_TIMER 0x1d4
236
237 #define NUM_DIST_VEC 16
238 #define NUM_WORDS_PER_DV 16
239 #define MAX_DV_TBL_ENTRIES (NUM_DIST_VEC * NUM_WORDS_PER_DV)
240 #define POE_DIST_THRESHOLD_VAL 0xa
241
242 /*
243 * POE distribution vectors
244 *
245 * Each vector is 512 bit with msb indicating vc 512 and lsb indicating vc 0
246 * 512-bit-vector is specified as 16 32-bit words.
247 * Left most word has the vc range 511-479 right most word has vc range 31 - 0
248 * Each word has the MSB select higer vc number and LSB select lower vc num
249 */
250 #define POE_DISTVECT_BASE 0x100
251 #define POE_DISTVECT(vec) (POE_DISTVECT_BASE + 16 * (vec))
252 #define POE_DISTVECT_OFFSET(node,cpu) (4 * (3 - (node)) + (3 - (cpu)/8))
253 #define POE_DISTVECT_SHIFT(node,cpu) (((cpu) % 8 ) * 4)
254
255 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
256
257 #define nlm_read_poe_reg(b, r) nlm_read_reg(b, r)
258 #define nlm_write_poe_reg(b, r, v) nlm_write_reg(b, r, v)
259 #define nlm_read_poedv_reg(b, r) nlm_read_reg_xkphys(b, r)
260 #define nlm_write_poedv_reg(b, r, v) nlm_write_reg_xkphys(b, r, v)
261 #define nlm_get_poe_pcibase(node) \
262 nlm_pcicfg_base(XLP_IO_POE_OFFSET(node))
263 #define nlm_get_poe_regbase(node) \
264 (nlm_get_poe_pcibase(node) + XLP_IO_PCI_HDRSZ)
265 #define nlm_get_poedv_regbase(node) \
266 nlm_xkphys_map_pcibar0(nlm_get_poe_pcibase(node))
267
268 static __inline int
nlm_poe_max_flows(uint64_t poe_pcibase)269 nlm_poe_max_flows(uint64_t poe_pcibase)
270 {
271 return (nlm_read_reg(poe_pcibase, XLP_PCI_DEVINFO_REG0));
272 }
273
274 /*
275 * Helper function, calculate the distribution vector
276 * cm0, cm1, cm2, cm3 : CPU masks for nodes 0..3
277 * thr_vcmask: destination VCs for a thread
278 */
279 static __inline void
nlm_calc_poe_distvec(uint32_t cm0,uint32_t cm1,uint32_t cm2,uint32_t cm3,uint32_t thr_vcmask,uint32_t * distvec)280 nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3,
281 uint32_t thr_vcmask, uint32_t *distvec)
282 {
283 uint32_t cpumask = 0, val;
284 int i, cpu, node, startcpu, index;
285
286 thr_vcmask &= 0xf;
287 for (node = 0; node < XLP_MAX_NODES; node++) {
288 switch (node) {
289 case 0: cpumask = cm0; break;
290 case 1: cpumask = cm1; break;
291 case 2: cpumask = cm2; break;
292 case 3: cpumask = cm3; break;
293 }
294
295 for (i = 0; i < 4; i++) {
296 val = 0;
297 startcpu = 31 - i * 8;
298 for (cpu = startcpu; cpu >= startcpu - 7; cpu--) {
299 val <<= 4;
300 if (cpumask & (1U << cpu))
301 val |= thr_vcmask;
302 }
303 index = POE_DISTVECT_OFFSET(node, startcpu);
304 distvec[index] = val;
305 }
306 }
307 }
308
309 static __inline int
nlm_write_poe_distvec(uint64_t poedv_base,int vec,uint32_t * distvec)310 nlm_write_poe_distvec(uint64_t poedv_base, int vec, uint32_t *distvec)
311 {
312 uint32_t reg;
313 int i;
314
315 if (vec < 0 || vec >= NUM_DIST_VEC)
316 return (-1);
317
318 for (i = 0; i < NUM_WORDS_PER_DV; i++) {
319 reg = POE_DISTVECT(vec) + i;
320 nlm_write_poedv_reg(poedv_base, reg, distvec[i]);
321 }
322
323 return (0);
324 }
325
326 static __inline void
nlm_config_poe(uint64_t poe_base,uint64_t poedv_base)327 nlm_config_poe(uint64_t poe_base, uint64_t poedv_base)
328 {
329 uint32_t zerodv[NUM_WORDS_PER_DV];
330 int i;
331
332 /* First disable distribution vector logic */
333 nlm_write_poe_reg(poe_base, POE_DISTR_EN, 0);
334
335 memset(zerodv, 0, sizeof(zerodv));
336 for (i = 0; i < NUM_DIST_VEC; i++)
337 nlm_write_poe_distvec(poedv_base, i, zerodv);
338
339 /* set the threshold */
340 for (i = 0; i < 5; i++)
341 nlm_write_poe_reg(poe_base, POE_DISTR_THRESHOLD(i),
342 POE_DIST_THRESHOLD_VAL);
343
344 nlm_write_poe_reg(poe_base, POE_DISTR_EN, 1);
345
346 /* always enable local message store */
347 nlm_write_poe_reg(poe_base, POE_LOC_ALLOC_EN, 1);
348
349 nlm_write_poe_reg(poe_base, POE_TX_TIMER, 0x3);
350 }
351 #endif /* !(LOCORE) && !(__ASSEMBLY__) */
352 #endif
353