1 /*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_setup.c 253511 2013-07-21 03:56:57Z adrian $");
29
30 #include "opt_ddb.h"
31
32 #include <sys/param.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/cons.h>
38 #include <sys/kdb.h>
39 #include <sys/reboot.h>
40
41 #include <vm/vm.h>
42 #include <vm/vm_page.h>
43
44 #include <net/ethernet.h>
45
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
53
54 #include <mips/atheros/ar71xxreg.h>
55 #include <mips/atheros/ar933xreg.h>
56 #include <mips/atheros/ar934xreg.h>
57
58 #include <mips/atheros/ar71xx_setup.h>
59
60 #include <mips/atheros/ar71xx_cpudef.h>
61
62 #include <mips/atheros/ar71xx_chip.h>
63 #include <mips/atheros/ar724x_chip.h>
64 #include <mips/atheros/ar91xx_chip.h>
65 #include <mips/atheros/ar933x_chip.h>
66 #include <mips/atheros/ar934x_chip.h>
67
68 #define AR71XX_SYS_TYPE_LEN 128
69
70 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
71 enum ar71xx_soc_type ar71xx_soc;
72 struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
73
74 void
ar71xx_detect_sys_type(void)75 ar71xx_detect_sys_type(void)
76 {
77 char *chip = "????";
78 uint32_t id;
79 uint32_t major;
80 uint32_t minor;
81 uint32_t rev = 0;
82
83 id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
84 major = id & REV_ID_MAJOR_MASK;
85
86 switch (major) {
87 case REV_ID_MAJOR_AR71XX:
88 minor = id & AR71XX_REV_ID_MINOR_MASK;
89 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
90 rev &= AR71XX_REV_ID_REVISION_MASK;
91 ar71xx_cpu_ops = &ar71xx_chip_def;
92 switch (minor) {
93 case AR71XX_REV_ID_MINOR_AR7130:
94 ar71xx_soc = AR71XX_SOC_AR7130;
95 chip = "7130";
96 break;
97
98 case AR71XX_REV_ID_MINOR_AR7141:
99 ar71xx_soc = AR71XX_SOC_AR7141;
100 chip = "7141";
101 break;
102
103 case AR71XX_REV_ID_MINOR_AR7161:
104 ar71xx_soc = AR71XX_SOC_AR7161;
105 chip = "7161";
106 break;
107 }
108 break;
109
110 case REV_ID_MAJOR_AR7240:
111 ar71xx_soc = AR71XX_SOC_AR7240;
112 chip = "7240";
113 ar71xx_cpu_ops = &ar724x_chip_def;
114 rev = (id & AR724X_REV_ID_REVISION_MASK);
115 break;
116
117 case REV_ID_MAJOR_AR7241:
118 ar71xx_soc = AR71XX_SOC_AR7241;
119 chip = "7241";
120 ar71xx_cpu_ops = &ar724x_chip_def;
121 rev = (id & AR724X_REV_ID_REVISION_MASK);
122 break;
123
124 case REV_ID_MAJOR_AR7242:
125 ar71xx_soc = AR71XX_SOC_AR7242;
126 chip = "7242";
127 ar71xx_cpu_ops = &ar724x_chip_def;
128 rev = (id & AR724X_REV_ID_REVISION_MASK);
129 break;
130
131 case REV_ID_MAJOR_AR913X:
132 minor = id & AR91XX_REV_ID_MINOR_MASK;
133 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
134 rev &= AR91XX_REV_ID_REVISION_MASK;
135 ar71xx_cpu_ops = &ar91xx_chip_def;
136 switch (minor) {
137 case AR91XX_REV_ID_MINOR_AR9130:
138 ar71xx_soc = AR71XX_SOC_AR9130;
139 chip = "9130";
140 break;
141
142 case AR91XX_REV_ID_MINOR_AR9132:
143 ar71xx_soc = AR71XX_SOC_AR9132;
144 chip = "9132";
145 break;
146 }
147 break;
148 case REV_ID_MAJOR_AR9330:
149 minor = 0;
150 rev = (id & AR933X_REV_ID_REVISION_MASK);
151 chip = "9330";
152 ar71xx_cpu_ops = &ar933x_chip_def;
153 ar71xx_soc = AR71XX_SOC_AR9330;
154 break;
155 case REV_ID_MAJOR_AR9331:
156 minor = 1;
157 rev = (id & AR933X_REV_ID_REVISION_MASK);
158 chip = "9331";
159 ar71xx_soc = AR71XX_SOC_AR9331;
160 ar71xx_cpu_ops = &ar933x_chip_def;
161 break;
162
163 case REV_ID_MAJOR_AR9341:
164 minor = 0;
165 rev = (id & AR934X_REV_ID_REVISION_MASK);
166 chip = "9341";
167 ar71xx_soc = AR71XX_SOC_AR9341;
168 ar71xx_cpu_ops = &ar934x_chip_def;
169 break;
170
171 case REV_ID_MAJOR_AR9342:
172 minor = 0;
173 rev = (id & AR934X_REV_ID_REVISION_MASK);
174 chip = "9342";
175 ar71xx_soc = AR71XX_SOC_AR9342;
176 ar71xx_cpu_ops = &ar934x_chip_def;
177 break;
178
179 case REV_ID_MAJOR_AR9344:
180 minor = 0;
181 rev = (id & AR934X_REV_ID_REVISION_MASK);
182 chip = "9344";
183 ar71xx_soc = AR71XX_SOC_AR9344;
184 ar71xx_cpu_ops = &ar934x_chip_def;
185 break;
186
187 default:
188 panic("ar71xx: unknown chip id:0x%08x\n", id);
189 }
190
191 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
192 }
193
194 const char *
ar71xx_get_system_type(void)195 ar71xx_get_system_type(void)
196 {
197 return ar71xx_sys_type;
198 }
199
200