1 /*-
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/10/sys/dev/uart/uart_dev_sab82532.c 262649 2014-03-01 04:16:54Z imp $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <machine/bus.h>
35
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
39
40 #include <dev/ic/sab82532.h>
41
42 #include "uart_if.h"
43
44 #define DEFAULT_RCLK 29491200
45
46 /*
47 * NOTE: To allow us to read the baudrate divisor from the chip, we
48 * copy the value written to the write-only BGR register to an unused
49 * read-write register. We use TCR for that.
50 */
51
52 static int
sab82532_delay(struct uart_bas * bas)53 sab82532_delay(struct uart_bas *bas)
54 {
55 int divisor, m, n;
56 uint8_t bgr, ccr2;
57
58 bgr = uart_getreg(bas, SAB_TCR);
59 ccr2 = uart_getreg(bas, SAB_CCR2);
60 n = (bgr & 0x3f) + 1;
61 m = (bgr >> 6) | ((ccr2 >> 4) & 0xC);
62 divisor = n * (1<<m);
63
64 /* 1/10th the time to transmit 1 character (estimate). */
65 return (16000000 * divisor / bas->rclk);
66 }
67
68 static int
sab82532_divisor(int rclk,int baudrate)69 sab82532_divisor(int rclk, int baudrate)
70 {
71 int act_baud, act_div, divisor;
72 int error, m, n;
73
74 if (baudrate == 0)
75 return (0);
76
77 divisor = (rclk / (baudrate << 3) + 1) >> 1;
78 if (divisor < 2 || divisor >= 1048576)
79 return (0);
80
81 /* Find the best (N+1,M) pair. */
82 for (m = 1; m < 15; m++) {
83 n = divisor / (1<<m);
84 if (n < 1 || n > 63)
85 continue;
86 act_div = n * (1<<m);
87 act_baud = rclk / (act_div << 4);
88
89 /* 10 times error in percent: */
90 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
91
92 /* 3.0% maximum error tolerance: */
93 if (error < -30 || error > 30)
94 continue;
95
96 /* Got it. */
97 return ((n - 1) | (m << 6));
98 }
99
100 return (0);
101 }
102
103 static void
sab82532_flush(struct uart_bas * bas,int what)104 sab82532_flush(struct uart_bas *bas, int what)
105 {
106
107 if (what & UART_FLUSH_TRANSMITTER) {
108 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
109 ;
110 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES);
111 uart_barrier(bas);
112 }
113 if (what & UART_FLUSH_RECEIVER) {
114 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
115 ;
116 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES);
117 uart_barrier(bas);
118 }
119 }
120
121 static int
sab82532_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)122 sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
123 int parity)
124 {
125 int divisor;
126 uint8_t ccr2, dafo;
127
128 if (databits >= 8)
129 dafo = SAB_DAFO_CHL_CS8;
130 else if (databits == 7)
131 dafo = SAB_DAFO_CHL_CS7;
132 else if (databits == 6)
133 dafo = SAB_DAFO_CHL_CS6;
134 else
135 dafo = SAB_DAFO_CHL_CS5;
136 if (stopbits > 1)
137 dafo |= SAB_DAFO_STOP;
138 switch (parity) {
139 case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break;
140 case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break;
141 case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break;
142 case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break;
143 case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break;
144 default: return (EINVAL);
145 }
146
147 /* Set baudrate. */
148 if (baudrate > 0) {
149 divisor = sab82532_divisor(bas->rclk, baudrate);
150 if (divisor == 0)
151 return (EINVAL);
152 uart_setreg(bas, SAB_BGR, divisor & 0xff);
153 uart_barrier(bas);
154 /* Allow reading the (n-1,m) tuple from the chip. */
155 uart_setreg(bas, SAB_TCR, divisor & 0xff);
156 uart_barrier(bas);
157 ccr2 = uart_getreg(bas, SAB_CCR2);
158 ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8);
159 ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8);
160 uart_setreg(bas, SAB_CCR2, ccr2);
161 uart_barrier(bas);
162 }
163
164 uart_setreg(bas, SAB_DAFO, dafo);
165 uart_barrier(bas);
166 return (0);
167 }
168
169 /*
170 * Low-level UART interface.
171 */
172 static int sab82532_probe(struct uart_bas *bas);
173 static void sab82532_init(struct uart_bas *bas, int, int, int, int);
174 static void sab82532_term(struct uart_bas *bas);
175 static void sab82532_putc(struct uart_bas *bas, int);
176 static int sab82532_rxready(struct uart_bas *bas);
177 static int sab82532_getc(struct uart_bas *bas, struct mtx *);
178
179 static struct uart_ops uart_sab82532_ops = {
180 .probe = sab82532_probe,
181 .init = sab82532_init,
182 .term = sab82532_term,
183 .putc = sab82532_putc,
184 .rxready = sab82532_rxready,
185 .getc = sab82532_getc,
186 };
187
188 static int
sab82532_probe(struct uart_bas * bas)189 sab82532_probe(struct uart_bas *bas)
190 {
191
192 return (0);
193 }
194
195 static void
sab82532_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)196 sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
197 int parity)
198 {
199 uint8_t ccr0, pvr;
200
201 if (bas->rclk == 0)
202 bas->rclk = DEFAULT_RCLK;
203
204 /*
205 * Set all pins, except the DTR pins (pin 1 and 2) to be inputs.
206 * Pin 4 is magical, meaning that I don't know what it does, but
207 * it too has to be set to output.
208 */
209 uart_setreg(bas, SAB_PCR,
210 ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC));
211 uart_barrier(bas);
212 /* Disable port interrupts. */
213 uart_setreg(bas, SAB_PIM, 0xff);
214 uart_barrier(bas);
215 /* Interrupts are active low. */
216 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL);
217 uart_barrier(bas);
218 /* Set DTR. */
219 pvr = uart_getreg(bas, SAB_PVR);
220 switch (bas->chan) {
221 case 1:
222 pvr &= ~SAB_PVR_DTR_A;
223 break;
224 case 2:
225 pvr &= ~SAB_PVR_DTR_B;
226 break;
227 }
228 uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC);
229 uart_barrier(bas);
230
231 /* power down */
232 uart_setreg(bas, SAB_CCR0, 0);
233 uart_barrier(bas);
234
235 /* set basic configuration */
236 ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC;
237 uart_setreg(bas, SAB_CCR0, ccr0);
238 uart_barrier(bas);
239 uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7);
240 uart_barrier(bas);
241 uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE);
242 uart_barrier(bas);
243 uart_setreg(bas, SAB_CCR3, 0);
244 uart_barrier(bas);
245 uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD);
246 uart_barrier(bas);
247 uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC);
248 uart_barrier(bas);
249 uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF|
250 SAB_RFC_RFTH_32CHAR);
251 uart_barrier(bas);
252
253 sab82532_param(bas, baudrate, databits, stopbits, parity);
254
255 /* Clear interrupts. */
256 uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD);
257 uart_setreg(bas, SAB_IMR1, 0xff);
258 uart_barrier(bas);
259 uart_getreg(bas, SAB_ISR0);
260 uart_getreg(bas, SAB_ISR1);
261 uart_barrier(bas);
262
263 sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER);
264
265 /* Power up. */
266 uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU);
267 uart_barrier(bas);
268 }
269
270 static void
sab82532_term(struct uart_bas * bas)271 sab82532_term(struct uart_bas *bas)
272 {
273 uint8_t pvr;
274
275 pvr = uart_getreg(bas, SAB_PVR);
276 switch (bas->chan) {
277 case 1:
278 pvr |= SAB_PVR_DTR_A;
279 break;
280 case 2:
281 pvr |= SAB_PVR_DTR_B;
282 break;
283 }
284 uart_setreg(bas, SAB_PVR, pvr);
285 uart_barrier(bas);
286 }
287
288 static void
sab82532_putc(struct uart_bas * bas,int c)289 sab82532_putc(struct uart_bas *bas, int c)
290 {
291 int delay, limit;
292
293 /* 1/10th the time to transmit 1 character (estimate). */
294 delay = sab82532_delay(bas);
295
296 limit = 20;
297 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
298 DELAY(delay);
299 uart_setreg(bas, SAB_TIC, c);
300 limit = 20;
301 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
302 DELAY(delay);
303 }
304
305 static int
sab82532_rxready(struct uart_bas * bas)306 sab82532_rxready(struct uart_bas *bas)
307 {
308
309 return ((uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) != 0 ? 1 : 0);
310 }
311
312 static int
sab82532_getc(struct uart_bas * bas,struct mtx * hwmtx)313 sab82532_getc(struct uart_bas *bas, struct mtx *hwmtx)
314 {
315 int c, delay;
316
317 uart_lock(hwmtx);
318
319 /* 1/10th the time to transmit 1 character (estimate). */
320 delay = sab82532_delay(bas);
321
322 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) {
323 uart_unlock(hwmtx);
324 DELAY(delay);
325 uart_lock(hwmtx);
326 }
327
328 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
329 ;
330 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
331 uart_barrier(bas);
332
333 while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD))
334 DELAY(delay);
335
336 c = uart_getreg(bas, SAB_RFIFO);
337 uart_barrier(bas);
338
339 /* Blow away everything left in the FIFO... */
340 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
341 ;
342 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
343 uart_barrier(bas);
344
345 uart_unlock(hwmtx);
346
347 return (c);
348 }
349
350 /*
351 * High-level UART interface.
352 */
353 struct sab82532_softc {
354 struct uart_softc base;
355 };
356
357 static int sab82532_bus_attach(struct uart_softc *);
358 static int sab82532_bus_detach(struct uart_softc *);
359 static int sab82532_bus_flush(struct uart_softc *, int);
360 static int sab82532_bus_getsig(struct uart_softc *);
361 static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t);
362 static int sab82532_bus_ipend(struct uart_softc *);
363 static int sab82532_bus_param(struct uart_softc *, int, int, int, int);
364 static int sab82532_bus_probe(struct uart_softc *);
365 static int sab82532_bus_receive(struct uart_softc *);
366 static int sab82532_bus_setsig(struct uart_softc *, int);
367 static int sab82532_bus_transmit(struct uart_softc *);
368 static void sab82532_bus_grab(struct uart_softc *);
369 static void sab82532_bus_ungrab(struct uart_softc *);
370
371 static kobj_method_t sab82532_methods[] = {
372 KOBJMETHOD(uart_attach, sab82532_bus_attach),
373 KOBJMETHOD(uart_detach, sab82532_bus_detach),
374 KOBJMETHOD(uart_flush, sab82532_bus_flush),
375 KOBJMETHOD(uart_getsig, sab82532_bus_getsig),
376 KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl),
377 KOBJMETHOD(uart_ipend, sab82532_bus_ipend),
378 KOBJMETHOD(uart_param, sab82532_bus_param),
379 KOBJMETHOD(uart_probe, sab82532_bus_probe),
380 KOBJMETHOD(uart_receive, sab82532_bus_receive),
381 KOBJMETHOD(uart_setsig, sab82532_bus_setsig),
382 KOBJMETHOD(uart_transmit, sab82532_bus_transmit),
383 KOBJMETHOD(uart_grab, sab82532_bus_grab),
384 KOBJMETHOD(uart_ungrab, sab82532_bus_ungrab),
385 { 0, 0 }
386 };
387
388 struct uart_class uart_sab82532_class = {
389 "sab82532",
390 sab82532_methods,
391 sizeof(struct sab82532_softc),
392 .uc_ops = &uart_sab82532_ops,
393 .uc_range = 64,
394 .uc_rclk = DEFAULT_RCLK
395 };
396
397 #define SIGCHG(c, i, s, d) \
398 if (c) { \
399 i |= (i & s) ? s : s | d; \
400 } else { \
401 i = (i & s) ? (i & ~s) | d : i; \
402 }
403
404 static int
sab82532_bus_attach(struct uart_softc * sc)405 sab82532_bus_attach(struct uart_softc *sc)
406 {
407 struct uart_bas *bas;
408 uint8_t imr0, imr1;
409
410 bas = &sc->sc_bas;
411 if (sc->sc_sysdev == NULL)
412 sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE);
413
414 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
415 SAB_IMR0_RPF;
416 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
417 imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC;
418 uart_setreg(bas, SAB_IMR1, 0xff & ~imr1);
419 uart_barrier(bas);
420
421 if (sc->sc_sysdev == NULL)
422 sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS);
423 (void)sab82532_bus_getsig(sc);
424 return (0);
425 }
426
427 static int
sab82532_bus_detach(struct uart_softc * sc)428 sab82532_bus_detach(struct uart_softc *sc)
429 {
430 struct uart_bas *bas;
431
432 bas = &sc->sc_bas;
433 uart_setreg(bas, SAB_IMR0, 0xff);
434 uart_setreg(bas, SAB_IMR1, 0xff);
435 uart_barrier(bas);
436 uart_getreg(bas, SAB_ISR0);
437 uart_getreg(bas, SAB_ISR1);
438 uart_barrier(bas);
439 uart_setreg(bas, SAB_CCR0, 0);
440 uart_barrier(bas);
441 return (0);
442 }
443
444 static int
sab82532_bus_flush(struct uart_softc * sc,int what)445 sab82532_bus_flush(struct uart_softc *sc, int what)
446 {
447
448 uart_lock(sc->sc_hwmtx);
449 sab82532_flush(&sc->sc_bas, what);
450 uart_unlock(sc->sc_hwmtx);
451 return (0);
452 }
453
454 static int
sab82532_bus_getsig(struct uart_softc * sc)455 sab82532_bus_getsig(struct uart_softc *sc)
456 {
457 struct uart_bas *bas;
458 uint32_t new, old, sig;
459 uint8_t pvr, star, vstr;
460
461 bas = &sc->sc_bas;
462 do {
463 old = sc->sc_hwsig;
464 sig = old;
465 uart_lock(sc->sc_hwmtx);
466 star = uart_getreg(bas, SAB_STAR);
467 SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS);
468 vstr = uart_getreg(bas, SAB_VSTR);
469 SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD);
470 pvr = ~uart_getreg(bas, SAB_PVR);
471 switch (bas->chan) {
472 case 1:
473 pvr &= SAB_PVR_DSR_A;
474 break;
475 case 2:
476 pvr &= SAB_PVR_DSR_B;
477 break;
478 }
479 SIGCHG(pvr, sig, SER_DSR, SER_DDSR);
480 uart_unlock(sc->sc_hwmtx);
481 new = sig & ~SER_MASK_DELTA;
482 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
483 return (sig);
484 }
485
486 static int
sab82532_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)487 sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
488 {
489 struct uart_bas *bas;
490 uint8_t dafo, mode;
491 int error;
492
493 bas = &sc->sc_bas;
494 error = 0;
495 uart_lock(sc->sc_hwmtx);
496 switch (request) {
497 case UART_IOCTL_BREAK:
498 dafo = uart_getreg(bas, SAB_DAFO);
499 if (data)
500 dafo |= SAB_DAFO_XBRK;
501 else
502 dafo &= ~SAB_DAFO_XBRK;
503 uart_setreg(bas, SAB_DAFO, dafo);
504 uart_barrier(bas);
505 break;
506 case UART_IOCTL_IFLOW:
507 mode = uart_getreg(bas, SAB_MODE);
508 if (data) {
509 mode &= ~SAB_MODE_RTS;
510 mode |= SAB_MODE_FRTS;
511 } else {
512 mode |= SAB_MODE_RTS;
513 mode &= ~SAB_MODE_FRTS;
514 }
515 uart_setreg(bas, SAB_MODE, mode);
516 uart_barrier(bas);
517 break;
518 case UART_IOCTL_OFLOW:
519 mode = uart_getreg(bas, SAB_MODE);
520 if (data)
521 mode &= ~SAB_MODE_FCTS;
522 else
523 mode |= SAB_MODE_FCTS;
524 uart_setreg(bas, SAB_MODE, mode);
525 uart_barrier(bas);
526 break;
527 default:
528 error = EINVAL;
529 break;
530 }
531 uart_unlock(sc->sc_hwmtx);
532 return (error);
533 }
534
535 static int
sab82532_bus_ipend(struct uart_softc * sc)536 sab82532_bus_ipend(struct uart_softc *sc)
537 {
538 struct uart_bas *bas;
539 int ipend;
540 uint8_t isr0, isr1;
541
542 bas = &sc->sc_bas;
543 uart_lock(sc->sc_hwmtx);
544 isr0 = uart_getreg(bas, SAB_ISR0);
545 isr1 = uart_getreg(bas, SAB_ISR1);
546 uart_barrier(bas);
547 if (isr0 & SAB_ISR0_TIME) {
548 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
549 ;
550 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
551 uart_barrier(bas);
552 }
553 uart_unlock(sc->sc_hwmtx);
554
555 ipend = 0;
556 if (isr1 & SAB_ISR1_BRKT)
557 ipend |= SER_INT_BREAK;
558 if (isr0 & SAB_ISR0_RFO)
559 ipend |= SER_INT_OVERRUN;
560 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
561 ipend |= SER_INT_RXREADY;
562 if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
563 ipend |= SER_INT_SIGCHG;
564 if (isr1 & SAB_ISR1_ALLS)
565 ipend |= SER_INT_TXIDLE;
566
567 return (ipend);
568 }
569
570 static int
sab82532_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)571 sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
572 int stopbits, int parity)
573 {
574 struct uart_bas *bas;
575 int error;
576
577 bas = &sc->sc_bas;
578 uart_lock(sc->sc_hwmtx);
579 error = sab82532_param(bas, baudrate, databits, stopbits, parity);
580 uart_unlock(sc->sc_hwmtx);
581 return (error);
582 }
583
584 static int
sab82532_bus_probe(struct uart_softc * sc)585 sab82532_bus_probe(struct uart_softc *sc)
586 {
587 char buf[80];
588 const char *vstr;
589 int error;
590 char ch;
591
592 error = sab82532_probe(&sc->sc_bas);
593 if (error)
594 return (error);
595
596 sc->sc_rxfifosz = 32;
597 sc->sc_txfifosz = 32;
598
599 ch = sc->sc_bas.chan - 1 + 'A';
600
601 switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) {
602 case SAB_VSTR_V_1:
603 vstr = "v1";
604 break;
605 case SAB_VSTR_V_2:
606 vstr = "v2";
607 break;
608 case SAB_VSTR_V_32:
609 vstr = "v3.2";
610 sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */
611 sc->sc_hwoflow = 1;
612 break;
613 default:
614 vstr = "v4?";
615 break;
616 }
617
618 snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch);
619 device_set_desc_copy(sc->sc_dev, buf);
620 return (0);
621 }
622
623 static int
sab82532_bus_receive(struct uart_softc * sc)624 sab82532_bus_receive(struct uart_softc *sc)
625 {
626 struct uart_bas *bas;
627 int i, rbcl, xc;
628 uint8_t s;
629
630 bas = &sc->sc_bas;
631 uart_lock(sc->sc_hwmtx);
632 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
633 rbcl = uart_getreg(bas, SAB_RBCL) & 31;
634 if (rbcl == 0)
635 rbcl = 32;
636 for (i = 0; i < rbcl; i += 2) {
637 if (uart_rx_full(sc)) {
638 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
639 break;
640 }
641 xc = uart_getreg(bas, SAB_RFIFO);
642 s = uart_getreg(bas, SAB_RFIFO + 1);
643 if (s & SAB_RSTAT_FE)
644 xc |= UART_STAT_FRAMERR;
645 if (s & SAB_RSTAT_PE)
646 xc |= UART_STAT_PARERR;
647 uart_rx_put(sc, xc);
648 }
649 }
650
651 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
652 ;
653 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
654 uart_barrier(bas);
655 uart_unlock(sc->sc_hwmtx);
656 return (0);
657 }
658
659 static int
sab82532_bus_setsig(struct uart_softc * sc,int sig)660 sab82532_bus_setsig(struct uart_softc *sc, int sig)
661 {
662 struct uart_bas *bas;
663 uint32_t new, old;
664 uint8_t mode, pvr;
665
666 bas = &sc->sc_bas;
667 do {
668 old = sc->sc_hwsig;
669 new = old;
670 if (sig & SER_DDTR) {
671 SIGCHG(sig & SER_DTR, new, SER_DTR,
672 SER_DDTR);
673 }
674 if (sig & SER_DRTS) {
675 SIGCHG(sig & SER_RTS, new, SER_RTS,
676 SER_DRTS);
677 }
678 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
679
680 uart_lock(sc->sc_hwmtx);
681 /* Set DTR pin. */
682 pvr = uart_getreg(bas, SAB_PVR);
683 switch (bas->chan) {
684 case 1:
685 if (new & SER_DTR)
686 pvr &= ~SAB_PVR_DTR_A;
687 else
688 pvr |= SAB_PVR_DTR_A;
689 break;
690 case 2:
691 if (new & SER_DTR)
692 pvr &= ~SAB_PVR_DTR_B;
693 else
694 pvr |= SAB_PVR_DTR_B;
695 break;
696 }
697 uart_setreg(bas, SAB_PVR, pvr);
698
699 /* Set RTS pin. */
700 mode = uart_getreg(bas, SAB_MODE);
701 if (new & SER_RTS)
702 mode &= ~SAB_MODE_FRTS;
703 else
704 mode |= SAB_MODE_FRTS;
705 uart_setreg(bas, SAB_MODE, mode);
706 uart_barrier(bas);
707 uart_unlock(sc->sc_hwmtx);
708 return (0);
709 }
710
711 static int
sab82532_bus_transmit(struct uart_softc * sc)712 sab82532_bus_transmit(struct uart_softc *sc)
713 {
714 struct uart_bas *bas;
715 int i;
716
717 bas = &sc->sc_bas;
718 uart_lock(sc->sc_hwmtx);
719 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
720 ;
721 for (i = 0; i < sc->sc_txdatasz; i++)
722 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
723 uart_barrier(bas);
724 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
725 ;
726 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
727 sc->sc_txbusy = 1;
728 uart_unlock(sc->sc_hwmtx);
729 return (0);
730 }
731
732 static void
sab82532_bus_grab(struct uart_softc * sc)733 sab82532_bus_grab(struct uart_softc *sc)
734 {
735 struct uart_bas *bas;
736 uint8_t imr0;
737
738 bas = &sc->sc_bas;
739 imr0 = SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO; /* No TCD or RPF */
740 uart_lock(sc->sc_hwmtx);
741 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
742 uart_barrier(bas);
743 uart_unlock(sc->sc_hwmtx);
744 }
745
746 static void
sab82532_bus_ungrab(struct uart_softc * sc)747 sab82532_bus_ungrab(struct uart_softc *sc)
748 {
749 struct uart_bas *bas;
750 uint8_t imr0;
751
752 bas = &sc->sc_bas;
753 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
754 SAB_IMR0_RPF;
755 uart_lock(sc->sc_hwmtx);
756 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
757 uart_barrier(bas);
758 uart_unlock(sc->sc_hwmtx);
759 }
760