1 /*-
2 * Copyright (c) 2005 by David E. O'Brien <obrien@FreeBSD.org>.
3 * Copyright (c) 2003,2004 by Quinton Dolan <q@onthenet.com.au>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
16 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: if_nv.c,v 1.19 2004/08/12 14:00:05 q Exp $
28 */
29 /*
30 * NVIDIA nForce MCP Networking Adapter driver
31 *
32 * This is a port of the NVIDIA MCP Linux ethernet driver distributed by NVIDIA
33 * through their web site.
34 *
35 * All mainstream nForce and nForce2 motherboards are supported. This module
36 * is as stable, sometimes more stable, than the linux version. (Recent
37 * Linux stability issues seem to be related to some issues with newer
38 * distributions using GCC 3.x, however this don't appear to effect FreeBSD
39 * 5.x).
40 *
41 * In accordance with the NVIDIA distribution license it is necessary to
42 * link this module against the nvlibnet.o binary object included in the
43 * Linux driver source distribution. The binary component is not modified in
44 * any way and is simply linked against a FreeBSD equivalent of the nvnet.c
45 * linux kernel module "wrapper".
46 *
47 * The Linux driver uses a common code API that is shared between Win32 and
48 * i386 Linux. This abstracts the low level driver functions and uses
49 * callbacks and hooks to access the underlying hardware device. By using
50 * this same API in a FreeBSD kernel module it is possible to support the
51 * hardware without breaching the Linux source distributions licensing
52 * requirements, or obtaining the hardware programming specifications.
53 *
54 * Although not conventional, it works, and given the relatively small
55 * amount of hardware centric code, it's hopefully no more buggy than its
56 * linux counterpart.
57 *
58 * NVIDIA now support the nForce3 AMD64 platform, however I have been
59 * unable to access such a system to verify support. However, the code is
60 * reported to work with little modification when compiled with the AMD64
61 * version of the NVIDIA Linux library. All that should be necessary to make
62 * the driver work is to link it directly into the kernel, instead of as a
63 * module, and apply the docs/amd64.diff patch in this source distribution to
64 * the NVIDIA Linux driver source.
65 *
66 * This driver should work on all versions of FreeBSD since 4.9/5.1 as well
67 * as recent versions of DragonFly.
68 *
69 * Written by Quinton Dolan <q@onthenet.com.au>
70 * Portions based on existing FreeBSD network drivers.
71 * NVIDIA API usage derived from distributed NVIDIA NVNET driver source files.
72 */
73
74 #include <sys/cdefs.h>
75 __FBSDID("$FreeBSD: stable/10/sys/dev/nve/if_nve.c 243857 2012-12-04 09:32:43Z glebius $");
76
77 #include <sys/param.h>
78 #include <sys/systm.h>
79 #include <sys/sockio.h>
80 #include <sys/mbuf.h>
81 #include <sys/malloc.h>
82 #include <sys/kernel.h>
83 #include <sys/socket.h>
84 #include <sys/sysctl.h>
85 #include <sys/queue.h>
86 #include <sys/module.h>
87
88 #include <net/if.h>
89 #include <net/if_arp.h>
90 #include <net/ethernet.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/if_types.h>
94 #include <net/bpf.h>
95 #include <net/if_vlan_var.h>
96
97 #include <machine/bus.h>
98 #include <machine/resource.h>
99
100 #include <vm/vm.h> /* for vtophys */
101 #include <vm/pmap.h> /* for vtophys */
102 #include <sys/bus.h>
103 #include <sys/rman.h>
104
105 #include <dev/pci/pcireg.h>
106 #include <dev/pci/pcivar.h>
107 #include <dev/mii/mii.h>
108 #include <dev/mii/miivar.h>
109 #include "miibus_if.h"
110
111 /* Include NVIDIA Linux driver header files */
112 #include <contrib/dev/nve/nvenet_version.h>
113 #define linux
114 #include <contrib/dev/nve/basetype.h>
115 #include <contrib/dev/nve/phy.h>
116 #include "os+%DIKED-nve.h"
117 #include <contrib/dev/nve/drvinfo.h>
118 #include <contrib/dev/nve/adapter.h>
119 #undef linux
120
121 #include <dev/nve/if_nvereg.h>
122
123 MODULE_DEPEND(nve, pci, 1, 1, 1);
124 MODULE_DEPEND(nve, ether, 1, 1, 1);
125 MODULE_DEPEND(nve, miibus, 1, 1, 1);
126
127 static int nve_probe(device_t);
128 static int nve_attach(device_t);
129 static int nve_detach(device_t);
130 static void nve_init(void *);
131 static void nve_init_locked(struct nve_softc *);
132 static void nve_stop(struct nve_softc *);
133 static int nve_shutdown(device_t);
134 static int nve_init_rings(struct nve_softc *);
135 static void nve_free_rings(struct nve_softc *);
136
137 static void nve_ifstart(struct ifnet *);
138 static void nve_ifstart_locked(struct ifnet *);
139 static int nve_ioctl(struct ifnet *, u_long, caddr_t);
140 static void nve_intr(void *);
141 static void nve_tick(void *);
142 static void nve_setmulti(struct nve_softc *);
143 static void nve_watchdog(struct nve_softc *);
144 static void nve_update_stats(struct nve_softc *);
145
146 static int nve_ifmedia_upd(struct ifnet *);
147 static void nve_ifmedia_upd_locked(struct ifnet *);
148 static void nve_ifmedia_sts(struct ifnet *, struct ifmediareq *);
149 static int nve_miibus_readreg(device_t, int, int);
150 static int nve_miibus_writereg(device_t, int, int, int);
151
152 static void nve_dmamap_cb(void *, bus_dma_segment_t *, int, int);
153 static void nve_dmamap_tx_cb(void *, bus_dma_segment_t *, int, bus_size_t, int);
154
155 static NV_API_CALL NV_SINT32 nve_osalloc(PNV_VOID, PMEMORY_BLOCK);
156 static NV_API_CALL NV_SINT32 nve_osfree(PNV_VOID, PMEMORY_BLOCK);
157 static NV_API_CALL NV_SINT32 nve_osallocex(PNV_VOID, PMEMORY_BLOCKEX);
158 static NV_API_CALL NV_SINT32 nve_osfreeex(PNV_VOID, PMEMORY_BLOCKEX);
159 static NV_API_CALL NV_SINT32 nve_osclear(PNV_VOID, PNV_VOID, NV_SINT32);
160 static NV_API_CALL NV_SINT32 nve_osdelay(PNV_VOID, NV_UINT32);
161 static NV_API_CALL NV_SINT32 nve_osallocrxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID *);
162 static NV_API_CALL NV_SINT32 nve_osfreerxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID);
163 static NV_API_CALL NV_SINT32 nve_ospackettx(PNV_VOID, PNV_VOID, NV_UINT32);
164 static NV_API_CALL NV_SINT32 nve_ospacketrx(PNV_VOID, PNV_VOID, NV_UINT32, NV_UINT8 *, NV_UINT8);
165 static NV_API_CALL NV_SINT32 nve_oslinkchg(PNV_VOID, NV_SINT32);
166 static NV_API_CALL NV_SINT32 nve_osalloctimer(PNV_VOID, PNV_VOID *);
167 static NV_API_CALL NV_SINT32 nve_osfreetimer(PNV_VOID, PNV_VOID);
168 static NV_API_CALL NV_SINT32 nve_osinittimer(PNV_VOID, PNV_VOID, PTIMER_FUNC, PNV_VOID);
169 static NV_API_CALL NV_SINT32 nve_ossettimer(PNV_VOID, PNV_VOID, NV_UINT32);
170 static NV_API_CALL NV_SINT32 nve_oscanceltimer(PNV_VOID, PNV_VOID);
171
172 static NV_API_CALL NV_SINT32 nve_ospreprocpkt(PNV_VOID, PNV_VOID, PNV_VOID *, NV_UINT8 *, NV_UINT8);
173 static NV_API_CALL PNV_VOID nve_ospreprocpktnopq(PNV_VOID, PNV_VOID);
174 static NV_API_CALL NV_SINT32 nve_osindicatepkt(PNV_VOID, PNV_VOID *, NV_UINT32);
175 static NV_API_CALL NV_SINT32 nve_oslockalloc(PNV_VOID, NV_SINT32, PNV_VOID *);
176 static NV_API_CALL NV_SINT32 nve_oslockacquire(PNV_VOID, NV_SINT32, PNV_VOID);
177 static NV_API_CALL NV_SINT32 nve_oslockrelease(PNV_VOID, NV_SINT32, PNV_VOID);
178 static NV_API_CALL PNV_VOID nve_osreturnbufvirt(PNV_VOID, PNV_VOID);
179
180 static device_method_t nve_methods[] = {
181 /* Device interface */
182 DEVMETHOD(device_probe, nve_probe),
183 DEVMETHOD(device_attach, nve_attach),
184 DEVMETHOD(device_detach, nve_detach),
185 DEVMETHOD(device_shutdown, nve_shutdown),
186
187 /* MII interface */
188 DEVMETHOD(miibus_readreg, nve_miibus_readreg),
189 DEVMETHOD(miibus_writereg, nve_miibus_writereg),
190
191 DEVMETHOD_END
192 };
193
194 static driver_t nve_driver = {
195 "nve",
196 nve_methods,
197 sizeof(struct nve_softc)
198 };
199
200 static devclass_t nve_devclass;
201
202 static int nve_pollinterval = 0;
203 SYSCTL_INT(_hw, OID_AUTO, nve_pollinterval, CTLFLAG_RW,
204 &nve_pollinterval, 0, "delay between interface polls");
205
206 DRIVER_MODULE(nve, pci, nve_driver, nve_devclass, 0, 0);
207 DRIVER_MODULE(miibus, nve, miibus_driver, miibus_devclass, 0, 0);
208
209 static struct nve_type nve_devs[] = {
210 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
211 "NVIDIA nForce MCP Networking Adapter"},
212 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
213 "NVIDIA nForce2 MCP2 Networking Adapter"},
214 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1,
215 "NVIDIA nForce2 400 MCP4 Networking Adapter"},
216 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2,
217 "NVIDIA nForce2 400 MCP5 Networking Adapter"},
218 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
219 "NVIDIA nForce3 MCP3 Networking Adapter"},
220 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN,
221 "NVIDIA nForce3 250 MCP6 Networking Adapter"},
222 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
223 "NVIDIA nForce3 MCP7 Networking Adapter"},
224 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1,
225 "NVIDIA nForce4 CK804 MCP8 Networking Adapter"},
226 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2,
227 "NVIDIA nForce4 CK804 MCP9 Networking Adapter"},
228 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
229 "NVIDIA nForce MCP04 Networking Adapter"}, // MCP10
230 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
231 "NVIDIA nForce MCP04 Networking Adapter"}, // MCP11
232 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1,
233 "NVIDIA nForce 430 MCP12 Networking Adapter"},
234 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2,
235 "NVIDIA nForce 430 MCP13 Networking Adapter"},
236 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
237 "NVIDIA nForce MCP55 Networking Adapter"},
238 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
239 "NVIDIA nForce MCP55 Networking Adapter"},
240 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
241 "NVIDIA nForce MCP61 Networking Adapter"},
242 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
243 "NVIDIA nForce MCP61 Networking Adapter"},
244 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
245 "NVIDIA nForce MCP61 Networking Adapter"},
246 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
247 "NVIDIA nForce MCP61 Networking Adapter"},
248 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
249 "NVIDIA nForce MCP65 Networking Adapter"},
250 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
251 "NVIDIA nForce MCP65 Networking Adapter"},
252 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
253 "NVIDIA nForce MCP65 Networking Adapter"},
254 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
255 "NVIDIA nForce MCP65 Networking Adapter"},
256 {0, 0, NULL}
257 };
258
259 /* DMA MEM map callback function to get data segment physical address */
260 static void
nve_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)261 nve_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nsegs, int error)
262 {
263 if (error)
264 return;
265
266 KASSERT(nsegs == 1,
267 ("Too many DMA segments returned when mapping DMA memory"));
268 *(bus_addr_t *)arg = segs->ds_addr;
269 }
270
271 /* DMA RX map callback function to get data segment physical address */
272 static void
nve_dmamap_rx_cb(void * arg,bus_dma_segment_t * segs,int nsegs,bus_size_t mapsize,int error)273 nve_dmamap_rx_cb(void *arg, bus_dma_segment_t * segs, int nsegs,
274 bus_size_t mapsize, int error)
275 {
276 if (error)
277 return;
278 *(bus_addr_t *)arg = segs->ds_addr;
279 }
280
281 /*
282 * DMA TX buffer callback function to allocate fragment data segment
283 * addresses
284 */
285 static void
nve_dmamap_tx_cb(void * arg,bus_dma_segment_t * segs,int nsegs,bus_size_t mapsize,int error)286 nve_dmamap_tx_cb(void *arg, bus_dma_segment_t * segs, int nsegs, bus_size_t mapsize, int error)
287 {
288 struct nve_tx_desc *info;
289
290 info = arg;
291 if (error)
292 return;
293 KASSERT(nsegs < NV_MAX_FRAGS,
294 ("Too many DMA segments returned when mapping mbuf"));
295 info->numfrags = nsegs;
296 bcopy(segs, info->frags, nsegs * sizeof(bus_dma_segment_t));
297 }
298
299 /* Probe for supported hardware ID's */
300 static int
nve_probe(device_t dev)301 nve_probe(device_t dev)
302 {
303 struct nve_type *t;
304
305 t = nve_devs;
306 /* Check for matching PCI DEVICE ID's */
307 while (t->name != NULL) {
308 if ((pci_get_vendor(dev) == t->vid_id) &&
309 (pci_get_device(dev) == t->dev_id)) {
310 device_set_desc(dev, t->name);
311 return (BUS_PROBE_LOW_PRIORITY);
312 }
313 t++;
314 }
315
316 return (ENXIO);
317 }
318
319 /* Attach driver and initialise hardware for use */
320 static int
nve_attach(device_t dev)321 nve_attach(device_t dev)
322 {
323 u_char eaddr[ETHER_ADDR_LEN];
324 struct nve_softc *sc;
325 struct ifnet *ifp;
326 OS_API *osapi;
327 ADAPTER_OPEN_PARAMS OpenParams;
328 int error = 0, i, rid;
329
330 if (bootverbose)
331 device_printf(dev, "nvenetlib.o version %s\n", DRIVER_VERSION);
332
333 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_attach - entry\n");
334
335 sc = device_get_softc(dev);
336
337 /* Allocate mutex */
338 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
339 MTX_DEF);
340 callout_init_mtx(&sc->stat_callout, &sc->mtx, 0);
341
342 sc->dev = dev;
343
344 /* Preinitialize data structures */
345 bzero(&OpenParams, sizeof(ADAPTER_OPEN_PARAMS));
346
347 /* Enable bus mastering */
348 pci_enable_busmaster(dev);
349
350 /* Allocate memory mapped address space */
351 rid = NV_RID;
352 sc->res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1,
353 RF_ACTIVE);
354
355 if (sc->res == NULL) {
356 device_printf(dev, "couldn't map memory\n");
357 error = ENXIO;
358 goto fail;
359 }
360 sc->sc_st = rman_get_bustag(sc->res);
361 sc->sc_sh = rman_get_bushandle(sc->res);
362
363 /* Allocate interrupt */
364 rid = 0;
365 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
366 RF_SHAREABLE | RF_ACTIVE);
367
368 if (sc->irq == NULL) {
369 device_printf(dev, "couldn't map interrupt\n");
370 error = ENXIO;
371 goto fail;
372 }
373 /* Allocate DMA tags */
374 error = bus_dma_tag_create(bus_get_dma_tag(dev),
375 4, 0, BUS_SPACE_MAXADDR_32BIT,
376 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * NV_MAX_FRAGS,
377 NV_MAX_FRAGS, MCLBYTES, 0,
378 busdma_lock_mutex, &Giant,
379 &sc->mtag);
380 if (error) {
381 device_printf(dev, "couldn't allocate dma tag\n");
382 goto fail;
383 }
384 error = bus_dma_tag_create(bus_get_dma_tag(dev),
385 4, 0, BUS_SPACE_MAXADDR_32BIT,
386 BUS_SPACE_MAXADDR, NULL, NULL,
387 sizeof(struct nve_rx_desc) * RX_RING_SIZE, 1,
388 sizeof(struct nve_rx_desc) * RX_RING_SIZE, 0,
389 busdma_lock_mutex, &Giant,
390 &sc->rtag);
391 if (error) {
392 device_printf(dev, "couldn't allocate dma tag\n");
393 goto fail;
394 }
395 error = bus_dma_tag_create(bus_get_dma_tag(dev),
396 4, 0, BUS_SPACE_MAXADDR_32BIT,
397 BUS_SPACE_MAXADDR, NULL, NULL,
398 sizeof(struct nve_tx_desc) * TX_RING_SIZE, 1,
399 sizeof(struct nve_tx_desc) * TX_RING_SIZE, 0,
400 busdma_lock_mutex, &Giant,
401 &sc->ttag);
402 if (error) {
403 device_printf(dev, "couldn't allocate dma tag\n");
404 goto fail;
405 }
406 /* Allocate DMA safe memory and get the DMA addresses. */
407 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
408 BUS_DMA_WAITOK, &sc->tmap);
409 if (error) {
410 device_printf(dev, "couldn't allocate dma memory\n");
411 goto fail;
412 }
413 bzero(sc->tx_desc, sizeof(struct nve_tx_desc) * TX_RING_SIZE);
414 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
415 sizeof(struct nve_tx_desc) * TX_RING_SIZE, nve_dmamap_cb,
416 &sc->tx_addr, 0);
417 if (error) {
418 device_printf(dev, "couldn't map dma memory\n");
419 goto fail;
420 }
421 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
422 BUS_DMA_WAITOK, &sc->rmap);
423 if (error) {
424 device_printf(dev, "couldn't allocate dma memory\n");
425 goto fail;
426 }
427 bzero(sc->rx_desc, sizeof(struct nve_rx_desc) * RX_RING_SIZE);
428 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
429 sizeof(struct nve_rx_desc) * RX_RING_SIZE, nve_dmamap_cb,
430 &sc->rx_addr, 0);
431 if (error) {
432 device_printf(dev, "couldn't map dma memory\n");
433 goto fail;
434 }
435 /* Initialize rings. */
436 if (nve_init_rings(sc)) {
437 device_printf(dev, "failed to init rings\n");
438 error = ENXIO;
439 goto fail;
440 }
441 /* Setup NVIDIA API callback routines */
442 osapi = &sc->osapi;
443 osapi->pOSCX = sc;
444 osapi->pfnAllocMemory = nve_osalloc;
445 osapi->pfnFreeMemory = nve_osfree;
446 osapi->pfnAllocMemoryEx = nve_osallocex;
447 osapi->pfnFreeMemoryEx = nve_osfreeex;
448 osapi->pfnClearMemory = nve_osclear;
449 osapi->pfnStallExecution = nve_osdelay;
450 osapi->pfnAllocReceiveBuffer = nve_osallocrxbuf;
451 osapi->pfnFreeReceiveBuffer = nve_osfreerxbuf;
452 osapi->pfnPacketWasSent = nve_ospackettx;
453 osapi->pfnPacketWasReceived = nve_ospacketrx;
454 osapi->pfnLinkStateHasChanged = nve_oslinkchg;
455 osapi->pfnAllocTimer = nve_osalloctimer;
456 osapi->pfnFreeTimer = nve_osfreetimer;
457 osapi->pfnInitializeTimer = nve_osinittimer;
458 osapi->pfnSetTimer = nve_ossettimer;
459 osapi->pfnCancelTimer = nve_oscanceltimer;
460 osapi->pfnPreprocessPacket = nve_ospreprocpkt;
461 osapi->pfnPreprocessPacketNopq = nve_ospreprocpktnopq;
462 osapi->pfnIndicatePackets = nve_osindicatepkt;
463 osapi->pfnLockAlloc = nve_oslockalloc;
464 osapi->pfnLockAcquire = nve_oslockacquire;
465 osapi->pfnLockRelease = nve_oslockrelease;
466 osapi->pfnReturnBufferVirtual = nve_osreturnbufvirt;
467
468 sc->linkup = FALSE;
469 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + FCS_LEN;
470
471 /* TODO - We don't support hardware offload yet */
472 sc->hwmode = 1;
473 sc->media = 0;
474
475 /* Set NVIDIA API startup parameters */
476 OpenParams.MaxDpcLoop = 2;
477 OpenParams.MaxRxPkt = RX_RING_SIZE;
478 OpenParams.MaxTxPkt = TX_RING_SIZE;
479 OpenParams.SentPacketStatusSuccess = 1;
480 OpenParams.SentPacketStatusFailure = 0;
481 OpenParams.MaxRxPktToAccumulate = 6;
482 OpenParams.ulPollInterval = nve_pollinterval;
483 OpenParams.SetForcedModeEveryNthRxPacket = 0;
484 OpenParams.SetForcedModeEveryNthTxPacket = 0;
485 OpenParams.RxForcedInterrupt = 0;
486 OpenParams.TxForcedInterrupt = 0;
487 OpenParams.pOSApi = osapi;
488 OpenParams.pvHardwareBaseAddress = rman_get_virtual(sc->res);
489 OpenParams.bASFEnabled = 0;
490 OpenParams.ulDescriptorVersion = sc->hwmode;
491 OpenParams.ulMaxPacketSize = sc->max_frame_size;
492 OpenParams.DeviceId = pci_get_device(dev);
493
494 /* Open NVIDIA Hardware API */
495 error = ADAPTER_Open(&OpenParams, (void **)&(sc->hwapi), &sc->phyaddr);
496 if (error) {
497 device_printf(dev,
498 "failed to open NVIDIA Hardware API: 0x%x\n", error);
499 goto fail;
500 }
501
502 /* TODO - Add support for MODE2 hardware offload */
503
504 bzero(&sc->adapterdata, sizeof(sc->adapterdata));
505
506 sc->adapterdata.ulMediaIF = sc->media;
507 sc->adapterdata.ulModeRegTxReadCompleteEnable = 1;
508 sc->hwapi->pfnSetCommonData(sc->hwapi->pADCX, &sc->adapterdata);
509
510 /* MAC is loaded backwards into h/w reg */
511 sc->hwapi->pfnGetNodeAddress(sc->hwapi->pADCX, sc->original_mac_addr);
512 for (i = 0; i < 6; i++) {
513 eaddr[i] = sc->original_mac_addr[5 - i];
514 }
515 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, eaddr);
516
517 /* Display ethernet address ,... */
518 device_printf(dev, "Ethernet address %6D\n", eaddr, ":");
519
520 /* Allocate interface structures */
521 ifp = sc->ifp = if_alloc(IFT_ETHER);
522 if (ifp == NULL) {
523 device_printf(dev, "can not if_alloc()\n");
524 error = ENOSPC;
525 goto fail;
526 }
527
528 /* Setup interface parameters */
529 ifp->if_softc = sc;
530 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
531 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
532 ifp->if_ioctl = nve_ioctl;
533 ifp->if_start = nve_ifstart;
534 ifp->if_init = nve_init;
535 ifp->if_baudrate = IF_Mbps(100);
536 IFQ_SET_MAXLEN(&ifp->if_snd, TX_RING_SIZE - 1);
537 ifp->if_snd.ifq_drv_maxlen = TX_RING_SIZE - 1;
538 IFQ_SET_READY(&ifp->if_snd);
539 ifp->if_capabilities |= IFCAP_VLAN_MTU;
540 ifp->if_capenable |= IFCAP_VLAN_MTU;
541
542 /* Attach device for MII interface to PHY */
543 DEBUGOUT(NVE_DEBUG_INIT, "nve: do mii_attach\n");
544 error = mii_attach(dev, &sc->miibus, ifp, nve_ifmedia_upd,
545 nve_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
546 if (error != 0) {
547 device_printf(dev, "attaching PHYs failed\n");
548 goto fail;
549 }
550
551 /* Attach to OS's managers. */
552 ether_ifattach(ifp, eaddr);
553
554 /* Activate our interrupt handler. - attach last to avoid lock */
555 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
556 NULL, nve_intr, sc, &sc->sc_ih);
557 if (error) {
558 device_printf(dev, "couldn't set up interrupt handler\n");
559 goto fail;
560 }
561 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_attach - exit\n");
562
563 fail:
564 if (error)
565 nve_detach(dev);
566
567 return (error);
568 }
569
570 /* Detach interface for module unload */
571 static int
nve_detach(device_t dev)572 nve_detach(device_t dev)
573 {
574 struct nve_softc *sc = device_get_softc(dev);
575 struct ifnet *ifp;
576
577 KASSERT(mtx_initialized(&sc->mtx), ("mutex not initialized"));
578
579 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_detach - entry\n");
580
581 ifp = sc->ifp;
582
583 if (device_is_attached(dev)) {
584 ether_ifdetach(ifp);
585 NVE_LOCK(sc);
586 nve_stop(sc);
587 NVE_UNLOCK(sc);
588 callout_drain(&sc->stat_callout);
589 }
590
591 if (sc->miibus)
592 device_delete_child(dev, sc->miibus);
593 bus_generic_detach(dev);
594
595 /* Reload unreversed address back into MAC in original state */
596 if (sc->original_mac_addr)
597 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX,
598 sc->original_mac_addr);
599
600 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: do pfnClose\n");
601 /* Detach from NVIDIA hardware API */
602 if (sc->hwapi->pfnClose)
603 sc->hwapi->pfnClose(sc->hwapi->pADCX, FALSE);
604 /* Release resources */
605 if (sc->sc_ih)
606 bus_teardown_intr(sc->dev, sc->irq, sc->sc_ih);
607 if (sc->irq)
608 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
609 if (sc->res)
610 bus_release_resource(sc->dev, SYS_RES_MEMORY, NV_RID, sc->res);
611
612 nve_free_rings(sc);
613
614 if (sc->tx_desc) {
615 bus_dmamap_unload(sc->rtag, sc->rmap);
616 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
617 bus_dmamap_destroy(sc->rtag, sc->rmap);
618 }
619 if (sc->mtag)
620 bus_dma_tag_destroy(sc->mtag);
621 if (sc->ttag)
622 bus_dma_tag_destroy(sc->ttag);
623 if (sc->rtag)
624 bus_dma_tag_destroy(sc->rtag);
625
626 if (ifp)
627 if_free(ifp);
628 mtx_destroy(&sc->mtx);
629
630 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_detach - exit\n");
631
632 return (0);
633 }
634
635 /* Initialise interface and start it "RUNNING" */
636 static void
nve_init(void * xsc)637 nve_init(void *xsc)
638 {
639 struct nve_softc *sc = xsc;
640
641 NVE_LOCK(sc);
642 nve_init_locked(sc);
643 NVE_UNLOCK(sc);
644 }
645
646 static void
nve_init_locked(struct nve_softc * sc)647 nve_init_locked(struct nve_softc *sc)
648 {
649 struct ifnet *ifp;
650 int error;
651
652 NVE_LOCK_ASSERT(sc);
653 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init - entry (%d)\n", sc->linkup);
654
655 ifp = sc->ifp;
656
657 /* Do nothing if already running */
658 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
659 return;
660
661 nve_stop(sc);
662 DEBUGOUT(NVE_DEBUG_INIT, "nve: do pfnInit\n");
663
664 nve_ifmedia_upd_locked(ifp);
665
666 /* Setup Hardware interface and allocate memory structures */
667 error = sc->hwapi->pfnInit(sc->hwapi->pADCX,
668 0, /* force speed */
669 0, /* force full duplex */
670 0, /* force mode */
671 0, /* force async mode */
672 &sc->linkup);
673
674 if (error) {
675 device_printf(sc->dev,
676 "failed to start NVIDIA Hardware interface\n");
677 return;
678 }
679 /* Set the MAC address */
680 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, IF_LLADDR(sc->ifp));
681 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
682 sc->hwapi->pfnStart(sc->hwapi->pADCX);
683
684 /* Setup multicast filter */
685 nve_setmulti(sc);
686
687 /* Update interface parameters */
688 ifp->if_drv_flags |= IFF_DRV_RUNNING;
689 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
690
691 callout_reset(&sc->stat_callout, hz, nve_tick, sc);
692
693 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init - exit\n");
694
695 return;
696 }
697
698 /* Stop interface activity ie. not "RUNNING" */
699 static void
nve_stop(struct nve_softc * sc)700 nve_stop(struct nve_softc *sc)
701 {
702 struct ifnet *ifp;
703
704 NVE_LOCK_ASSERT(sc);
705
706 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_stop - entry\n");
707
708 ifp = sc->ifp;
709 sc->tx_timer = 0;
710
711 /* Cancel tick timer */
712 callout_stop(&sc->stat_callout);
713
714 /* Stop hardware activity */
715 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
716 sc->hwapi->pfnStop(sc->hwapi->pADCX, 0);
717
718 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: do pfnDeinit\n");
719 /* Shutdown interface and deallocate memory buffers */
720 if (sc->hwapi->pfnDeinit)
721 sc->hwapi->pfnDeinit(sc->hwapi->pADCX, 0);
722
723 sc->linkup = 0;
724 sc->cur_rx = 0;
725 sc->pending_rxs = 0;
726 sc->pending_txs = 0;
727
728 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
729
730 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_stop - exit\n");
731
732 return;
733 }
734
735 /* Shutdown interface for unload/reboot */
736 static int
nve_shutdown(device_t dev)737 nve_shutdown(device_t dev)
738 {
739 struct nve_softc *sc;
740
741 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_shutdown\n");
742
743 sc = device_get_softc(dev);
744
745 /* Stop hardware activity */
746 NVE_LOCK(sc);
747 nve_stop(sc);
748 NVE_UNLOCK(sc);
749
750 return (0);
751 }
752
753 /* Allocate TX ring buffers */
754 static int
nve_init_rings(struct nve_softc * sc)755 nve_init_rings(struct nve_softc *sc)
756 {
757 int error, i;
758
759 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init_rings - entry\n");
760
761 sc->cur_rx = sc->cur_tx = sc->pending_rxs = sc->pending_txs = 0;
762 /* Initialise RX ring */
763 for (i = 0; i < RX_RING_SIZE; i++) {
764 struct nve_rx_desc *desc = sc->rx_desc + i;
765 struct nve_map_buffer *buf = &desc->buf;
766
767 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
768 if (buf->mbuf == NULL) {
769 device_printf(sc->dev, "couldn't allocate mbuf\n");
770 nve_free_rings(sc);
771 return (ENOBUFS);
772 }
773 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
774 m_adj(buf->mbuf, ETHER_ALIGN);
775
776 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
777 if (error) {
778 device_printf(sc->dev, "couldn't create dma map\n");
779 nve_free_rings(sc);
780 return (error);
781 }
782 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
783 nve_dmamap_rx_cb, &desc->paddr, 0);
784 if (error) {
785 device_printf(sc->dev, "couldn't dma map mbuf\n");
786 nve_free_rings(sc);
787 return (error);
788 }
789 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
790
791 desc->buflength = buf->mbuf->m_len;
792 desc->vaddr = mtod(buf->mbuf, caddr_t);
793 }
794 bus_dmamap_sync(sc->rtag, sc->rmap,
795 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
796
797 /* Initialize TX ring */
798 for (i = 0; i < TX_RING_SIZE; i++) {
799 struct nve_tx_desc *desc = sc->tx_desc + i;
800 struct nve_map_buffer *buf = &desc->buf;
801
802 buf->mbuf = NULL;
803
804 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
805 if (error) {
806 device_printf(sc->dev, "couldn't create dma map\n");
807 nve_free_rings(sc);
808 return (error);
809 }
810 }
811 bus_dmamap_sync(sc->ttag, sc->tmap,
812 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
813
814 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init_rings - exit\n");
815
816 return (error);
817 }
818
819 /* Free the TX ring buffers */
820 static void
nve_free_rings(struct nve_softc * sc)821 nve_free_rings(struct nve_softc *sc)
822 {
823 int i;
824
825 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_free_rings - entry\n");
826
827 for (i = 0; i < RX_RING_SIZE; i++) {
828 struct nve_rx_desc *desc = sc->rx_desc + i;
829 struct nve_map_buffer *buf = &desc->buf;
830
831 if (buf->mbuf) {
832 bus_dmamap_unload(sc->mtag, buf->map);
833 bus_dmamap_destroy(sc->mtag, buf->map);
834 m_freem(buf->mbuf);
835 }
836 buf->mbuf = NULL;
837 }
838
839 for (i = 0; i < TX_RING_SIZE; i++) {
840 struct nve_tx_desc *desc = sc->tx_desc + i;
841 struct nve_map_buffer *buf = &desc->buf;
842
843 if (buf->mbuf) {
844 bus_dmamap_unload(sc->mtag, buf->map);
845 bus_dmamap_destroy(sc->mtag, buf->map);
846 m_freem(buf->mbuf);
847 }
848 buf->mbuf = NULL;
849 }
850
851 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_free_rings - exit\n");
852 }
853
854 /* Main loop for sending packets from OS to interface */
855 static void
nve_ifstart(struct ifnet * ifp)856 nve_ifstart(struct ifnet *ifp)
857 {
858 struct nve_softc *sc = ifp->if_softc;
859
860 NVE_LOCK(sc);
861 nve_ifstart_locked(ifp);
862 NVE_UNLOCK(sc);
863 }
864
865 static void
nve_ifstart_locked(struct ifnet * ifp)866 nve_ifstart_locked(struct ifnet *ifp)
867 {
868 struct nve_softc *sc = ifp->if_softc;
869 struct nve_map_buffer *buf;
870 struct mbuf *m0, *m;
871 struct nve_tx_desc *desc;
872 ADAPTER_WRITE_DATA txdata;
873 int error, i;
874
875 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_ifstart - entry\n");
876
877 NVE_LOCK_ASSERT(sc);
878
879 /* If link is down/busy or queue is empty do nothing */
880 if (ifp->if_drv_flags & IFF_DRV_OACTIVE ||
881 IFQ_DRV_IS_EMPTY(&ifp->if_snd))
882 return;
883
884 /* Transmit queued packets until sent or TX ring is full */
885 while (sc->pending_txs < TX_RING_SIZE) {
886 desc = sc->tx_desc + sc->cur_tx;
887 buf = &desc->buf;
888
889 /* Get next packet to send. */
890 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
891
892 /* If nothing to send, return. */
893 if (m0 == NULL)
894 return;
895
896 /*
897 * On nForce4, the chip doesn't interrupt on transmit,
898 * so try to flush transmitted packets from the queue
899 * if it's getting large (see note in nve_watchdog).
900 */
901 if (sc->pending_txs > TX_RING_SIZE/2) {
902 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
903 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
904 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
905 }
906
907 /* Map MBUF for DMA access */
908 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
909 nve_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
910
911 if (error && error != EFBIG) {
912 m_freem(m0);
913 sc->tx_errors++;
914 continue;
915 }
916 /*
917 * Packet has too many fragments - defrag into new mbuf
918 * cluster
919 */
920 if (error) {
921 m = m_defrag(m0, M_NOWAIT);
922 if (m == NULL) {
923 m_freem(m0);
924 sc->tx_errors++;
925 continue;
926 }
927 m0 = m;
928
929 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
930 nve_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
931 if (error) {
932 m_freem(m);
933 sc->tx_errors++;
934 continue;
935 }
936 }
937 /* Do sync on DMA bounce buffer */
938 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
939
940 buf->mbuf = m0;
941 txdata.ulNumberOfElements = desc->numfrags;
942 txdata.pvID = (PVOID)desc;
943
944 /* Put fragments into API element list */
945 txdata.ulTotalLength = buf->mbuf->m_len;
946 for (i = 0; i < desc->numfrags; i++) {
947 txdata.sElement[i].ulLength =
948 (ulong)desc->frags[i].ds_len;
949 txdata.sElement[i].pPhysical =
950 (PVOID)desc->frags[i].ds_addr;
951 }
952
953 /* Send packet to Nvidia API for transmission */
954 error = sc->hwapi->pfnWrite(sc->hwapi->pADCX, &txdata);
955
956 switch (error) {
957 case ADAPTERERR_NONE:
958 /* Packet was queued in API TX queue successfully */
959 sc->pending_txs++;
960 sc->cur_tx = (sc->cur_tx + 1) % TX_RING_SIZE;
961 break;
962
963 case ADAPTERERR_TRANSMIT_QUEUE_FULL:
964 /* The API TX queue is full - requeue the packet */
965 device_printf(sc->dev,
966 "nve_ifstart: transmit queue is full\n");
967 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
968 bus_dmamap_unload(sc->mtag, buf->map);
969 IFQ_DRV_PREPEND(&ifp->if_snd, buf->mbuf);
970 buf->mbuf = NULL;
971 return;
972
973 default:
974 /* The API failed to queue/send the packet so dump it */
975 device_printf(sc->dev, "nve_ifstart: transmit error\n");
976 bus_dmamap_unload(sc->mtag, buf->map);
977 m_freem(buf->mbuf);
978 buf->mbuf = NULL;
979 sc->tx_errors++;
980 return;
981 }
982 /* Set watchdog timer. */
983 sc->tx_timer = 8;
984
985 /* Copy packet to BPF tap */
986 BPF_MTAP(ifp, m0);
987 }
988 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
989
990 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_ifstart - exit\n");
991 }
992
993 /* Handle IOCTL events */
994 static int
nve_ioctl(struct ifnet * ifp,u_long command,caddr_t data)995 nve_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
996 {
997 struct nve_softc *sc = ifp->if_softc;
998 struct ifreq *ifr = (struct ifreq *) data;
999 struct mii_data *mii;
1000 int error = 0;
1001
1002 DEBUGOUT(NVE_DEBUG_IOCTL, "nve: nve_ioctl - entry\n");
1003
1004 switch (command) {
1005 case SIOCSIFMTU:
1006 /* Set MTU size */
1007 NVE_LOCK(sc);
1008 if (ifp->if_mtu == ifr->ifr_mtu) {
1009 NVE_UNLOCK(sc);
1010 break;
1011 }
1012 if (ifr->ifr_mtu + ifp->if_hdrlen <= MAX_PACKET_SIZE_1518) {
1013 ifp->if_mtu = ifr->ifr_mtu;
1014 nve_stop(sc);
1015 nve_init_locked(sc);
1016 } else
1017 error = EINVAL;
1018 NVE_UNLOCK(sc);
1019 break;
1020
1021 case SIOCSIFFLAGS:
1022 /* Setup interface flags */
1023 NVE_LOCK(sc);
1024 if (ifp->if_flags & IFF_UP) {
1025 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1026 nve_init_locked(sc);
1027 NVE_UNLOCK(sc);
1028 break;
1029 }
1030 } else {
1031 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1032 nve_stop(sc);
1033 NVE_UNLOCK(sc);
1034 break;
1035 }
1036 }
1037 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
1038 nve_setmulti(sc);
1039 NVE_UNLOCK(sc);
1040 break;
1041
1042 case SIOCADDMULTI:
1043 case SIOCDELMULTI:
1044 /* Setup multicast filter */
1045 NVE_LOCK(sc);
1046 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1047 nve_setmulti(sc);
1048 }
1049 NVE_UNLOCK(sc);
1050 break;
1051
1052 case SIOCGIFMEDIA:
1053 case SIOCSIFMEDIA:
1054 /* Get/Set interface media parameters */
1055 mii = device_get_softc(sc->miibus);
1056 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1057 break;
1058
1059 default:
1060 /* Everything else we forward to generic ether ioctl */
1061 error = ether_ioctl(ifp, command, data);
1062 break;
1063 }
1064
1065 DEBUGOUT(NVE_DEBUG_IOCTL, "nve: nve_ioctl - exit\n");
1066
1067 return (error);
1068 }
1069
1070 /* Interrupt service routine */
1071 static void
nve_intr(void * arg)1072 nve_intr(void *arg)
1073 {
1074 struct nve_softc *sc = arg;
1075 struct ifnet *ifp = sc->ifp;
1076
1077 DEBUGOUT(NVE_DEBUG_INTERRUPT, "nve: nve_intr - entry\n");
1078
1079 NVE_LOCK(sc);
1080 if (!ifp->if_flags & IFF_UP) {
1081 nve_stop(sc);
1082 NVE_UNLOCK(sc);
1083 return;
1084 }
1085 /* Handle interrupt event */
1086 if (sc->hwapi->pfnQueryInterrupt(sc->hwapi->pADCX)) {
1087 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
1088 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
1089 }
1090 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1091 nve_ifstart_locked(ifp);
1092
1093 /* If no pending packets we don't need a timeout */
1094 if (sc->pending_txs == 0)
1095 sc->tx_timer = 0;
1096 NVE_UNLOCK(sc);
1097
1098 DEBUGOUT(NVE_DEBUG_INTERRUPT, "nve: nve_intr - exit\n");
1099
1100 return;
1101 }
1102
1103 /* Setup multicast filters */
1104 static void
nve_setmulti(struct nve_softc * sc)1105 nve_setmulti(struct nve_softc *sc)
1106 {
1107 struct ifnet *ifp;
1108 struct ifmultiaddr *ifma;
1109 PACKET_FILTER hwfilter;
1110 int i;
1111 u_int8_t andaddr[6], oraddr[6];
1112
1113 NVE_LOCK_ASSERT(sc);
1114
1115 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_setmulti - entry\n");
1116
1117 ifp = sc->ifp;
1118
1119 /* Initialize filter */
1120 hwfilter.ulFilterFlags = 0;
1121 for (i = 0; i < 6; i++) {
1122 hwfilter.acMulticastAddress[i] = 0;
1123 hwfilter.acMulticastMask[i] = 0;
1124 }
1125
1126 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1127 /* Accept all packets */
1128 hwfilter.ulFilterFlags |= ACCEPT_ALL_PACKETS;
1129 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
1130 return;
1131 }
1132 /* Setup multicast filter */
1133 if_maddr_rlock(ifp);
1134 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1135 u_char *addrp;
1136
1137 if (ifma->ifma_addr->sa_family != AF_LINK)
1138 continue;
1139
1140 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1141 for (i = 0; i < 6; i++) {
1142 u_int8_t mcaddr = addrp[i];
1143 andaddr[i] &= mcaddr;
1144 oraddr[i] |= mcaddr;
1145 }
1146 }
1147 if_maddr_runlock(ifp);
1148 for (i = 0; i < 6; i++) {
1149 hwfilter.acMulticastAddress[i] = andaddr[i] & oraddr[i];
1150 hwfilter.acMulticastMask[i] = andaddr[i] | (~oraddr[i]);
1151 }
1152
1153 /* Send filter to NVIDIA API */
1154 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
1155
1156 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_setmulti - exit\n");
1157
1158 return;
1159 }
1160
1161 /* Change the current media/mediaopts */
1162 static int
nve_ifmedia_upd(struct ifnet * ifp)1163 nve_ifmedia_upd(struct ifnet *ifp)
1164 {
1165 struct nve_softc *sc = ifp->if_softc;
1166
1167 NVE_LOCK(sc);
1168 nve_ifmedia_upd_locked(ifp);
1169 NVE_UNLOCK(sc);
1170 return (0);
1171 }
1172
1173 static void
nve_ifmedia_upd_locked(struct ifnet * ifp)1174 nve_ifmedia_upd_locked(struct ifnet *ifp)
1175 {
1176 struct nve_softc *sc = ifp->if_softc;
1177 struct mii_data *mii;
1178 struct mii_softc *miisc;
1179
1180 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_ifmedia_upd\n");
1181
1182 NVE_LOCK_ASSERT(sc);
1183 mii = device_get_softc(sc->miibus);
1184
1185 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1186 PHY_RESET(miisc);
1187 mii_mediachg(mii);
1188 }
1189
1190 /* Update current miibus PHY status of media */
1191 static void
nve_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1192 nve_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1193 {
1194 struct nve_softc *sc;
1195 struct mii_data *mii;
1196
1197 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_ifmedia_sts\n");
1198
1199 sc = ifp->if_softc;
1200 NVE_LOCK(sc);
1201 mii = device_get_softc(sc->miibus);
1202 mii_pollstat(mii);
1203
1204 ifmr->ifm_active = mii->mii_media_active;
1205 ifmr->ifm_status = mii->mii_media_status;
1206 NVE_UNLOCK(sc);
1207
1208 return;
1209 }
1210
1211 /* miibus tick timer - maintain link status */
1212 static void
nve_tick(void * xsc)1213 nve_tick(void *xsc)
1214 {
1215 struct nve_softc *sc = xsc;
1216 struct mii_data *mii;
1217 struct ifnet *ifp;
1218
1219 NVE_LOCK_ASSERT(sc);
1220
1221 ifp = sc->ifp;
1222 nve_update_stats(sc);
1223
1224 mii = device_get_softc(sc->miibus);
1225 mii_tick(mii);
1226
1227 if (mii->mii_media_status & IFM_ACTIVE &&
1228 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1229 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1230 nve_ifstart_locked(ifp);
1231 }
1232
1233 if (sc->tx_timer > 0 && --sc->tx_timer == 0)
1234 nve_watchdog(sc);
1235 callout_reset(&sc->stat_callout, hz, nve_tick, sc);
1236
1237 return;
1238 }
1239
1240 /* Update ifnet data structure with collected interface stats from API */
1241 static void
nve_update_stats(struct nve_softc * sc)1242 nve_update_stats(struct nve_softc *sc)
1243 {
1244 struct ifnet *ifp = sc->ifp;
1245 ADAPTER_STATS stats;
1246
1247 NVE_LOCK_ASSERT(sc);
1248
1249 if (sc->hwapi) {
1250 sc->hwapi->pfnGetStatistics(sc->hwapi->pADCX, &stats);
1251
1252 ifp->if_ipackets = stats.ulSuccessfulReceptions;
1253 ifp->if_ierrors = stats.ulMissedFrames +
1254 stats.ulFailedReceptions +
1255 stats.ulCRCErrors +
1256 stats.ulFramingErrors +
1257 stats.ulOverFlowErrors;
1258
1259 ifp->if_opackets = stats.ulSuccessfulTransmissions;
1260 ifp->if_oerrors = sc->tx_errors +
1261 stats.ulFailedTransmissions +
1262 stats.ulRetryErrors +
1263 stats.ulUnderflowErrors +
1264 stats.ulLossOfCarrierErrors +
1265 stats.ulLateCollisionErrors;
1266
1267 ifp->if_collisions = stats.ulLateCollisionErrors;
1268 }
1269
1270 return;
1271 }
1272
1273 /* miibus Read PHY register wrapper - calls Nvidia API entry point */
1274 static int
nve_miibus_readreg(device_t dev,int phy,int reg)1275 nve_miibus_readreg(device_t dev, int phy, int reg)
1276 {
1277 struct nve_softc *sc = device_get_softc(dev);
1278 ULONG data;
1279
1280 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_readreg - entry\n");
1281
1282 ADAPTER_ReadPhy(sc->hwapi->pADCX, phy, reg, &data);
1283
1284 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_readreg - exit\n");
1285
1286 return (data);
1287 }
1288
1289 /* miibus Write PHY register wrapper - calls Nvidia API entry point */
1290 static int
nve_miibus_writereg(device_t dev,int phy,int reg,int data)1291 nve_miibus_writereg(device_t dev, int phy, int reg, int data)
1292 {
1293 struct nve_softc *sc = device_get_softc(dev);
1294
1295 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_writereg - entry\n");
1296
1297 ADAPTER_WritePhy(sc->hwapi->pADCX, phy, reg, (ulong)data);
1298
1299 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_writereg - exit\n");
1300
1301 return 0;
1302 }
1303
1304 /* Watchdog timer to prevent PHY lockups */
1305 static void
nve_watchdog(struct nve_softc * sc)1306 nve_watchdog(struct nve_softc *sc)
1307 {
1308 struct ifnet *ifp;
1309 int pending_txs_start;
1310
1311 NVE_LOCK_ASSERT(sc);
1312 ifp = sc->ifp;
1313
1314 /*
1315 * The nvidia driver blob defers tx completion notifications.
1316 * Thus, sometimes the watchdog timer will go off when the
1317 * tx engine is fine, but the tx completions are just deferred.
1318 * Try kicking the driver blob to clear out any pending tx
1319 * completions. If that clears up any of the pending tx
1320 * operations, then just return without printing the warning
1321 * message or resetting the adapter, as we can then conclude
1322 * the chip hasn't actually crashed (it's still sending packets).
1323 */
1324 pending_txs_start = sc->pending_txs;
1325 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
1326 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
1327 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
1328 if (sc->pending_txs < pending_txs_start)
1329 return;
1330
1331 device_printf(sc->dev, "device timeout (%d)\n", sc->pending_txs);
1332
1333 sc->tx_errors++;
1334
1335 nve_stop(sc);
1336 nve_init_locked(sc);
1337
1338 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1339 nve_ifstart_locked(ifp);
1340 }
1341
1342 /* --- Start of NVOSAPI interface --- */
1343
1344 /* Allocate DMA enabled general use memory for API */
1345 static NV_API_CALL NV_SINT32
nve_osalloc(PNV_VOID ctx,PMEMORY_BLOCK mem)1346 nve_osalloc(PNV_VOID ctx, PMEMORY_BLOCK mem)
1347 {
1348 struct nve_softc *sc;
1349 bus_addr_t mem_physical;
1350
1351 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osalloc - %d\n", mem->uiLength);
1352
1353 sc = (struct nve_softc *)ctx;
1354
1355 mem->pLogical = (PVOID)contigmalloc(mem->uiLength, M_DEVBUF,
1356 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
1357
1358 if (!mem->pLogical) {
1359 device_printf(sc->dev, "memory allocation failed\n");
1360 return (0);
1361 }
1362 memset(mem->pLogical, 0, (ulong)mem->uiLength);
1363 mem_physical = vtophys(mem->pLogical);
1364 mem->pPhysical = (PVOID)mem_physical;
1365
1366 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osalloc 0x%x/0x%x - %d\n",
1367 (uint)mem->pLogical, (uint)mem->pPhysical, (uint)mem->uiLength);
1368
1369 return (1);
1370 }
1371
1372 /* Free allocated memory */
1373 static NV_API_CALL NV_SINT32
nve_osfree(PNV_VOID ctx,PMEMORY_BLOCK mem)1374 nve_osfree(PNV_VOID ctx, PMEMORY_BLOCK mem)
1375 {
1376 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfree - 0x%x - %d\n",
1377 (uint)mem->pLogical, (uint) mem->uiLength);
1378
1379 contigfree(mem->pLogical, PAGE_SIZE, M_DEVBUF);
1380 return (1);
1381 }
1382
1383 /* Copied directly from nvnet.c */
1384 static NV_API_CALL NV_SINT32
nve_osallocex(PNV_VOID ctx,PMEMORY_BLOCKEX mem_block_ex)1385 nve_osallocex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
1386 {
1387 MEMORY_BLOCK mem_block;
1388
1389 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osallocex\n");
1390
1391 mem_block_ex->pLogical = NULL;
1392 mem_block_ex->uiLengthOrig = mem_block_ex->uiLength;
1393
1394 if ((mem_block_ex->AllocFlags & ALLOC_MEMORY_ALIGNED) &&
1395 (mem_block_ex->AlignmentSize > 1)) {
1396 DEBUGOUT(NVE_DEBUG_API, " aligning on %d\n",
1397 mem_block_ex->AlignmentSize);
1398 mem_block_ex->uiLengthOrig += mem_block_ex->AlignmentSize;
1399 }
1400 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1401
1402 if (nve_osalloc(ctx, &mem_block) == 0) {
1403 return (0);
1404 }
1405 mem_block_ex->pLogicalOrig = mem_block.pLogical;
1406 mem_block_ex->pPhysicalOrigLow = (unsigned long)mem_block.pPhysical;
1407 mem_block_ex->pPhysicalOrigHigh = 0;
1408
1409 mem_block_ex->pPhysical = mem_block.pPhysical;
1410 mem_block_ex->pLogical = mem_block.pLogical;
1411
1412 if (mem_block_ex->uiLength != mem_block_ex->uiLengthOrig) {
1413 unsigned int offset;
1414 offset = mem_block_ex->pPhysicalOrigLow &
1415 (mem_block_ex->AlignmentSize - 1);
1416
1417 if (offset) {
1418 mem_block_ex->pPhysical =
1419 (PVOID)((ulong)mem_block_ex->pPhysical +
1420 mem_block_ex->AlignmentSize - offset);
1421 mem_block_ex->pLogical =
1422 (PVOID)((ulong)mem_block_ex->pLogical +
1423 mem_block_ex->AlignmentSize - offset);
1424 } /* if (offset) */
1425 } /* if (mem_block_ex->uiLength != *mem_block_ex->uiLengthOrig) */
1426 return (1);
1427 }
1428
1429 /* Copied directly from nvnet.c */
1430 static NV_API_CALL NV_SINT32
nve_osfreeex(PNV_VOID ctx,PMEMORY_BLOCKEX mem_block_ex)1431 nve_osfreeex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
1432 {
1433 MEMORY_BLOCK mem_block;
1434
1435 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfreeex\n");
1436
1437 mem_block.pLogical = mem_block_ex->pLogicalOrig;
1438 mem_block.pPhysical = (PVOID)((ulong)mem_block_ex->pPhysicalOrigLow);
1439 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1440
1441 return (nve_osfree(ctx, &mem_block));
1442 }
1443
1444 /* Clear memory region */
1445 static NV_API_CALL NV_SINT32
nve_osclear(PNV_VOID ctx,PNV_VOID mem,NV_SINT32 length)1446 nve_osclear(PNV_VOID ctx, PNV_VOID mem, NV_SINT32 length)
1447 {
1448 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osclear\n");
1449 memset(mem, 0, length);
1450 return (1);
1451 }
1452
1453 /* Sleep for a tick */
1454 static NV_API_CALL NV_SINT32
nve_osdelay(PNV_VOID ctx,NV_UINT32 usec)1455 nve_osdelay(PNV_VOID ctx, NV_UINT32 usec)
1456 {
1457 DELAY(usec);
1458 return (1);
1459 }
1460
1461 /* Allocate memory for rx buffer */
1462 static NV_API_CALL NV_SINT32
nve_osallocrxbuf(PNV_VOID ctx,PMEMORY_BLOCK mem,PNV_VOID * id)1463 nve_osallocrxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID *id)
1464 {
1465 struct nve_softc *sc = ctx;
1466 struct nve_rx_desc *desc;
1467 struct nve_map_buffer *buf;
1468 int error;
1469
1470 if (device_is_attached(sc->dev))
1471 NVE_LOCK_ASSERT(sc);
1472
1473 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osallocrxbuf\n");
1474
1475 if (sc->pending_rxs == RX_RING_SIZE) {
1476 device_printf(sc->dev, "rx ring buffer is full\n");
1477 goto fail;
1478 }
1479 desc = sc->rx_desc + sc->cur_rx;
1480 buf = &desc->buf;
1481
1482 if (buf->mbuf == NULL) {
1483 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1484 if (buf->mbuf == NULL) {
1485 device_printf(sc->dev, "failed to allocate memory\n");
1486 goto fail;
1487 }
1488 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1489 m_adj(buf->mbuf, ETHER_ALIGN);
1490
1491 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1492 nve_dmamap_rx_cb, &desc->paddr, 0);
1493 if (error) {
1494 device_printf(sc->dev, "failed to dmamap mbuf\n");
1495 m_freem(buf->mbuf);
1496 buf->mbuf = NULL;
1497 goto fail;
1498 }
1499 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1500 desc->buflength = buf->mbuf->m_len;
1501 desc->vaddr = mtod(buf->mbuf, caddr_t);
1502 }
1503 sc->pending_rxs++;
1504 sc->cur_rx = (sc->cur_rx + 1) % RX_RING_SIZE;
1505
1506 mem->pLogical = (void *)desc->vaddr;
1507 mem->pPhysical = (void *)desc->paddr;
1508 mem->uiLength = desc->buflength;
1509 *id = (void *)desc;
1510
1511 return (1);
1512
1513 fail:
1514 return (0);
1515 }
1516
1517 /* Free the rx buffer */
1518 static NV_API_CALL NV_SINT32
nve_osfreerxbuf(PNV_VOID ctx,PMEMORY_BLOCK mem,PNV_VOID id)1519 nve_osfreerxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID id)
1520 {
1521 struct nve_softc *sc = ctx;
1522 struct nve_rx_desc *desc;
1523 struct nve_map_buffer *buf;
1524
1525 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfreerxbuf\n");
1526
1527 desc = (struct nve_rx_desc *) id;
1528 buf = &desc->buf;
1529
1530 if (buf->mbuf) {
1531 bus_dmamap_unload(sc->mtag, buf->map);
1532 bus_dmamap_destroy(sc->mtag, buf->map);
1533 m_freem(buf->mbuf);
1534 }
1535 sc->pending_rxs--;
1536 buf->mbuf = NULL;
1537
1538 return (1);
1539 }
1540
1541 /* This gets called by the Nvidia API after our TX packet has been sent */
1542 static NV_API_CALL NV_SINT32
nve_ospackettx(PNV_VOID ctx,PNV_VOID id,NV_UINT32 success)1543 nve_ospackettx(PNV_VOID ctx, PNV_VOID id, NV_UINT32 success)
1544 {
1545 struct nve_softc *sc = ctx;
1546 struct nve_map_buffer *buf;
1547 struct nve_tx_desc *desc = (struct nve_tx_desc *) id;
1548 struct ifnet *ifp;
1549
1550 NVE_LOCK_ASSERT(sc);
1551
1552 DEBUGOUT(NVE_DEBUG_API, "nve: nve_ospackettx\n");
1553
1554 ifp = sc->ifp;
1555 buf = &desc->buf;
1556 sc->pending_txs--;
1557
1558 /* Unload and free mbuf cluster */
1559 if (buf->mbuf == NULL)
1560 goto fail;
1561
1562 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
1563 bus_dmamap_unload(sc->mtag, buf->map);
1564 m_freem(buf->mbuf);
1565 buf->mbuf = NULL;
1566
1567 /* Send more packets if we have them */
1568 if (sc->pending_txs < TX_RING_SIZE)
1569 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1570
1571 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->pending_txs < TX_RING_SIZE)
1572 nve_ifstart_locked(ifp);
1573
1574 fail:
1575
1576 return (1);
1577 }
1578
1579 /* This gets called by the Nvidia API when a new packet has been received */
1580 /* XXX What is newbuf used for? XXX */
1581 static NV_API_CALL NV_SINT32
nve_ospacketrx(PNV_VOID ctx,PNV_VOID data,NV_UINT32 success,NV_UINT8 * newbuf,NV_UINT8 priority)1582 nve_ospacketrx(PNV_VOID ctx, PNV_VOID data, NV_UINT32 success, NV_UINT8 *newbuf,
1583 NV_UINT8 priority)
1584 {
1585 struct nve_softc *sc = ctx;
1586 struct ifnet *ifp;
1587 struct nve_rx_desc *desc;
1588 struct nve_map_buffer *buf;
1589 ADAPTER_READ_DATA *readdata;
1590 struct mbuf *m;
1591
1592 NVE_LOCK_ASSERT(sc);
1593
1594 DEBUGOUT(NVE_DEBUG_API, "nve: nve_ospacketrx\n");
1595
1596 ifp = sc->ifp;
1597
1598 readdata = (ADAPTER_READ_DATA *) data;
1599 desc = readdata->pvID;
1600 buf = &desc->buf;
1601 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1602
1603 if (success) {
1604 /* Sync DMA bounce buffer. */
1605 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1606
1607 /* First mbuf in packet holds the ethernet and packet headers */
1608 buf->mbuf->m_pkthdr.rcvif = ifp;
1609 buf->mbuf->m_pkthdr.len = buf->mbuf->m_len =
1610 readdata->ulTotalLength;
1611
1612 bus_dmamap_unload(sc->mtag, buf->map);
1613
1614 /* Blat the mbuf pointer, kernel will free the mbuf cluster */
1615 m = buf->mbuf;
1616 buf->mbuf = NULL;
1617
1618 /* Give mbuf to OS. */
1619 NVE_UNLOCK(sc);
1620 (*ifp->if_input)(ifp, m);
1621 NVE_LOCK(sc);
1622 if (readdata->ulFilterMatch & ADREADFL_MULTICAST_MATCH)
1623 ifp->if_imcasts++;
1624
1625 } else {
1626 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1627 bus_dmamap_unload(sc->mtag, buf->map);
1628 m_freem(buf->mbuf);
1629 buf->mbuf = NULL;
1630 }
1631
1632 sc->cur_rx = desc - sc->rx_desc;
1633 sc->pending_rxs--;
1634
1635 return (1);
1636 }
1637
1638 /* This gets called by NVIDIA API when the PHY link state changes */
1639 static NV_API_CALL NV_SINT32
nve_oslinkchg(PNV_VOID ctx,NV_SINT32 enabled)1640 nve_oslinkchg(PNV_VOID ctx, NV_SINT32 enabled)
1641 {
1642
1643 DEBUGOUT(NVE_DEBUG_API, "nve: nve_oslinkchg\n");
1644
1645 return (1);
1646 }
1647
1648 /* Setup a watchdog timer */
1649 static NV_API_CALL NV_SINT32
nve_osalloctimer(PNV_VOID ctx,PNV_VOID * timer)1650 nve_osalloctimer(PNV_VOID ctx, PNV_VOID *timer)
1651 {
1652 struct nve_softc *sc = (struct nve_softc *)ctx;
1653
1654 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osalloctimer\n");
1655
1656 callout_init(&sc->ostimer, CALLOUT_MPSAFE);
1657 *timer = &sc->ostimer;
1658
1659 return (1);
1660 }
1661
1662 /* Free the timer */
1663 static NV_API_CALL NV_SINT32
nve_osfreetimer(PNV_VOID ctx,PNV_VOID timer)1664 nve_osfreetimer(PNV_VOID ctx, PNV_VOID timer)
1665 {
1666
1667 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osfreetimer\n");
1668
1669 callout_drain((struct callout *)timer);
1670
1671 return (1);
1672 }
1673
1674 /* Setup timer parameters */
1675 static NV_API_CALL NV_SINT32
nve_osinittimer(PNV_VOID ctx,PNV_VOID timer,PTIMER_FUNC func,PNV_VOID parameters)1676 nve_osinittimer(PNV_VOID ctx, PNV_VOID timer, PTIMER_FUNC func, PNV_VOID parameters)
1677 {
1678 struct nve_softc *sc = (struct nve_softc *)ctx;
1679
1680 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osinittimer\n");
1681
1682 sc->ostimer_func = func;
1683 sc->ostimer_params = parameters;
1684
1685 return (1);
1686 }
1687
1688 /* Set the timer to go off */
1689 static NV_API_CALL NV_SINT32
nve_ossettimer(PNV_VOID ctx,PNV_VOID timer,NV_UINT32 delay)1690 nve_ossettimer(PNV_VOID ctx, PNV_VOID timer, NV_UINT32 delay)
1691 {
1692 struct nve_softc *sc = ctx;
1693
1694 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ossettimer\n");
1695
1696 callout_reset((struct callout *)timer, delay, sc->ostimer_func,
1697 sc->ostimer_params);
1698
1699 return (1);
1700 }
1701
1702 /* Cancel the timer */
1703 static NV_API_CALL NV_SINT32
nve_oscanceltimer(PNV_VOID ctx,PNV_VOID timer)1704 nve_oscanceltimer(PNV_VOID ctx, PNV_VOID timer)
1705 {
1706
1707 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_oscanceltimer\n");
1708
1709 callout_stop((struct callout *)timer);
1710
1711 return (1);
1712 }
1713
1714 static NV_API_CALL NV_SINT32
nve_ospreprocpkt(PNV_VOID ctx,PNV_VOID readdata,PNV_VOID * id,NV_UINT8 * newbuffer,NV_UINT8 priority)1715 nve_ospreprocpkt(PNV_VOID ctx, PNV_VOID readdata, PNV_VOID *id,
1716 NV_UINT8 *newbuffer, NV_UINT8 priority)
1717 {
1718
1719 /* Not implemented */
1720 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ospreprocpkt\n");
1721
1722 return (1);
1723 }
1724
1725 static NV_API_CALL PNV_VOID
nve_ospreprocpktnopq(PNV_VOID ctx,PNV_VOID readdata)1726 nve_ospreprocpktnopq(PNV_VOID ctx, PNV_VOID readdata)
1727 {
1728
1729 /* Not implemented */
1730 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ospreprocpkt\n");
1731
1732 return (NULL);
1733 }
1734
1735 static NV_API_CALL NV_SINT32
nve_osindicatepkt(PNV_VOID ctx,PNV_VOID * id,NV_UINT32 pktno)1736 nve_osindicatepkt(PNV_VOID ctx, PNV_VOID *id, NV_UINT32 pktno)
1737 {
1738
1739 /* Not implemented */
1740 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osindicatepkt\n");
1741
1742 return (1);
1743 }
1744
1745 /* Allocate mutex context (already done in nve_attach) */
1746 static NV_API_CALL NV_SINT32
nve_oslockalloc(PNV_VOID ctx,NV_SINT32 type,PNV_VOID * pLock)1747 nve_oslockalloc(PNV_VOID ctx, NV_SINT32 type, PNV_VOID *pLock)
1748 {
1749 struct nve_softc *sc = (struct nve_softc *)ctx;
1750
1751 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockalloc\n");
1752
1753 *pLock = (void **)sc;
1754
1755 return (1);
1756 }
1757
1758 /* Obtain a spin lock */
1759 static NV_API_CALL NV_SINT32
nve_oslockacquire(PNV_VOID ctx,NV_SINT32 type,PNV_VOID lock)1760 nve_oslockacquire(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
1761 {
1762
1763 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockacquire\n");
1764
1765 return (1);
1766 }
1767
1768 /* Release lock */
1769 static NV_API_CALL NV_SINT32
nve_oslockrelease(PNV_VOID ctx,NV_SINT32 type,PNV_VOID lock)1770 nve_oslockrelease(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
1771 {
1772
1773 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockrelease\n");
1774
1775 return (1);
1776 }
1777
1778 /* I have no idea what this is for */
1779 static NV_API_CALL PNV_VOID
nve_osreturnbufvirt(PNV_VOID ctx,PNV_VOID readdata)1780 nve_osreturnbufvirt(PNV_VOID ctx, PNV_VOID readdata)
1781 {
1782
1783 /* Not implemented */
1784 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_osreturnbufvirt\n");
1785 panic("nve: nve_osreturnbufvirtual not implemented\n");
1786
1787 return (NULL);
1788 }
1789
1790 /* --- End on NVOSAPI interface --- */
1791