1 /*-
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/10/sys/dev/mlx5/mlx5_core/mlx5_eq.c 339713 2018-10-25 14:12:48Z slavash $
26 */
27
28 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <dev/mlx5/driver.h>
31 #include <dev/mlx5/mlx5_ifc.h>
32 #include "mlx5_core.h"
33
34 #if (__FreeBSD_version >= 1100000)
35 #include "opt_rss.h"
36 #endif
37
38 #ifdef RSS
39 #include <net/rss_config.h>
40 #include <netinet/in_rss.h>
41 #endif
42
43 enum {
44 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
45 MLX5_EQE_OWNER_INIT_VAL = 0x1,
46 };
47
48 enum {
49 MLX5_NUM_SPARE_EQE = 0x80,
50 MLX5_NUM_ASYNC_EQE = 0x100,
51 MLX5_NUM_CMD_EQE = 32,
52 };
53
54 enum {
55 MLX5_EQ_DOORBEL_OFFSET = 0x40,
56 };
57
58 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
59 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
60 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
61 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
62 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
63 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
64 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
65 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
66 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
67 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
68 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
69 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
70
71 struct map_eq_in {
72 u64 mask;
73 u32 reserved;
74 u32 unmap_eqn;
75 };
76
77 struct cre_des_eq {
78 u8 reserved[15];
79 u8 eqn;
80 };
81
82 /*Function prototype*/
83 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
84 struct mlx5_eqe *eqe);
85
mlx5_cmd_destroy_eq(struct mlx5_core_dev * dev,u8 eqn)86 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
87 {
88 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)];
89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)];
90
91 memset(in, 0, sizeof(in));
92
93 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
94 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
95
96 memset(out, 0, sizeof(out));
97 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
98 out, sizeof(out));
99 }
100
get_eqe(struct mlx5_eq * eq,u32 entry)101 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
102 {
103 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
104 }
105
next_eqe_sw(struct mlx5_eq * eq)106 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
107 {
108 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
109
110 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
111 }
112
eqe_type_str(u8 type)113 static const char *eqe_type_str(u8 type)
114 {
115 switch (type) {
116 case MLX5_EVENT_TYPE_COMP:
117 return "MLX5_EVENT_TYPE_COMP";
118 case MLX5_EVENT_TYPE_PATH_MIG:
119 return "MLX5_EVENT_TYPE_PATH_MIG";
120 case MLX5_EVENT_TYPE_COMM_EST:
121 return "MLX5_EVENT_TYPE_COMM_EST";
122 case MLX5_EVENT_TYPE_SQ_DRAINED:
123 return "MLX5_EVENT_TYPE_SQ_DRAINED";
124 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
125 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
126 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
127 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
128 case MLX5_EVENT_TYPE_CQ_ERROR:
129 return "MLX5_EVENT_TYPE_CQ_ERROR";
130 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
131 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
132 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
133 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
134 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
135 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
136 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
137 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
138 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
139 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
140 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
141 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
142 case MLX5_EVENT_TYPE_PORT_CHANGE:
143 return "MLX5_EVENT_TYPE_PORT_CHANGE";
144 case MLX5_EVENT_TYPE_GPIO_EVENT:
145 return "MLX5_EVENT_TYPE_GPIO_EVENT";
146 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
147 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
148 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
149 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
150 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
151 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
152 case MLX5_EVENT_TYPE_STALL_EVENT:
153 return "MLX5_EVENT_TYPE_STALL_EVENT";
154 case MLX5_EVENT_TYPE_CMD:
155 return "MLX5_EVENT_TYPE_CMD";
156 case MLX5_EVENT_TYPE_PAGE_REQUEST:
157 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
158 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
159 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
160 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
161 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT";
162 default:
163 return "Unrecognized event";
164 }
165 }
166
port_subtype_event(u8 subtype)167 static enum mlx5_dev_event port_subtype_event(u8 subtype)
168 {
169 switch (subtype) {
170 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
171 return MLX5_DEV_EVENT_PORT_DOWN;
172 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
173 return MLX5_DEV_EVENT_PORT_UP;
174 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
175 return MLX5_DEV_EVENT_PORT_INITIALIZED;
176 case MLX5_PORT_CHANGE_SUBTYPE_LID:
177 return MLX5_DEV_EVENT_LID_CHANGE;
178 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
179 return MLX5_DEV_EVENT_PKEY_CHANGE;
180 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
181 return MLX5_DEV_EVENT_GUID_CHANGE;
182 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
183 return MLX5_DEV_EVENT_CLIENT_REREG;
184 }
185 return -1;
186 }
187
dcbx_subevent(u8 subtype)188 static enum mlx5_dev_event dcbx_subevent(u8 subtype)
189 {
190 switch (subtype) {
191 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
192 return MLX5_DEV_EVENT_ERROR_STATE_DCBX;
193 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
194 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE;
195 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
196 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE;
197 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
198 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE;
199 }
200 return -1;
201 }
202
eq_update_ci(struct mlx5_eq * eq,int arm)203 static void eq_update_ci(struct mlx5_eq *eq, int arm)
204 {
205 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
206 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
207 __raw_writel((__force u32) cpu_to_be32(val), addr);
208 /* We still want ordering, just not swabbing, so add a barrier */
209 mb();
210 }
211
mlx5_eq_int(struct mlx5_core_dev * dev,struct mlx5_eq * eq)212 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
213 {
214 struct mlx5_eqe *eqe;
215 int eqes_found = 0;
216 int set_ci = 0;
217 u32 cqn;
218 u32 rsn;
219 u8 port;
220
221 while ((eqe = next_eqe_sw(eq))) {
222 /*
223 * Make sure we read EQ entry contents after we've
224 * checked the ownership bit.
225 */
226 rmb();
227
228 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
229 eq->eqn, eqe_type_str(eqe->type));
230 switch (eqe->type) {
231 case MLX5_EVENT_TYPE_COMP:
232 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
233 mlx5_cq_completion(dev, cqn);
234 break;
235
236 case MLX5_EVENT_TYPE_PATH_MIG:
237 case MLX5_EVENT_TYPE_COMM_EST:
238 case MLX5_EVENT_TYPE_SQ_DRAINED:
239 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
240 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
241 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
242 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
243 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
244 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
245 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
246 eqe_type_str(eqe->type), eqe->type, rsn);
247 mlx5_rsc_event(dev, rsn, eqe->type);
248 break;
249
250 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
251 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
252 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
253 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
254 eqe_type_str(eqe->type), eqe->type, rsn);
255 mlx5_srq_event(dev, rsn, eqe->type);
256 break;
257
258 case MLX5_EVENT_TYPE_CMD:
259 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
260 break;
261
262 case MLX5_EVENT_TYPE_PORT_CHANGE:
263 port = (eqe->data.port.port >> 4) & 0xf;
264 switch (eqe->sub_type) {
265 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
266 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
267 case MLX5_PORT_CHANGE_SUBTYPE_LID:
268 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
269 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
270 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
271 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
272 if (dev->event)
273 dev->event(dev, port_subtype_event(eqe->sub_type),
274 (unsigned long)port);
275 break;
276 default:
277 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
278 port, eqe->sub_type);
279 }
280 break;
281
282 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
283 port = (eqe->data.port.port >> 4) & 0xf;
284 switch (eqe->sub_type) {
285 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
286 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
287 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
288 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
289 if (dev->event)
290 dev->event(dev,
291 dcbx_subevent(eqe->sub_type),
292 0);
293 break;
294 default:
295 mlx5_core_warn(dev,
296 "dcbx event with unrecognized subtype: port %d, sub_type %d\n",
297 port, eqe->sub_type);
298 }
299 break;
300
301 case MLX5_EVENT_TYPE_CQ_ERROR:
302 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
303 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
304 cqn, eqe->data.cq_err.syndrome);
305 mlx5_cq_event(dev, cqn, eqe->type);
306 break;
307
308 case MLX5_EVENT_TYPE_PAGE_REQUEST:
309 {
310 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
311 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
312
313 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
314 func_id, npages);
315 mlx5_core_req_pages_handler(dev, func_id, npages);
316 }
317 break;
318
319 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
320 mlx5_port_module_event(dev, eqe);
321 break;
322
323 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
324 {
325 struct mlx5_eqe_vport_change *vc_eqe =
326 &eqe->data.vport_change;
327 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
328
329 if (dev->event)
330 dev->event(dev,
331 MLX5_DEV_EVENT_VPORT_CHANGE,
332 (unsigned long)vport_num);
333 }
334 break;
335
336 default:
337 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
338 eqe->type, eq->eqn);
339 break;
340 }
341
342 ++eq->cons_index;
343 eqes_found = 1;
344 ++set_ci;
345
346 /* The HCA will think the queue has overflowed if we
347 * don't tell it we've been processing events. We
348 * create our EQs with MLX5_NUM_SPARE_EQE extra
349 * entries, so we must update our consumer index at
350 * least that often.
351 */
352 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
353 eq_update_ci(eq, 0);
354 set_ci = 0;
355 }
356 }
357
358 eq_update_ci(eq, 1);
359
360 return eqes_found;
361 }
362
mlx5_msix_handler(int irq,void * eq_ptr)363 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
364 {
365 struct mlx5_eq *eq = eq_ptr;
366 struct mlx5_core_dev *dev = eq->dev;
367
368 mlx5_eq_int(dev, eq);
369
370 /* MSI-X vectors always belong to us */
371 return IRQ_HANDLED;
372 }
373
init_eq_buf(struct mlx5_eq * eq)374 static void init_eq_buf(struct mlx5_eq *eq)
375 {
376 struct mlx5_eqe *eqe;
377 int i;
378
379 for (i = 0; i < eq->nent; i++) {
380 eqe = get_eqe(eq, i);
381 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
382 }
383 }
384
mlx5_create_map_eq(struct mlx5_core_dev * dev,struct mlx5_eq * eq,u8 vecidx,int nent,u64 mask,const char * name,struct mlx5_uar * uar)385 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
386 int nent, u64 mask, const char *name, struct mlx5_uar *uar)
387 {
388 struct mlx5_priv *priv = &dev->priv;
389 struct mlx5_create_eq_mbox_in *in;
390 struct mlx5_create_eq_mbox_out out;
391 int err;
392 int inlen;
393
394 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
395 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE,
396 &eq->buf);
397 if (err)
398 return err;
399
400 init_eq_buf(eq);
401
402 inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages;
403 in = mlx5_vzalloc(inlen);
404 if (!in) {
405 err = -ENOMEM;
406 goto err_buf;
407 }
408 memset(&out, 0, sizeof(out));
409
410 mlx5_fill_page_array(&eq->buf, in->pas);
411
412 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ);
413 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index);
414 in->ctx.intr = vecidx;
415 in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
416 in->events_mask = cpu_to_be64(mask);
417
418 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
419 if (err)
420 goto err_in;
421
422 if (out.hdr.status) {
423 err = mlx5_cmd_status_to_err(&out.hdr);
424 goto err_in;
425 }
426
427 eq->eqn = out.eq_number;
428 eq->irqn = vecidx;
429 eq->dev = dev;
430 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
431 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
432 name, pci_name(dev->pdev));
433 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
434 priv->irq_info[vecidx].name, eq);
435 if (err)
436 goto err_eq;
437 #ifdef RSS
438 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) {
439 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE;
440 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector,
441 rss_getcpu(bucket % rss_getnumbuckets()));
442 if (err)
443 goto err_irq;
444 }
445 #else
446 if (0)
447 goto err_irq;
448 #endif
449
450
451 /* EQs are created in ARMED state
452 */
453 eq_update_ci(eq, 1);
454
455 kvfree(in);
456 return 0;
457
458 err_irq:
459 free_irq(priv->msix_arr[vecidx].vector, eq);
460
461 err_eq:
462 mlx5_cmd_destroy_eq(dev, eq->eqn);
463
464 err_in:
465 kvfree(in);
466
467 err_buf:
468 mlx5_buf_free(dev, &eq->buf);
469 return err;
470 }
471 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
472
mlx5_destroy_unmap_eq(struct mlx5_core_dev * dev,struct mlx5_eq * eq)473 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
474 {
475 int err;
476
477 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq);
478 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
479 if (err)
480 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
481 eq->eqn);
482 mlx5_buf_free(dev, &eq->buf);
483
484 return err;
485 }
486 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
487
mlx5_eq_init(struct mlx5_core_dev * dev)488 int mlx5_eq_init(struct mlx5_core_dev *dev)
489 {
490 int err;
491
492 spin_lock_init(&dev->priv.eq_table.lock);
493
494 err = 0;
495
496 return err;
497 }
498
499
mlx5_eq_cleanup(struct mlx5_core_dev * dev)500 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
501 {
502 }
503
mlx5_start_eqs(struct mlx5_core_dev * dev)504 int mlx5_start_eqs(struct mlx5_core_dev *dev)
505 {
506 struct mlx5_eq_table *table = &dev->priv.eq_table;
507 u32 async_event_mask = MLX5_ASYNC_EVENT_MASK;
508 int err;
509
510 if (MLX5_CAP_GEN(dev, port_module_event))
511 async_event_mask |= (1ull <<
512 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT);
513
514 if (MLX5_CAP_GEN(dev, nic_vport_change_event))
515 async_event_mask |= (1ull <<
516 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
517
518 if (MLX5_CAP_GEN(dev, dcbx))
519 async_event_mask |= (1ull <<
520 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT);
521
522 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
523 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
524 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
525 if (err) {
526 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
527 return err;
528 }
529
530 mlx5_cmd_use_events(dev);
531
532 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
533 MLX5_NUM_ASYNC_EQE, async_event_mask,
534 "mlx5_async_eq", &dev->priv.uuari.uars[0]);
535 if (err) {
536 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
537 goto err1;
538 }
539
540 err = mlx5_create_map_eq(dev, &table->pages_eq,
541 MLX5_EQ_VEC_PAGES,
542 /* TODO: sriov max_vf + */ 1,
543 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
544 &dev->priv.uuari.uars[0]);
545 if (err) {
546 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
547 goto err2;
548 }
549
550 return err;
551
552 err2:
553 mlx5_destroy_unmap_eq(dev, &table->async_eq);
554
555 err1:
556 mlx5_cmd_use_polling(dev);
557 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
558 return err;
559 }
560
mlx5_stop_eqs(struct mlx5_core_dev * dev)561 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
562 {
563 struct mlx5_eq_table *table = &dev->priv.eq_table;
564 int err;
565
566 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
567 if (err)
568 return err;
569
570 mlx5_destroy_unmap_eq(dev, &table->async_eq);
571 mlx5_cmd_use_polling(dev);
572
573 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
574 if (err)
575 mlx5_cmd_use_events(dev);
576
577 return err;
578 }
579
mlx5_core_eq_query(struct mlx5_core_dev * dev,struct mlx5_eq * eq,struct mlx5_query_eq_mbox_out * out,int outlen)580 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
581 struct mlx5_query_eq_mbox_out *out, int outlen)
582 {
583 struct mlx5_query_eq_mbox_in in;
584 int err;
585
586 memset(&in, 0, sizeof(in));
587 memset(out, 0, outlen);
588 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ);
589 in.eqn = eq->eqn;
590 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
591 if (err)
592 return err;
593
594 if (out->hdr.status)
595 err = mlx5_cmd_status_to_err(&out->hdr);
596
597 return err;
598 }
599
600 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
601
mlx5_port_module_event_error_type_to_string(u8 error_type)602 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type)
603 {
604 switch (error_type) {
605 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED:
606 return "Power Budget Exceeded";
607 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE:
608 return "Long Range for non MLNX cable/module";
609 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK:
610 return "Bus stuck(I2C or data shorted)";
611 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT:
612 return "No EEPROM/retry timeout";
613 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST:
614 return "Enforce part number list";
615 case MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER:
616 return "Unknown identifier";
617 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE:
618 return "High Temperature";
619 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED:
620 return "Cable is shorted";
621 case MLX5_MODULE_EVENT_ERROR_PCIE_SYSTEM_POWER_SLOT_EXCEEDED:
622 return "One or more network ports have been powered "
623 "down due to insufficient/unadvertised power on "
624 "the PCIe slot. Please refer to the card's user "
625 "manual for power specifications or contact "
626 "Mellanox support.";
627
628 default:
629 return "Unknown error type";
630 }
631 }
632
mlx5_query_module_status(struct mlx5_core_dev * dev,int module_num)633 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num)
634 {
635 if (module_num < 0 || module_num >= MLX5_MAX_PORTS)
636 return 0; /* undefined */
637 return dev->module_status[module_num];
638 }
639
mlx5_port_module_event(struct mlx5_core_dev * dev,struct mlx5_eqe * eqe)640 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
641 struct mlx5_eqe *eqe)
642 {
643 unsigned int module_num;
644 unsigned int module_status;
645 unsigned int error_type;
646 struct mlx5_eqe_port_module_event *module_event_eqe;
647 struct pci_dev *pdev = dev->pdev;
648
649 module_event_eqe = &eqe->data.port_module_event;
650
651 module_num = (unsigned int)module_event_eqe->module;
652 module_status = (unsigned int)module_event_eqe->module_status &
653 PORT_MODULE_EVENT_MODULE_STATUS_MASK;
654 error_type = (unsigned int)module_event_eqe->error_type &
655 PORT_MODULE_EVENT_ERROR_TYPE_MASK;
656
657 switch (module_status) {
658 case MLX5_MODULE_STATUS_PLUGGED:
659 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged\n", module_num);
660 break;
661
662 case MLX5_MODULE_STATUS_UNPLUGGED:
663 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged\n", module_num);
664 break;
665
666 case MLX5_MODULE_STATUS_ERROR:
667 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s\n", module_num, mlx5_port_module_event_error_type_to_string(error_type));
668 break;
669
670 default:
671 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status\n", module_num);
672 }
673 /* store module status */
674 if (module_num < MLX5_MAX_PORTS)
675 dev->module_status[module_num] = module_status;
676 }
677
678