1 /*-
2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: stable/10/sys/dev/ffec/if_ffec.c 276285 2014-12-27 04:35:18Z ian $");
30
31 /*
32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among
33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28,
34 * but the driver doesn't currently use any of the ENET advanced features other
35 * than enabling gigabit.
36 *
37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel
38 * (netgraph/ng_fec.c), so we use 'ffec'.
39 *
40 * Requires an FDT entry with at least these properties:
41 * fec: ethernet@02188000 {
42 * compatible = "fsl,imxNN-fec";
43 * reg = <0x02188000 0x4000>;
44 * interrupts = <150 151>;
45 * phy-mode = "rgmii";
46 * phy-disable-preamble; // optional
47 * };
48 * The second interrupt number is for IEEE-1588, and is not currently used; it
49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii".
50 * There is also an optional property, phy-disable-preamble, which if present
51 * will disable the preamble bits, cutting the size of each mdio transaction
52 * (and thus the busy-wait time) in half.
53 */
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/bus.h>
58 #include <sys/endian.h>
59 #include <sys/kernel.h>
60 #include <sys/lock.h>
61 #include <sys/malloc.h>
62 #include <sys/mbuf.h>
63 #include <sys/module.h>
64 #include <sys/mutex.h>
65 #include <sys/rman.h>
66 #include <sys/socket.h>
67 #include <sys/sockio.h>
68 #include <sys/sysctl.h>
69
70 #include <machine/bus.h>
71
72 #include <net/bpf.h>
73 #include <net/if.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/if_var.h>
79 #include <net/if_vlan_var.h>
80
81 #include <dev/ffec/if_ffecreg.h>
82 #include <dev/ofw/ofw_bus.h>
83 #include <dev/ofw/ofw_bus_subr.h>
84 #include <dev/mii/mii.h>
85 #include <dev/mii/miivar.h>
86 #include "miibus_if.h"
87
88 /*
89 * There are small differences in the hardware on various SoCs. Not every SoC
90 * we support has its own FECTYPE; most work as GENERIC and only the ones that
91 * need different handling get their own entry. In addition to the types in
92 * this list, there are some flags below that can be ORed into the upper bits.
93 */
94 enum {
95 FECTYPE_NONE,
96 FECTYPE_GENERIC,
97 FECTYPE_IMX53,
98 FECTYPE_IMX6,
99 };
100
101 /*
102 * Flags that describe general differences between the FEC hardware in various
103 * SoCs. These are ORed into the FECTYPE enum values.
104 */
105 #define FECTYPE_MASK 0x0000ffff
106 #define FECFLAG_GBE (0x0001 << 16)
107
108 /*
109 * Table of supported FDT compat strings and their associated FECTYPE values.
110 */
111 static struct ofw_compat_data compat_data[] = {
112 {"fsl,imx51-fec", FECTYPE_GENERIC},
113 {"fsl,imx53-fec", FECTYPE_IMX53},
114 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_GBE},
115 {"fsl,mvf600-fec", FECTYPE_GENERIC},
116 {"fsl,vf-fec", FECTYPE_GENERIC},
117 {NULL, FECTYPE_NONE},
118 };
119
120 /*
121 * Driver data and defines.
122 */
123 #define RX_DESC_COUNT 64
124 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT)
125 #define TX_DESC_COUNT 64
126 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT)
127
128 #define WATCHDOG_TIMEOUT_SECS 5
129 #define STATS_HARVEST_INTERVAL 3
130
131 struct ffec_bufmap {
132 struct mbuf *mbuf;
133 bus_dmamap_t map;
134 };
135
136 enum {
137 PHY_CONN_UNKNOWN,
138 PHY_CONN_MII,
139 PHY_CONN_RMII,
140 PHY_CONN_RGMII
141 };
142
143 struct ffec_softc {
144 device_t dev;
145 device_t miibus;
146 struct mii_data * mii_softc;
147 struct ifnet *ifp;
148 int if_flags;
149 struct mtx mtx;
150 struct resource *irq_res;
151 struct resource *mem_res;
152 void * intr_cookie;
153 struct callout ffec_callout;
154 uint8_t phy_conn_type;
155 uint8_t fectype;
156 boolean_t link_is_up;
157 boolean_t is_attached;
158 boolean_t is_detaching;
159 int tx_watchdog_count;
160 int stats_harvest_count;
161
162 bus_dma_tag_t rxdesc_tag;
163 bus_dmamap_t rxdesc_map;
164 struct ffec_hwdesc *rxdesc_ring;
165 bus_addr_t rxdesc_ring_paddr;
166 bus_dma_tag_t rxbuf_tag;
167 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT];
168 uint32_t rx_idx;
169
170 bus_dma_tag_t txdesc_tag;
171 bus_dmamap_t txdesc_map;
172 struct ffec_hwdesc *txdesc_ring;
173 bus_addr_t txdesc_ring_paddr;
174 bus_dma_tag_t txbuf_tag;
175 struct ffec_bufmap txbuf_map[RX_DESC_COUNT];
176 uint32_t tx_idx_head;
177 uint32_t tx_idx_tail;
178 int txcount;
179 };
180
181 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx)
182 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
183 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \
184 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF)
185 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
186 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
187 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
188
189 static void ffec_init_locked(struct ffec_softc *sc);
190 static void ffec_stop_locked(struct ffec_softc *sc);
191 static void ffec_txstart_locked(struct ffec_softc *sc);
192 static void ffec_txfinish_locked(struct ffec_softc *sc);
193
194 static inline uint16_t
RD2(struct ffec_softc * sc,bus_size_t off)195 RD2(struct ffec_softc *sc, bus_size_t off)
196 {
197
198 return (bus_read_2(sc->mem_res, off));
199 }
200
201 static inline void
WR2(struct ffec_softc * sc,bus_size_t off,uint16_t val)202 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val)
203 {
204
205 bus_write_2(sc->mem_res, off, val);
206 }
207
208 static inline uint32_t
RD4(struct ffec_softc * sc,bus_size_t off)209 RD4(struct ffec_softc *sc, bus_size_t off)
210 {
211
212 return (bus_read_4(sc->mem_res, off));
213 }
214
215 static inline void
WR4(struct ffec_softc * sc,bus_size_t off,uint32_t val)216 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
217 {
218
219 bus_write_4(sc->mem_res, off, val);
220 }
221
222 static inline uint32_t
next_rxidx(struct ffec_softc * sc,uint32_t curidx)223 next_rxidx(struct ffec_softc *sc, uint32_t curidx)
224 {
225
226 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1);
227 }
228
229 static inline uint32_t
next_txidx(struct ffec_softc * sc,uint32_t curidx)230 next_txidx(struct ffec_softc *sc, uint32_t curidx)
231 {
232
233 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1);
234 }
235
236 static void
ffec_get1paddr(void * arg,bus_dma_segment_t * segs,int nsegs,int error)237 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
238 {
239
240 if (error != 0)
241 return;
242 *(bus_addr_t *)arg = segs[0].ds_addr;
243 }
244
245 static void
ffec_miigasket_setup(struct ffec_softc * sc)246 ffec_miigasket_setup(struct ffec_softc *sc)
247 {
248 uint32_t ifmode;
249
250 /*
251 * We only need the gasket for MII and RMII connections on certain SoCs.
252 */
253
254 switch (sc->fectype & FECTYPE_MASK)
255 {
256 case FECTYPE_IMX53:
257 break;
258 default:
259 return;
260 }
261
262 switch (sc->phy_conn_type)
263 {
264 case PHY_CONN_MII:
265 ifmode = 0;
266 break;
267 case PHY_CONN_RMII:
268 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII;
269 break;
270 default:
271 return;
272 }
273
274 /*
275 * Disable the gasket, configure for either MII or RMII, then enable.
276 */
277
278 WR2(sc, FEC_MIIGSK_ENR, 0);
279 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
280 continue;
281
282 WR2(sc, FEC_MIIGSK_CFGR, ifmode);
283
284 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
285 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
286 continue;
287 }
288
289 static boolean_t
ffec_miibus_iowait(struct ffec_softc * sc)290 ffec_miibus_iowait(struct ffec_softc *sc)
291 {
292 uint32_t timeout;
293
294 for (timeout = 10000; timeout != 0; --timeout)
295 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
296 return (true);
297
298 return (false);
299 }
300
301 static int
ffec_miibus_readreg(device_t dev,int phy,int reg)302 ffec_miibus_readreg(device_t dev, int phy, int reg)
303 {
304 struct ffec_softc *sc;
305 int val;
306
307 sc = device_get_softc(dev);
308
309 WR4(sc, FEC_IER_REG, FEC_IER_MII);
310
311 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
312 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
313 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
314 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK));
315
316 if (!ffec_miibus_iowait(sc)) {
317 device_printf(dev, "timeout waiting for mii read\n");
318 return (-1); /* All-ones is a symptom of bad mdio. */
319 }
320
321 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
322
323 return (val);
324 }
325
326 static int
ffec_miibus_writereg(device_t dev,int phy,int reg,int val)327 ffec_miibus_writereg(device_t dev, int phy, int reg, int val)
328 {
329 struct ffec_softc *sc;
330
331 sc = device_get_softc(dev);
332
333 WR4(sc, FEC_IER_REG, FEC_IER_MII);
334
335 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
336 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
337 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
338 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) |
339 (val & FEC_MMFR_DATA_MASK));
340
341 if (!ffec_miibus_iowait(sc)) {
342 device_printf(dev, "timeout waiting for mii write\n");
343 return (-1);
344 }
345
346 return (0);
347 }
348
349 static void
ffec_miibus_statchg(device_t dev)350 ffec_miibus_statchg(device_t dev)
351 {
352 struct ffec_softc *sc;
353 struct mii_data *mii;
354 uint32_t ecr, rcr, tcr;
355
356 /*
357 * Called by the MII bus driver when the PHY establishes link to set the
358 * MAC interface registers.
359 */
360
361 sc = device_get_softc(dev);
362
363 FFEC_ASSERT_LOCKED(sc);
364
365 mii = sc->mii_softc;
366
367 if (mii->mii_media_status & IFM_ACTIVE)
368 sc->link_is_up = true;
369 else
370 sc->link_is_up = false;
371
372 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
373 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
374 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE);
375 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
376
377 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */
378 switch (sc->phy_conn_type) {
379 case PHY_CONN_MII:
380 break;
381 case PHY_CONN_RMII:
382 rcr |= FEC_RCR_RMII_MODE;
383 break;
384 case PHY_CONN_RGMII:
385 rcr |= FEC_RCR_RGMII_EN;
386 break;
387 }
388
389 switch (IFM_SUBTYPE(mii->mii_media_active)) {
390 case IFM_1000_T:
391 case IFM_1000_SX:
392 ecr |= FEC_ECR_SPEED;
393 break;
394 case IFM_100_TX:
395 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */
396 break;
397 case IFM_10_T:
398 rcr |= FEC_RCR_RMII_10T;
399 break;
400 case IFM_NONE:
401 sc->link_is_up = false;
402 return;
403 default:
404 sc->link_is_up = false;
405 device_printf(dev, "Unsupported media %u\n",
406 IFM_SUBTYPE(mii->mii_media_active));
407 return;
408 }
409
410 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
411 tcr |= FEC_TCR_FDEN;
412 else
413 rcr |= FEC_RCR_DRT;
414
415 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0)
416 rcr |= FEC_RCR_FCE;
417
418 WR4(sc, FEC_RCR_REG, rcr);
419 WR4(sc, FEC_TCR_REG, tcr);
420 WR4(sc, FEC_ECR_REG, ecr);
421 }
422
423 static void
ffec_media_status(struct ifnet * ifp,struct ifmediareq * ifmr)424 ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
425 {
426 struct ffec_softc *sc;
427 struct mii_data *mii;
428
429
430 sc = ifp->if_softc;
431 mii = sc->mii_softc;
432 FFEC_LOCK(sc);
433 mii_pollstat(mii);
434 ifmr->ifm_active = mii->mii_media_active;
435 ifmr->ifm_status = mii->mii_media_status;
436 FFEC_UNLOCK(sc);
437 }
438
439 static int
ffec_media_change_locked(struct ffec_softc * sc)440 ffec_media_change_locked(struct ffec_softc *sc)
441 {
442
443 return (mii_mediachg(sc->mii_softc));
444 }
445
446 static int
ffec_media_change(struct ifnet * ifp)447 ffec_media_change(struct ifnet * ifp)
448 {
449 struct ffec_softc *sc;
450 int error;
451
452 sc = ifp->if_softc;
453
454 FFEC_LOCK(sc);
455 error = ffec_media_change_locked(sc);
456 FFEC_UNLOCK(sc);
457 return (error);
458 }
459
ffec_clear_stats(struct ffec_softc * sc)460 static void ffec_clear_stats(struct ffec_softc *sc)
461 {
462
463 WR4(sc, FEC_RMON_R_PACKETS, 0);
464 WR4(sc, FEC_RMON_R_MC_PKT, 0);
465 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
466 WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
467 WR4(sc, FEC_RMON_R_OVERSIZE, 0);
468 WR4(sc, FEC_RMON_R_FRAG, 0);
469 WR4(sc, FEC_RMON_R_JAB, 0);
470 WR4(sc, FEC_RMON_T_PACKETS, 0);
471 WR4(sc, FEC_RMON_T_MC_PKT, 0);
472 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
473 WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
474 WR4(sc, FEC_RMON_T_OVERSIZE , 0);
475 WR4(sc, FEC_RMON_T_FRAG, 0);
476 WR4(sc, FEC_RMON_T_JAB, 0);
477 WR4(sc, FEC_RMON_T_COL, 0);
478 }
479
480 static void
ffec_harvest_stats(struct ffec_softc * sc)481 ffec_harvest_stats(struct ffec_softc *sc)
482 {
483 struct ifnet *ifp;
484
485 /* We don't need to harvest too often. */
486 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
487 return;
488
489 /*
490 * Try to avoid harvesting unless the IDLE flag is on, but if it has
491 * been too long just go ahead and do it anyway, the worst that'll
492 * happen is we'll lose a packet count or two as we clear at the end.
493 */
494 if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) &&
495 ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0))
496 return;
497
498 sc->stats_harvest_count = 0;
499 ifp = sc->ifp;
500
501 ifp->if_ipackets += RD4(sc, FEC_RMON_R_PACKETS);
502 ifp->if_imcasts += RD4(sc, FEC_RMON_R_MC_PKT);
503 ifp->if_ierrors += RD4(sc, FEC_RMON_R_CRC_ALIGN);
504 ifp->if_ierrors += RD4(sc, FEC_RMON_R_UNDERSIZE);
505 ifp->if_ierrors += RD4(sc, FEC_RMON_R_OVERSIZE);
506 ifp->if_ierrors += RD4(sc, FEC_RMON_R_FRAG);
507 ifp->if_ierrors += RD4(sc, FEC_RMON_R_JAB);
508
509 ifp->if_opackets += RD4(sc, FEC_RMON_T_PACKETS);
510 ifp->if_omcasts += RD4(sc, FEC_RMON_T_MC_PKT);
511 ifp->if_oerrors += RD4(sc, FEC_RMON_T_CRC_ALIGN);
512 ifp->if_oerrors += RD4(sc, FEC_RMON_T_UNDERSIZE);
513 ifp->if_oerrors += RD4(sc, FEC_RMON_T_OVERSIZE );
514 ifp->if_oerrors += RD4(sc, FEC_RMON_T_FRAG);
515 ifp->if_oerrors += RD4(sc, FEC_RMON_T_JAB);
516
517 ifp->if_collisions += RD4(sc, FEC_RMON_T_COL);
518
519 ffec_clear_stats(sc);
520 }
521
522 static void
ffec_tick(void * arg)523 ffec_tick(void *arg)
524 {
525 struct ffec_softc *sc;
526 struct ifnet *ifp;
527 int link_was_up;
528
529 sc = arg;
530
531 FFEC_ASSERT_LOCKED(sc);
532
533 ifp = sc->ifp;
534
535 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
536 return;
537
538 /*
539 * Typical tx watchdog. If this fires it indicates that we enqueued
540 * packets for output and never got a txdone interrupt for them. Maybe
541 * it's a missed interrupt somehow, just pretend we got one.
542 */
543 if (sc->tx_watchdog_count > 0) {
544 if (--sc->tx_watchdog_count == 0) {
545 ffec_txfinish_locked(sc);
546 }
547 }
548
549 /* Gather stats from hardware counters. */
550 ffec_harvest_stats(sc);
551
552 /* Check the media status. */
553 link_was_up = sc->link_is_up;
554 mii_tick(sc->mii_softc);
555 if (sc->link_is_up && !link_was_up)
556 ffec_txstart_locked(sc);
557
558 /* Schedule another check one second from now. */
559 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
560 }
561
562 inline static uint32_t
ffec_setup_txdesc(struct ffec_softc * sc,int idx,bus_addr_t paddr,uint32_t len)563 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
564 uint32_t len)
565 {
566 uint32_t nidx;
567 uint32_t flags;
568
569 nidx = next_txidx(sc, idx);
570
571 /* Addr/len 0 means we're clearing the descriptor after xmit done. */
572 if (paddr == 0 || len == 0) {
573 flags = 0;
574 --sc->txcount;
575 } else {
576 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC;
577 ++sc->txcount;
578 }
579 if (nidx == 0)
580 flags |= FEC_TXDESC_WRAP;
581
582 /*
583 * The hardware requires 32-bit physical addresses. We set up the dma
584 * tag to indicate that, so the cast to uint32_t should never lose
585 * significant bits.
586 */
587 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
588 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */
589
590 return (nidx);
591 }
592
593 static int
ffec_setup_txbuf(struct ffec_softc * sc,int idx,struct mbuf ** mp)594 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp)
595 {
596 struct mbuf * m;
597 int error, nsegs;
598 struct bus_dma_segment seg;
599
600 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
601 return (ENOMEM);
602 *mp = m;
603
604 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
605 m, &seg, &nsegs, 0);
606 if (error != 0) {
607 return (ENOMEM);
608 }
609 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
610 BUS_DMASYNC_PREWRITE);
611
612 sc->txbuf_map[idx].mbuf = m;
613 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
614
615 return (0);
616
617 }
618
619 static void
ffec_txstart_locked(struct ffec_softc * sc)620 ffec_txstart_locked(struct ffec_softc *sc)
621 {
622 struct ifnet *ifp;
623 struct mbuf *m;
624 int enqueued;
625
626 FFEC_ASSERT_LOCKED(sc);
627
628 if (!sc->link_is_up)
629 return;
630
631 ifp = sc->ifp;
632
633 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
634 return;
635
636 enqueued = 0;
637
638 for (;;) {
639 if (sc->txcount == (TX_DESC_COUNT-1)) {
640 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
641 break;
642 }
643 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
644 if (m == NULL)
645 break;
646 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
647 IFQ_DRV_PREPEND(&ifp->if_snd, m);
648 break;
649 }
650 BPF_MTAP(ifp, m);
651 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
652 ++enqueued;
653 }
654
655 if (enqueued != 0) {
656 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
657 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
658 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
659 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
660 }
661 }
662
663 static void
ffec_txstart(struct ifnet * ifp)664 ffec_txstart(struct ifnet *ifp)
665 {
666 struct ffec_softc *sc = ifp->if_softc;
667
668 FFEC_LOCK(sc);
669 ffec_txstart_locked(sc);
670 FFEC_UNLOCK(sc);
671 }
672
673 static void
ffec_txfinish_locked(struct ffec_softc * sc)674 ffec_txfinish_locked(struct ffec_softc *sc)
675 {
676 struct ifnet *ifp;
677 struct ffec_hwdesc *desc;
678 struct ffec_bufmap *bmap;
679 boolean_t retired_buffer;
680
681 FFEC_ASSERT_LOCKED(sc);
682
683 /* XXX Can't set PRE|POST right now, but we need both. */
684 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD);
685 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD);
686 ifp = sc->ifp;
687 retired_buffer = false;
688 while (sc->tx_idx_tail != sc->tx_idx_head) {
689 desc = &sc->txdesc_ring[sc->tx_idx_tail];
690 if (desc->flags_len & FEC_TXDESC_READY)
691 break;
692 retired_buffer = true;
693 bmap = &sc->txbuf_map[sc->tx_idx_tail];
694 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
695 BUS_DMASYNC_POSTWRITE);
696 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
697 m_freem(bmap->mbuf);
698 bmap->mbuf = NULL;
699 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
700 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
701 }
702
703 /*
704 * If we retired any buffers, there will be open tx slots available in
705 * the descriptor ring, go try to start some new output.
706 */
707 if (retired_buffer) {
708 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
709 ffec_txstart_locked(sc);
710 }
711
712 /* If there are no buffers outstanding, muzzle the watchdog. */
713 if (sc->tx_idx_tail == sc->tx_idx_head) {
714 sc->tx_watchdog_count = 0;
715 }
716 }
717
718 inline static uint32_t
ffec_setup_rxdesc(struct ffec_softc * sc,int idx,bus_addr_t paddr)719 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
720 {
721 uint32_t nidx;
722
723 /*
724 * The hardware requires 32-bit physical addresses. We set up the dma
725 * tag to indicate that, so the cast to uint32_t should never lose
726 * significant bits.
727 */
728 nidx = next_rxidx(sc, idx);
729 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
730 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
731 ((nidx == 0) ? FEC_RXDESC_WRAP : 0);
732
733 return (nidx);
734 }
735
736 static int
ffec_setup_rxbuf(struct ffec_softc * sc,int idx,struct mbuf * m)737 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m)
738 {
739 int error, nsegs;
740 struct bus_dma_segment seg;
741
742 /*
743 * We need to leave at least ETHER_ALIGN bytes free at the beginning of
744 * the buffer to allow the data to be re-aligned after receiving it (by
745 * copying it backwards ETHER_ALIGN bytes in the same buffer). We also
746 * have to ensure that the beginning of the buffer is aligned to the
747 * hardware's requirements.
748 */
749 m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN));
750
751 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
752 m, &seg, &nsegs, 0);
753 if (error != 0) {
754 return (error);
755 }
756
757 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
758 BUS_DMASYNC_PREREAD);
759
760 sc->rxbuf_map[idx].mbuf = m;
761 ffec_setup_rxdesc(sc, idx, seg.ds_addr);
762
763 return (0);
764 }
765
766 static struct mbuf *
ffec_alloc_mbufcl(struct ffec_softc * sc)767 ffec_alloc_mbufcl(struct ffec_softc *sc)
768 {
769 struct mbuf *m;
770
771 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
772 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
773
774 return (m);
775 }
776
777 static void
ffec_rxfinish_onebuf(struct ffec_softc * sc,int len)778 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
779 {
780 struct mbuf *m, *newmbuf;
781 struct ffec_bufmap *bmap;
782 uint8_t *dst, *src;
783 int error;
784
785 /*
786 * First try to get a new mbuf to plug into this slot in the rx ring.
787 * If that fails, drop the current packet and recycle the current
788 * mbuf, which is still mapped and loaded.
789 */
790 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) {
791 ++sc->ifp->if_iqdrops;
792 ffec_setup_rxdesc(sc, sc->rx_idx,
793 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
794 return;
795 }
796
797 /*
798 * Unfortunately, the protocol headers need to be aligned on a 32-bit
799 * boundary for the upper layers. The hardware requires receive
800 * buffers to be 16-byte aligned. The ethernet header is 14 bytes,
801 * leaving the protocol header unaligned. We used m_adj() after
802 * allocating the buffer to leave empty space at the start of the
803 * buffer, now we'll use the alignment agnostic bcopy() routine to
804 * shuffle all the data backwards 2 bytes and adjust m_data.
805 *
806 * XXX imx6 hardware is able to do this 2-byte alignment by setting the
807 * SHIFT16 bit in the RACC register. Older hardware doesn't have that
808 * feature, but for them could we speed this up by copying just the
809 * protocol headers into their own small mbuf then chaining the cluster
810 * to it? That way we'd only need to copy like 64 bytes or whatever
811 * the biggest header is, instead of the whole 1530ish-byte frame.
812 */
813
814 FFEC_UNLOCK(sc);
815
816 bmap = &sc->rxbuf_map[sc->rx_idx];
817 len -= ETHER_CRC_LEN;
818 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD);
819 bus_dmamap_unload(sc->rxbuf_tag, bmap->map);
820 m = bmap->mbuf;
821 bmap->mbuf = NULL;
822 m->m_len = len;
823 m->m_pkthdr.len = len;
824 m->m_pkthdr.rcvif = sc->ifp;
825
826 src = mtod(m, uint8_t*);
827 dst = src - ETHER_ALIGN;
828 bcopy(src, dst, len);
829 m->m_data = dst;
830 sc->ifp->if_input(sc->ifp, m);
831
832 FFEC_LOCK(sc);
833
834 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) {
835 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error);
836 /* XXX Now what? We've got a hole in the rx ring. */
837 }
838
839 }
840
841 static void
ffec_rxfinish_locked(struct ffec_softc * sc)842 ffec_rxfinish_locked(struct ffec_softc *sc)
843 {
844 struct ffec_hwdesc *desc;
845 int len;
846 boolean_t produced_empty_buffer;
847
848 FFEC_ASSERT_LOCKED(sc);
849
850 /* XXX Can't set PRE|POST right now, but we need both. */
851 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD);
852 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD);
853 produced_empty_buffer = false;
854 for (;;) {
855 desc = &sc->rxdesc_ring[sc->rx_idx];
856 if (desc->flags_len & FEC_RXDESC_EMPTY)
857 break;
858 produced_empty_buffer = true;
859 len = (desc->flags_len & FEC_RXDESC_LEN_MASK);
860 if (len < 64) {
861 /*
862 * Just recycle the descriptor and continue. .
863 */
864 ffec_setup_rxdesc(sc, sc->rx_idx,
865 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
866 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) {
867 /*
868 * The entire frame is not in this buffer. Impossible.
869 * Recycle the descriptor and continue.
870 *
871 * XXX what's the right way to handle this? Probably we
872 * should stop/init the hardware because this should
873 * just really never happen when we have buffers bigger
874 * than the maximum frame size.
875 */
876 device_printf(sc->dev,
877 "fec_rxfinish: received frame without LAST bit set");
878 ffec_setup_rxdesc(sc, sc->rx_idx,
879 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
880 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) {
881 /*
882 * Something went wrong with receiving the frame, we
883 * don't care what (the hardware has counted the error
884 * in the stats registers already), we just reuse the
885 * same mbuf, which is still dma-mapped, by resetting
886 * the rx descriptor.
887 */
888 ffec_setup_rxdesc(sc, sc->rx_idx,
889 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
890 } else {
891 /*
892 * Normal case: a good frame all in one buffer.
893 */
894 ffec_rxfinish_onebuf(sc, len);
895 }
896 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
897 }
898
899 if (produced_empty_buffer) {
900 bus_dmamap_sync(sc->rxdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
901 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
902 bus_dmamap_sync(sc->rxdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
903 }
904 }
905
906 static void
ffec_get_hwaddr(struct ffec_softc * sc,uint8_t * hwaddr)907 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr)
908 {
909 uint32_t palr, paur, rnd;
910
911 /*
912 * Try to recover a MAC address from the running hardware. If there's
913 * something non-zero there, assume the bootloader did the right thing
914 * and just use it.
915 *
916 * Otherwise, set the address to a convenient locally assigned address,
917 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
918 * assigned bit set, and the broadcast/multicast bit clear.
919 */
920 palr = RD4(sc, FEC_PALR_REG);
921 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
922 if ((palr | paur) != 0) {
923 hwaddr[0] = palr >> 24;
924 hwaddr[1] = palr >> 16;
925 hwaddr[2] = palr >> 8;
926 hwaddr[3] = palr >> 0;
927 hwaddr[4] = paur >> 24;
928 hwaddr[5] = paur >> 16;
929 } else {
930 rnd = arc4random() & 0x00ffffff;
931 hwaddr[0] = 'b';
932 hwaddr[1] = 's';
933 hwaddr[2] = 'd';
934 hwaddr[3] = rnd >> 16;
935 hwaddr[4] = rnd >> 8;
936 hwaddr[5] = rnd >> 0;
937 }
938
939 if (bootverbose) {
940 device_printf(sc->dev,
941 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n",
942 hwaddr[0], hwaddr[1], hwaddr[2],
943 hwaddr[3], hwaddr[4], hwaddr[5]);
944 }
945 }
946
947 static void
ffec_setup_rxfilter(struct ffec_softc * sc)948 ffec_setup_rxfilter(struct ffec_softc *sc)
949 {
950 struct ifnet *ifp;
951 struct ifmultiaddr *ifma;
952 uint8_t *eaddr;
953 uint32_t crc;
954 uint64_t ghash, ihash;
955
956 FFEC_ASSERT_LOCKED(sc);
957
958 ifp = sc->ifp;
959
960 /*
961 * Set the multicast (group) filter hash.
962 */
963 if ((ifp->if_flags & IFF_ALLMULTI))
964 ghash = 0xffffffffffffffffLLU;
965 else {
966 ghash = 0;
967 if_maddr_rlock(ifp);
968 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
969 if (ifma->ifma_addr->sa_family != AF_LINK)
970 continue;
971 /* 6 bits from MSB in LE CRC32 are used for hash. */
972 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
973 ifma->ifma_addr), ETHER_ADDR_LEN);
974 ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2);
975 }
976 if_maddr_runlock(ifp);
977 }
978 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
979 WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
980
981 /*
982 * Set the individual address filter hash.
983 *
984 * XXX Is 0 the right value when promiscuous is off? This hw feature
985 * seems to support the concept of MAC address aliases, does such a
986 * thing even exist?
987 */
988 if ((ifp->if_flags & IFF_PROMISC))
989 ihash = 0xffffffffffffffffLLU;
990 else {
991 ihash = 0;
992 }
993 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
994 WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
995
996 /*
997 * Set the primary address.
998 */
999 eaddr = IF_LLADDR(ifp);
1000 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |
1001 (eaddr[2] << 8) | eaddr[3]);
1002 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));
1003 }
1004
1005 static void
ffec_stop_locked(struct ffec_softc * sc)1006 ffec_stop_locked(struct ffec_softc *sc)
1007 {
1008 struct ifnet *ifp;
1009 struct ffec_hwdesc *desc;
1010 struct ffec_bufmap *bmap;
1011 int idx;
1012
1013 FFEC_ASSERT_LOCKED(sc);
1014
1015 ifp = sc->ifp;
1016 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1017 sc->tx_watchdog_count = 0;
1018 sc->stats_harvest_count = 0;
1019
1020 /*
1021 * Stop the hardware, mask all interrupts, and clear all current
1022 * interrupt status bits.
1023 */
1024 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
1025 WR4(sc, FEC_IEM_REG, 0x00000000);
1026 WR4(sc, FEC_IER_REG, 0xffffffff);
1027
1028 /*
1029 * Stop the media-check callout. Do not use callout_drain() because
1030 * we're holding a mutex the callout acquires, and if it's currently
1031 * waiting to acquire it, we'd deadlock. If it is waiting now, the
1032 * ffec_tick() routine will return without doing anything when it sees
1033 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe.
1034 */
1035 callout_stop(&sc->ffec_callout);
1036
1037 /*
1038 * Discard all untransmitted buffers. Each buffer is simply freed;
1039 * it's as if the bits were transmitted and then lost on the wire.
1040 *
1041 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them
1042 * back on the queue for when we get restarted later?
1043 */
1044 idx = sc->tx_idx_tail;
1045 while (idx != sc->tx_idx_head) {
1046 desc = &sc->txdesc_ring[idx];
1047 bmap = &sc->txbuf_map[idx];
1048 if (desc->buf_paddr != 0) {
1049 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1050 m_freem(bmap->mbuf);
1051 bmap->mbuf = NULL;
1052 ffec_setup_txdesc(sc, idx, 0, 0);
1053 }
1054 idx = next_txidx(sc, idx);
1055 }
1056
1057 /*
1058 * Discard all unprocessed receive buffers. This amounts to just
1059 * pretending that nothing ever got received into them. We reuse the
1060 * mbuf already mapped for each desc, simply turning the EMPTY flags
1061 * back on so they'll get reused when we start up again.
1062 */
1063 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1064 desc = &sc->rxdesc_ring[idx];
1065 ffec_setup_rxdesc(sc, idx, desc->buf_paddr);
1066 }
1067 }
1068
1069 static void
ffec_init_locked(struct ffec_softc * sc)1070 ffec_init_locked(struct ffec_softc *sc)
1071 {
1072 struct ifnet *ifp = sc->ifp;
1073 uint32_t maxbuf, maxfl, regval;
1074
1075 FFEC_ASSERT_LOCKED(sc);
1076
1077 /*
1078 * The hardware has a limit of 0x7ff as the max frame length (see
1079 * comments for MRBR below), and we use mbuf clusters as receive
1080 * buffers, and we currently are designed to receive an entire frame
1081 * into a single buffer.
1082 *
1083 * We start with a MCLBYTES-sized cluster, but we have to offset into
1084 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment,
1085 * and then that value has to be rounded up to the hardware's DMA
1086 * alignment requirements, so all in all our buffer is that much smaller
1087 * than MCLBYTES.
1088 *
1089 * The resulting value is used as the frame truncation length and the
1090 * max buffer receive buffer size for now. It'll become more complex
1091 * when we support jumbo frames and receiving fragments of them into
1092 * separate buffers.
1093 */
1094 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN);
1095 maxfl = min(maxbuf, 0x7ff);
1096
1097 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1098 return;
1099
1100 /* Mask all interrupts and clear all current interrupt status bits. */
1101 WR4(sc, FEC_IEM_REG, 0x00000000);
1102 WR4(sc, FEC_IER_REG, 0xffffffff);
1103
1104 /*
1105 * Go set up palr/puar, galr/gaur, ialr/iaur.
1106 */
1107 ffec_setup_rxfilter(sc);
1108
1109 /*
1110 * TFWR - Transmit FIFO watermark register.
1111 *
1112 * Set the transmit fifo watermark register to "store and forward" mode
1113 * and also set a threshold of 128 bytes in the fifo before transmission
1114 * of a frame begins (to avoid dma underruns). Recent FEC hardware
1115 * supports STRFWD and when that bit is set, the watermark level in the
1116 * low bits is ignored. Older hardware doesn't have STRFWD, but writing
1117 * to that bit is innocuous, and the TWFR bits get used instead.
1118 */
1119 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);
1120
1121 /* RCR - Receive control register.
1122 *
1123 * Set max frame length + clean out anything left from u-boot.
1124 */
1125 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
1126
1127 /*
1128 * TCR - Transmit control register.
1129 *
1130 * Clean out anything left from u-boot. Any necessary values are set in
1131 * ffec_miibus_statchg() based on the media type.
1132 */
1133 WR4(sc, FEC_TCR_REG, 0);
1134
1135 /*
1136 * OPD - Opcode/pause duration.
1137 *
1138 * XXX These magic numbers come from u-boot.
1139 */
1140 WR4(sc, FEC_OPD_REG, 0x00010020);
1141
1142 /*
1143 * FRSR - Fifo receive start register.
1144 *
1145 * This register does not exist on imx6, it is present on earlier
1146 * hardware. The u-boot code sets this to a non-default value that's 32
1147 * bytes larger than the default, with no clue as to why. The default
1148 * value should work fine, so there's no code to init it here.
1149 */
1150
1151 /*
1152 * MRBR - Max RX buffer size.
1153 *
1154 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff,
1155 * but the datasheet says no such thing for imx6. On the imx6, setting
1156 * this to 2K without setting EN1588 resulted in a crazy runaway
1157 * receive loop in the hardware, where every rx descriptor in the ring
1158 * had its EMPTY flag cleared, no completion or error flags set, and a
1159 * length of zero. I think maybe you can only exceed it when EN1588 is
1160 * set, like maybe that's what enables jumbo frames, because in general
1161 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy-
1162 * compatible" flag.
1163 */
1164 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
1165
1166 /*
1167 * FTRL - Frame truncation length.
1168 *
1169 * Must be greater than or equal to the value set in FEC_RCR_MAXFL.
1170 */
1171 WR4(sc, FEC_FTRL_REG, maxfl);
1172
1173 /*
1174 * RDSR / TDSR descriptor ring pointers.
1175 *
1176 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its
1177 * internal current descriptor index values for both rings, so we zero
1178 * our index values as well.
1179 */
1180 sc->rx_idx = 0;
1181 sc->tx_idx_head = sc->tx_idx_tail = 0;
1182 sc->txcount = 0;
1183 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
1184 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
1185
1186 /*
1187 * EIM - interrupt mask register.
1188 *
1189 * We always enable the same set of interrupts while running; unlike
1190 * some drivers there's no need to change the mask on the fly depending
1191 * on what operations are in progress.
1192 */
1193 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);
1194
1195 /*
1196 * MIBC - MIB control (hardware stats).
1197 */
1198 regval = RD4(sc, FEC_MIBC_REG);
1199 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);
1200 ffec_clear_stats(sc);
1201 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
1202
1203 /*
1204 * ECR - Ethernet control register.
1205 *
1206 * This must happen after all the other config registers are set. If
1207 * we're running on little-endian hardware, also set the flag for byte-
1208 * swapping descriptor ring entries. This flag doesn't exist on older
1209 * hardware, but it can be safely set -- the bit position it occupies
1210 * was unused.
1211 */
1212 regval = RD4(sc, FEC_ECR_REG);
1213 #if _BYTE_ORDER == _LITTLE_ENDIAN
1214 regval |= FEC_ECR_DBSWP;
1215 #endif
1216 regval |= FEC_ECR_ETHEREN;
1217 WR4(sc, FEC_ECR_REG, regval);
1218
1219 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1220
1221 /*
1222 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to
1223 * set up the remaining config registers based on the current media.
1224 */
1225 mii_mediachg(sc->mii_softc);
1226 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
1227
1228 /*
1229 * Tell the hardware that receive buffers are available. They were made
1230 * available in ffec_attach() or ffec_stop().
1231 */
1232 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
1233 }
1234
1235 static void
ffec_init(void * if_softc)1236 ffec_init(void *if_softc)
1237 {
1238 struct ffec_softc *sc = if_softc;
1239
1240 FFEC_LOCK(sc);
1241 ffec_init_locked(sc);
1242 FFEC_UNLOCK(sc);
1243 }
1244
1245 static void
ffec_intr(void * arg)1246 ffec_intr(void *arg)
1247 {
1248 struct ffec_softc *sc;
1249 uint32_t ier;
1250
1251 sc = arg;
1252
1253 FFEC_LOCK(sc);
1254
1255 ier = RD4(sc, FEC_IER_REG);
1256
1257 if (ier & FEC_IER_TXF) {
1258 WR4(sc, FEC_IER_REG, FEC_IER_TXF);
1259 ffec_txfinish_locked(sc);
1260 }
1261
1262 if (ier & FEC_IER_RXF) {
1263 WR4(sc, FEC_IER_REG, FEC_IER_RXF);
1264 ffec_rxfinish_locked(sc);
1265 }
1266
1267 /*
1268 * We actually don't care about most errors, because the hardware copes
1269 * with them just fine, discarding the incoming bad frame, or forcing a
1270 * bad CRC onto an outgoing bad frame, and counting the errors in the
1271 * stats registers. The one that really matters is EBERR (DMA bus
1272 * error) because the hardware automatically clears ECR[ETHEREN] and we
1273 * have to restart it here. It should never happen.
1274 */
1275 if (ier & FEC_IER_EBERR) {
1276 WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
1277 device_printf(sc->dev,
1278 "Ethernet DMA error, restarting controller.\n");
1279 ffec_stop_locked(sc);
1280 ffec_init_locked(sc);
1281 }
1282
1283 FFEC_UNLOCK(sc);
1284
1285 }
1286
1287 static int
ffec_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1288 ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1289 {
1290 struct ffec_softc *sc;
1291 struct mii_data *mii;
1292 struct ifreq *ifr;
1293 int mask, error;
1294
1295 sc = ifp->if_softc;
1296 ifr = (struct ifreq *)data;
1297
1298 error = 0;
1299 switch (cmd) {
1300 case SIOCSIFFLAGS:
1301 FFEC_LOCK(sc);
1302 if (ifp->if_flags & IFF_UP) {
1303 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1304 if ((ifp->if_flags ^ sc->if_flags) &
1305 (IFF_PROMISC | IFF_ALLMULTI))
1306 ffec_setup_rxfilter(sc);
1307 } else {
1308 if (!sc->is_detaching)
1309 ffec_init_locked(sc);
1310 }
1311 } else {
1312 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1313 ffec_stop_locked(sc);
1314 }
1315 sc->if_flags = ifp->if_flags;
1316 FFEC_UNLOCK(sc);
1317 break;
1318
1319 case SIOCADDMULTI:
1320 case SIOCDELMULTI:
1321 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1322 FFEC_LOCK(sc);
1323 ffec_setup_rxfilter(sc);
1324 FFEC_UNLOCK(sc);
1325 }
1326 break;
1327
1328 case SIOCSIFMEDIA:
1329 case SIOCGIFMEDIA:
1330 mii = sc->mii_softc;
1331 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1332 break;
1333
1334 case SIOCSIFCAP:
1335 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1336 if (mask & IFCAP_VLAN_MTU) {
1337 /* No work to do except acknowledge the change took. */
1338 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1339 }
1340 break;
1341
1342 default:
1343 error = ether_ioctl(ifp, cmd, data);
1344 break;
1345 }
1346
1347 return (error);
1348 }
1349
1350 static int
ffec_detach(device_t dev)1351 ffec_detach(device_t dev)
1352 {
1353 struct ffec_softc *sc;
1354 bus_dmamap_t map;
1355 int idx;
1356
1357 /*
1358 * NB: This function can be called internally to unwind a failure to
1359 * attach. Make sure a resource got allocated/created before destroying.
1360 */
1361
1362 sc = device_get_softc(dev);
1363
1364 if (sc->is_attached) {
1365 FFEC_LOCK(sc);
1366 sc->is_detaching = true;
1367 ffec_stop_locked(sc);
1368 FFEC_UNLOCK(sc);
1369 callout_drain(&sc->ffec_callout);
1370 ether_ifdetach(sc->ifp);
1371 }
1372
1373 /* XXX no miibus detach? */
1374
1375 /* Clean up RX DMA resources and free mbufs. */
1376 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1377 if ((map = sc->rxbuf_map[idx].map) != NULL) {
1378 bus_dmamap_unload(sc->rxbuf_tag, map);
1379 bus_dmamap_destroy(sc->rxbuf_tag, map);
1380 m_freem(sc->rxbuf_map[idx].mbuf);
1381 }
1382 }
1383 if (sc->rxbuf_tag != NULL)
1384 bus_dma_tag_destroy(sc->rxbuf_tag);
1385 if (sc->rxdesc_map != NULL) {
1386 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map);
1387 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map);
1388 }
1389 if (sc->rxdesc_tag != NULL)
1390 bus_dma_tag_destroy(sc->rxdesc_tag);
1391
1392 /* Clean up TX DMA resources. */
1393 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1394 if ((map = sc->txbuf_map[idx].map) != NULL) {
1395 /* TX maps are already unloaded. */
1396 bus_dmamap_destroy(sc->txbuf_tag, map);
1397 }
1398 }
1399 if (sc->txbuf_tag != NULL)
1400 bus_dma_tag_destroy(sc->txbuf_tag);
1401 if (sc->txdesc_map != NULL) {
1402 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map);
1403 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map);
1404 }
1405 if (sc->txdesc_tag != NULL)
1406 bus_dma_tag_destroy(sc->txdesc_tag);
1407
1408 /* Release bus resources. */
1409 if (sc->intr_cookie)
1410 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
1411
1412 if (sc->irq_res != NULL)
1413 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
1414
1415 if (sc->mem_res != NULL)
1416 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
1417
1418 FFEC_LOCK_DESTROY(sc);
1419 return (0);
1420 }
1421
1422 static int
ffec_attach(device_t dev)1423 ffec_attach(device_t dev)
1424 {
1425 struct ffec_softc *sc;
1426 struct ifnet *ifp = NULL;
1427 struct mbuf *m;
1428 phandle_t ofw_node;
1429 int error, rid;
1430 uint8_t eaddr[ETHER_ADDR_LEN];
1431 char phy_conn_name[32];
1432 uint32_t idx, mscr;
1433
1434 sc = device_get_softc(dev);
1435 sc->dev = dev;
1436
1437 FFEC_LOCK_INIT(sc);
1438
1439 /*
1440 * There are differences in the implementation and features of the FEC
1441 * hardware on different SoCs, so figure out what type we are.
1442 */
1443 sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1444
1445 /*
1446 * We have to be told what kind of electrical connection exists between
1447 * the MAC and PHY or we can't operate correctly.
1448 */
1449 if ((ofw_node = ofw_bus_get_node(dev)) == -1) {
1450 device_printf(dev, "Impossible: Can't find ofw bus node\n");
1451 error = ENXIO;
1452 goto out;
1453 }
1454 if (OF_searchprop(ofw_node, "phy-mode",
1455 phy_conn_name, sizeof(phy_conn_name)) != -1) {
1456 if (strcasecmp(phy_conn_name, "mii") == 0)
1457 sc->phy_conn_type = PHY_CONN_MII;
1458 else if (strcasecmp(phy_conn_name, "rmii") == 0)
1459 sc->phy_conn_type = PHY_CONN_RMII;
1460 else if (strcasecmp(phy_conn_name, "rgmii") == 0)
1461 sc->phy_conn_type = PHY_CONN_RGMII;
1462 }
1463 if (sc->phy_conn_type == PHY_CONN_UNKNOWN) {
1464 device_printf(sc->dev, "No valid 'phy-mode' "
1465 "property found in FDT data for device.\n");
1466 error = ENOATTR;
1467 goto out;
1468 }
1469
1470 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0);
1471
1472 /* Allocate bus resources for accessing the hardware. */
1473 rid = 0;
1474 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1475 RF_ACTIVE);
1476 if (sc->mem_res == NULL) {
1477 device_printf(dev, "could not allocate memory resources.\n");
1478 error = ENOMEM;
1479 goto out;
1480 }
1481 rid = 0;
1482 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1483 RF_ACTIVE);
1484 if (sc->irq_res == NULL) {
1485 device_printf(dev, "could not allocate interrupt resources.\n");
1486 error = ENOMEM;
1487 goto out;
1488 }
1489
1490 /*
1491 * Set up TX descriptor ring, descriptors, and dma maps.
1492 */
1493 error = bus_dma_tag_create(
1494 bus_get_dma_tag(dev), /* Parent tag. */
1495 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1496 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1497 BUS_SPACE_MAXADDR, /* highaddr */
1498 NULL, NULL, /* filter, filterarg */
1499 TX_DESC_SIZE, 1, /* maxsize, nsegments */
1500 TX_DESC_SIZE, /* maxsegsize */
1501 0, /* flags */
1502 NULL, NULL, /* lockfunc, lockarg */
1503 &sc->txdesc_tag);
1504 if (error != 0) {
1505 device_printf(sc->dev,
1506 "could not create TX ring DMA tag.\n");
1507 goto out;
1508 }
1509
1510 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1511 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map);
1512 if (error != 0) {
1513 device_printf(sc->dev,
1514 "could not allocate TX descriptor ring.\n");
1515 goto out;
1516 }
1517
1518 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring,
1519 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0);
1520 if (error != 0) {
1521 device_printf(sc->dev,
1522 "could not load TX descriptor ring map.\n");
1523 goto out;
1524 }
1525
1526 error = bus_dma_tag_create(
1527 bus_get_dma_tag(dev), /* Parent tag. */
1528 FEC_TXBUF_ALIGN, 0, /* alignment, boundary */
1529 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1530 BUS_SPACE_MAXADDR, /* highaddr */
1531 NULL, NULL, /* filter, filterarg */
1532 MCLBYTES, 1, /* maxsize, nsegments */
1533 MCLBYTES, /* maxsegsize */
1534 0, /* flags */
1535 NULL, NULL, /* lockfunc, lockarg */
1536 &sc->txbuf_tag);
1537 if (error != 0) {
1538 device_printf(sc->dev,
1539 "could not create TX ring DMA tag.\n");
1540 goto out;
1541 }
1542
1543 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1544 error = bus_dmamap_create(sc->txbuf_tag, 0,
1545 &sc->txbuf_map[idx].map);
1546 if (error != 0) {
1547 device_printf(sc->dev,
1548 "could not create TX buffer DMA map.\n");
1549 goto out;
1550 }
1551 ffec_setup_txdesc(sc, idx, 0, 0);
1552 }
1553
1554 /*
1555 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
1556 */
1557 error = bus_dma_tag_create(
1558 bus_get_dma_tag(dev), /* Parent tag. */
1559 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1560 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1561 BUS_SPACE_MAXADDR, /* highaddr */
1562 NULL, NULL, /* filter, filterarg */
1563 RX_DESC_SIZE, 1, /* maxsize, nsegments */
1564 RX_DESC_SIZE, /* maxsegsize */
1565 0, /* flags */
1566 NULL, NULL, /* lockfunc, lockarg */
1567 &sc->rxdesc_tag);
1568 if (error != 0) {
1569 device_printf(sc->dev,
1570 "could not create RX ring DMA tag.\n");
1571 goto out;
1572 }
1573
1574 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1575 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map);
1576 if (error != 0) {
1577 device_printf(sc->dev,
1578 "could not allocate RX descriptor ring.\n");
1579 goto out;
1580 }
1581
1582 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring,
1583 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0);
1584 if (error != 0) {
1585 device_printf(sc->dev,
1586 "could not load RX descriptor ring map.\n");
1587 goto out;
1588 }
1589
1590 error = bus_dma_tag_create(
1591 bus_get_dma_tag(dev), /* Parent tag. */
1592 1, 0, /* alignment, boundary */
1593 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1594 BUS_SPACE_MAXADDR, /* highaddr */
1595 NULL, NULL, /* filter, filterarg */
1596 MCLBYTES, 1, /* maxsize, nsegments */
1597 MCLBYTES, /* maxsegsize */
1598 0, /* flags */
1599 NULL, NULL, /* lockfunc, lockarg */
1600 &sc->rxbuf_tag);
1601 if (error != 0) {
1602 device_printf(sc->dev,
1603 "could not create RX buf DMA tag.\n");
1604 goto out;
1605 }
1606
1607 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1608 error = bus_dmamap_create(sc->rxbuf_tag, 0,
1609 &sc->rxbuf_map[idx].map);
1610 if (error != 0) {
1611 device_printf(sc->dev,
1612 "could not create RX buffer DMA map.\n");
1613 goto out;
1614 }
1615 if ((m = ffec_alloc_mbufcl(sc)) == NULL) {
1616 device_printf(dev, "Could not alloc mbuf\n");
1617 error = ENOMEM;
1618 goto out;
1619 }
1620 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) {
1621 device_printf(sc->dev,
1622 "could not create new RX buffer.\n");
1623 goto out;
1624 }
1625 }
1626
1627 /* Try to get the MAC address from the hardware before resetting it. */
1628 ffec_get_hwaddr(sc, eaddr);
1629
1630 /* Reset the hardware. Disables all interrupts. */
1631 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
1632
1633 /* Setup interrupt handler. */
1634 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
1635 NULL, ffec_intr, sc, &sc->intr_cookie);
1636 if (error != 0) {
1637 device_printf(dev, "could not setup interrupt handler.\n");
1638 goto out;
1639 }
1640
1641 /*
1642 * Set up the PHY control register.
1643 *
1644 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2).
1645 * Speed formula for FEC is md_clock = mac_clock / (N * 2)
1646 *
1647 * XXX - Revisit this...
1648 *
1649 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot
1650 * code uses 10. Both values seem to work, but I suspect many modern
1651 * PHY parts can do mdio at speeds far above the standard 2.5 MHz.
1652 *
1653 * Different imx manuals use confusingly different terminology (things
1654 * like "system clock" and "internal module clock") with examples that
1655 * use frequencies that have nothing to do with ethernet, giving the
1656 * vague impression that maybe the clock in question is the periphclock
1657 * or something. In fact, on an imx53 development board (FEC),
1658 * measuring the mdio clock at the pin on the PHY and playing with
1659 * various divisors showed that the root speed was 66 MHz (clk_ipg_root
1660 * aka periphclock) and 13 was the right divisor.
1661 *
1662 * All in all, it seems likely that 13 is a safe divisor for now,
1663 * because if we really do need to base it on the peripheral clock
1664 * speed, then we need a platform-independant get-clock-freq API.
1665 */
1666 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT;
1667 if (OF_hasprop(ofw_node, "phy-disable-preamble")) {
1668 mscr |= FEC_MSCR_DIS_PRE;
1669 if (bootverbose)
1670 device_printf(dev, "PHY preamble disabled\n");
1671 }
1672 WR4(sc, FEC_MSCR_REG, mscr);
1673
1674 /* Set up the ethernet interface. */
1675 sc->ifp = ifp = if_alloc(IFT_ETHER);
1676
1677 ifp->if_softc = sc;
1678 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1679 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1680 ifp->if_capabilities = IFCAP_VLAN_MTU;
1681 ifp->if_capenable = ifp->if_capabilities;
1682 ifp->if_start = ffec_txstart;
1683 ifp->if_ioctl = ffec_ioctl;
1684 ifp->if_init = ffec_init;
1685 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1686 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1687 IFQ_SET_READY(&ifp->if_snd);
1688 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1689
1690 #if 0 /* XXX The hardware keeps stats we could use for these. */
1691 ifp->if_linkmib = &sc->mibdata;
1692 ifp->if_linkmiblen = sizeof(sc->mibdata);
1693 #endif
1694
1695 /* Set up the miigasket hardware (if any). */
1696 ffec_miigasket_setup(sc);
1697
1698 /* Attach the mii driver. */
1699 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change,
1700 ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1701 if (error != 0) {
1702 device_printf(dev, "PHY attach failed\n");
1703 goto out;
1704 }
1705 sc->mii_softc = device_get_softc(sc->miibus);
1706
1707 /* All ready to run, attach the ethernet interface. */
1708 ether_ifattach(ifp, eaddr);
1709 sc->is_attached = true;
1710
1711 error = 0;
1712 out:
1713
1714 if (error != 0)
1715 ffec_detach(dev);
1716
1717 return (error);
1718 }
1719
1720 static int
ffec_probe(device_t dev)1721 ffec_probe(device_t dev)
1722 {
1723 uintptr_t fectype;
1724
1725 if (!ofw_bus_status_okay(dev))
1726 return (ENXIO);
1727
1728 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1729 if (fectype == FECTYPE_NONE)
1730 return (ENXIO);
1731
1732 device_set_desc(dev, (fectype & FECFLAG_GBE) ?
1733 "Freescale Gigabit Ethernet Controller" :
1734 "Freescale Fast Ethernet Controller");
1735
1736 return (BUS_PROBE_DEFAULT);
1737 }
1738
1739
1740 static device_method_t ffec_methods[] = {
1741 /* Device interface. */
1742 DEVMETHOD(device_probe, ffec_probe),
1743 DEVMETHOD(device_attach, ffec_attach),
1744 DEVMETHOD(device_detach, ffec_detach),
1745
1746 /*
1747 DEVMETHOD(device_shutdown, ffec_shutdown),
1748 DEVMETHOD(device_suspend, ffec_suspend),
1749 DEVMETHOD(device_resume, ffec_resume),
1750 */
1751
1752 /* MII interface. */
1753 DEVMETHOD(miibus_readreg, ffec_miibus_readreg),
1754 DEVMETHOD(miibus_writereg, ffec_miibus_writereg),
1755 DEVMETHOD(miibus_statchg, ffec_miibus_statchg),
1756
1757 DEVMETHOD_END
1758 };
1759
1760 static driver_t ffec_driver = {
1761 "ffec",
1762 ffec_methods,
1763 sizeof(struct ffec_softc)
1764 };
1765
1766 static devclass_t ffec_devclass;
1767
1768 DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0);
1769 DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0);
1770
1771 MODULE_DEPEND(ffec, ether, 1, 1, 1);
1772 MODULE_DEPEND(ffec, miibus, 1, 1, 1);
1773