1 /* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- 2 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Jeff Hartmann <jhartmann@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 * 31 * Rewritten by: 32 * Gareth Hughes <gareth@valinux.com> 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD: stable/10/sys/dev/drm/mga_drm.h 182080 2008-08-23 20:59:12Z rnoland $"); 37 38 #ifndef __MGA_DRM_H__ 39 #define __MGA_DRM_H__ 40 41 /* WARNING: If you change any of these defines, make sure to change the 42 * defines in the Xserver file (mga_sarea.h) 43 */ 44 45 #ifndef __MGA_SAREA_DEFINES__ 46 #define __MGA_SAREA_DEFINES__ 47 48 /* WARP pipe flags 49 */ 50 #define MGA_F 0x1 /* fog */ 51 #define MGA_A 0x2 /* alpha */ 52 #define MGA_S 0x4 /* specular */ 53 #define MGA_T2 0x8 /* multitexture */ 54 55 #define MGA_WARP_TGZ 0 56 #define MGA_WARP_TGZF (MGA_F) 57 #define MGA_WARP_TGZA (MGA_A) 58 #define MGA_WARP_TGZAF (MGA_F|MGA_A) 59 #define MGA_WARP_TGZS (MGA_S) 60 #define MGA_WARP_TGZSF (MGA_S|MGA_F) 61 #define MGA_WARP_TGZSA (MGA_S|MGA_A) 62 #define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) 63 #define MGA_WARP_T2GZ (MGA_T2) 64 #define MGA_WARP_T2GZF (MGA_T2|MGA_F) 65 #define MGA_WARP_T2GZA (MGA_T2|MGA_A) 66 #define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) 67 #define MGA_WARP_T2GZS (MGA_T2|MGA_S) 68 #define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) 69 #define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) 70 #define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) 71 72 #define MGA_MAX_G200_PIPES 8 /* no multitex */ 73 #define MGA_MAX_G400_PIPES 16 74 #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES 75 #define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ 76 77 #define MGA_CARD_TYPE_G200 1 78 #define MGA_CARD_TYPE_G400 2 79 #define MGA_CARD_TYPE_G450 3 /* not currently used */ 80 #define MGA_CARD_TYPE_G550 4 81 82 #define MGA_FRONT 0x1 83 #define MGA_BACK 0x2 84 #define MGA_DEPTH 0x4 85 86 /* What needs to be changed for the current vertex dma buffer? 87 */ 88 #define MGA_UPLOAD_CONTEXT 0x1 89 #define MGA_UPLOAD_TEX0 0x2 90 #define MGA_UPLOAD_TEX1 0x4 91 #define MGA_UPLOAD_PIPE 0x8 92 #define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ 93 #define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ 94 #define MGA_UPLOAD_2D 0x40 95 #define MGA_WAIT_AGE 0x80 /* handled client-side */ 96 #define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ 97 #if 0 98 #define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock 99 quiescent */ 100 #endif 101 102 /* 32 buffers of 64k each, total 2 meg. 103 */ 104 #define MGA_BUFFER_SIZE (1 << 16) 105 #define MGA_NUM_BUFFERS 128 106 107 /* Keep these small for testing. 108 */ 109 #define MGA_NR_SAREA_CLIPRECTS 8 110 111 /* 2 heaps (1 for card, 1 for agp), each divided into upto 128 112 * regions, subject to a minimum region size of (1<<16) == 64k. 113 * 114 * Clients may subdivide regions internally, but when sharing between 115 * clients, the region size is the minimum granularity. 116 */ 117 118 #define MGA_CARD_HEAP 0 119 #define MGA_AGP_HEAP 1 120 #define MGA_NR_TEX_HEAPS 2 121 #define MGA_NR_TEX_REGIONS 16 122 #define MGA_LOG_MIN_TEX_REGION_SIZE 16 123 124 #define DRM_MGA_IDLE_RETRY 2048 125 126 #endif /* __MGA_SAREA_DEFINES__ */ 127 128 /* Setup registers for 3D context 129 */ 130 typedef struct { 131 unsigned int dstorg; 132 unsigned int maccess; 133 unsigned int plnwt; 134 unsigned int dwgctl; 135 unsigned int alphactrl; 136 unsigned int fogcolor; 137 unsigned int wflag; 138 unsigned int tdualstage0; 139 unsigned int tdualstage1; 140 unsigned int fcol; 141 unsigned int stencil; 142 unsigned int stencilctl; 143 } drm_mga_context_regs_t; 144 145 /* Setup registers for 2D, X server 146 */ 147 typedef struct { 148 unsigned int pitch; 149 } drm_mga_server_regs_t; 150 151 /* Setup registers for each texture unit 152 */ 153 typedef struct { 154 unsigned int texctl; 155 unsigned int texctl2; 156 unsigned int texfilter; 157 unsigned int texbordercol; 158 unsigned int texorg; 159 unsigned int texwidth; 160 unsigned int texheight; 161 unsigned int texorg1; 162 unsigned int texorg2; 163 unsigned int texorg3; 164 unsigned int texorg4; 165 } drm_mga_texture_regs_t; 166 167 /* General aging mechanism 168 */ 169 typedef struct { 170 unsigned int head; /* Position of head pointer */ 171 unsigned int wrap; /* Primary DMA wrap count */ 172 } drm_mga_age_t; 173 174 typedef struct _drm_mga_sarea { 175 /* The channel for communication of state information to the kernel 176 * on firing a vertex dma buffer. 177 */ 178 drm_mga_context_regs_t context_state; 179 drm_mga_server_regs_t server_state; 180 drm_mga_texture_regs_t tex_state[2]; 181 unsigned int warp_pipe; 182 unsigned int dirty; 183 unsigned int vertsize; 184 185 /* The current cliprects, or a subset thereof. 186 */ 187 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; 188 unsigned int nbox; 189 190 /* Information about the most recently used 3d drawable. The 191 * client fills in the req_* fields, the server fills in the 192 * exported_ fields and puts the cliprects into boxes, above. 193 * 194 * The client clears the exported_drawable field before 195 * clobbering the boxes data. 196 */ 197 unsigned int req_drawable; /* the X drawable id */ 198 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ 199 200 unsigned int exported_drawable; 201 unsigned int exported_index; 202 unsigned int exported_stamp; 203 unsigned int exported_buffers; 204 unsigned int exported_nfront; 205 unsigned int exported_nback; 206 int exported_back_x, exported_front_x, exported_w; 207 int exported_back_y, exported_front_y, exported_h; 208 struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; 209 210 /* Counters for aging textures and for client-side throttling. 211 */ 212 unsigned int status[4]; 213 unsigned int last_wrap; 214 215 drm_mga_age_t last_frame; 216 unsigned int last_enqueue; /* last time a buffer was enqueued */ 217 unsigned int last_dispatch; /* age of the most recently dispatched buffer */ 218 unsigned int last_quiescent; /* */ 219 220 /* LRU lists for texture memory in agp space and on the card. 221 */ 222 struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; 223 unsigned int texAge[MGA_NR_TEX_HEAPS]; 224 225 /* Mechanism to validate card state. 226 */ 227 int ctxOwner; 228 } drm_mga_sarea_t; 229 230 231 /* MGA specific ioctls 232 * The device specific ioctl range is 0x40 to 0x79. 233 */ 234 #define DRM_MGA_INIT 0x00 235 #define DRM_MGA_FLUSH 0x01 236 #define DRM_MGA_RESET 0x02 237 #define DRM_MGA_SWAP 0x03 238 #define DRM_MGA_CLEAR 0x04 239 #define DRM_MGA_VERTEX 0x05 240 #define DRM_MGA_INDICES 0x06 241 #define DRM_MGA_ILOAD 0x07 242 #define DRM_MGA_BLIT 0x08 243 #define DRM_MGA_GETPARAM 0x09 244 245 /* 3.2: 246 * ioctls for operating on fences. 247 */ 248 #define DRM_MGA_SET_FENCE 0x0a 249 #define DRM_MGA_WAIT_FENCE 0x0b 250 #define DRM_MGA_DMA_BOOTSTRAP 0x0c 251 252 253 #define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) 254 #define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) 255 #define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) 256 #define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) 257 #define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) 258 #define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) 259 #define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) 260 #define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) 261 #define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) 262 #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) 263 #define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t) 264 #define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t) 265 #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) 266 267 typedef struct _drm_mga_warp_index { 268 int installed; 269 unsigned long phys_addr; 270 int size; 271 } drm_mga_warp_index_t; 272 273 typedef struct drm_mga_init { 274 enum { 275 MGA_INIT_DMA = 0x01, 276 MGA_CLEANUP_DMA = 0x02 277 } func; 278 279 unsigned long sarea_priv_offset; 280 281 int chipset; 282 int sgram; 283 284 unsigned int maccess; 285 286 unsigned int fb_cpp; 287 unsigned int front_offset, front_pitch; 288 unsigned int back_offset, back_pitch; 289 290 unsigned int depth_cpp; 291 unsigned int depth_offset, depth_pitch; 292 293 unsigned int texture_offset[MGA_NR_TEX_HEAPS]; 294 unsigned int texture_size[MGA_NR_TEX_HEAPS]; 295 296 unsigned long fb_offset; 297 unsigned long mmio_offset; 298 unsigned long status_offset; 299 unsigned long warp_offset; 300 unsigned long primary_offset; 301 unsigned long buffers_offset; 302 } drm_mga_init_t; 303 304 305 typedef struct drm_mga_dma_bootstrap { 306 /** 307 * \name AGP texture region 308 * 309 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will 310 * be filled in with the actual AGP texture settings. 311 * 312 * \warning 313 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode 314 * is zero, it means that PCI memory (most likely through the use of 315 * an IOMMU) is being used for "AGP" textures. 316 */ 317 /*@{*/ 318 unsigned long texture_handle; /**< Handle used to map AGP textures. */ 319 uint32_t texture_size; /**< Size of the AGP texture region. */ 320 /*@}*/ 321 322 323 /** 324 * Requested size of the primary DMA region. 325 * 326 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 327 * filled in with the actual AGP mode. If AGP was not available 328 */ 329 uint32_t primary_size; 330 331 332 /** 333 * Requested number of secondary DMA buffers. 334 * 335 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 336 * filled in with the actual number of secondary DMA buffers 337 * allocated. Particularly when PCI DMA is used, this may be 338 * (subtantially) less than the number requested. 339 */ 340 uint32_t secondary_bin_count; 341 342 343 /** 344 * Requested size of each secondary DMA buffer. 345 * 346 * While the kernel \b is free to reduce 347 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed 348 * to reduce dma_mga_dma_bootstrap::secondary_bin_size. 349 */ 350 uint32_t secondary_bin_size; 351 352 353 /** 354 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, 355 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is 356 * zero, it means that PCI DMA should be used, even if AGP is 357 * possible. 358 * 359 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 360 * filled in with the actual AGP mode. If AGP was not available 361 * (i.e., PCI DMA was used), this value will be zero. 362 */ 363 uint32_t agp_mode; 364 365 366 /** 367 * Desired AGP GART size, measured in megabytes. 368 */ 369 uint8_t agp_size; 370 } drm_mga_dma_bootstrap_t; 371 372 typedef struct drm_mga_clear { 373 unsigned int flags; 374 unsigned int clear_color; 375 unsigned int clear_depth; 376 unsigned int color_mask; 377 unsigned int depth_mask; 378 } drm_mga_clear_t; 379 380 typedef struct drm_mga_vertex { 381 int idx; /* buffer to queue */ 382 int used; /* bytes in use */ 383 int discard; /* client finished with buffer? */ 384 } drm_mga_vertex_t; 385 386 typedef struct drm_mga_indices { 387 int idx; /* buffer to queue */ 388 unsigned int start; 389 unsigned int end; 390 int discard; /* client finished with buffer? */ 391 } drm_mga_indices_t; 392 393 typedef struct drm_mga_iload { 394 int idx; 395 unsigned int dstorg; 396 unsigned int length; 397 } drm_mga_iload_t; 398 399 typedef struct _drm_mga_blit { 400 unsigned int planemask; 401 unsigned int srcorg; 402 unsigned int dstorg; 403 int src_pitch, dst_pitch; 404 int delta_sx, delta_sy; 405 int delta_dx, delta_dy; 406 int height, ydir; /* flip image vertically */ 407 int source_pitch, dest_pitch; 408 } drm_mga_blit_t; 409 410 /* 3.1: An ioctl to get parameters that aren't available to the 3d 411 * client any other way. 412 */ 413 #define MGA_PARAM_IRQ_NR 1 414 415 /* 3.2: Query the actual card type. The DDX only distinguishes between 416 * G200 chips and non-G200 chips, which it calls G400. It turns out that 417 * there are some very sublte differences between the G4x0 chips and the G550 418 * chips. Using this parameter query, a client-side driver can detect the 419 * difference between a G4x0 and a G550. 420 */ 421 #define MGA_PARAM_CARD_TYPE 2 422 423 typedef struct drm_mga_getparam { 424 int param; 425 void __user *value; 426 } drm_mga_getparam_t; 427 428 #endif 429