1 /*-
2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/10/sys/arm/lpc/lpc_mmc.c 318198 2017-05-11 21:01:02Z marius $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
39 #include <sys/rman.h>
40
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/resource.h>
45 #include <machine/intr.h>
46
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49
50 #include <dev/mmc/bridge.h>
51 #include <dev/mmc/mmcbrvar.h>
52
53 #include <arm/lpc/lpcreg.h>
54 #include <arm/lpc/lpcvar.h>
55
56 #ifdef DEBUG
57 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
58 printf(fmt,##args); } while (0)
59 #else
60 #define debugf(fmt, args...)
61 #endif
62
63 struct lpc_mmc_dmamap_arg {
64 bus_addr_t lm_dma_busaddr;
65 };
66
67 struct lpc_mmc_softc {
68 device_t lm_dev;
69 struct mtx lm_mtx;
70 struct resource * lm_mem_res;
71 struct resource * lm_irq_res;
72 bus_space_tag_t lm_bst;
73 bus_space_handle_t lm_bsh;
74 void * lm_intrhand;
75 struct mmc_host lm_host;
76 struct mmc_request * lm_req;
77 struct mmc_data * lm_data;
78 uint32_t lm_flags;
79 #define LPC_SD_FLAGS_IGNORECRC (1 << 0)
80 int lm_xfer_direction;
81 #define DIRECTION_READ 0
82 #define DIRECTION_WRITE 1
83 int lm_xfer_done;
84 int lm_bus_busy;
85 bus_dma_tag_t lm_dma_tag;
86 bus_dmamap_t lm_dma_map;
87 bus_addr_t lm_buffer_phys;
88 void * lm_buffer;
89 };
90
91 #define LPC_SD_MAX_BLOCKSIZE 1024
92 /* XXX */
93 #define LPC_MMC_DMACH_READ 1
94 #define LPC_MMC_DMACH_WRITE 0
95
96
97 static int lpc_mmc_probe(device_t);
98 static int lpc_mmc_attach(device_t);
99 static int lpc_mmc_detach(device_t);
100 static void lpc_mmc_intr(void *);
101
102 static void lpc_mmc_cmd(struct lpc_mmc_softc *, struct mmc_command *);
103 static void lpc_mmc_setup_xfer(struct lpc_mmc_softc *, struct mmc_data *);
104
105 static int lpc_mmc_update_ios(device_t, device_t);
106 static int lpc_mmc_request(device_t, device_t, struct mmc_request *);
107 static int lpc_mmc_get_ro(device_t, device_t);
108 static int lpc_mmc_acquire_host(device_t, device_t);
109 static int lpc_mmc_release_host(device_t, device_t);
110
111 static void lpc_mmc_dma_rxfinish(void *);
112 static void lpc_mmc_dma_rxerror(void *);
113 static void lpc_mmc_dma_txfinish(void *);
114 static void lpc_mmc_dma_txerror(void *);
115
116 static void lpc_mmc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
117
118 #define lpc_mmc_lock(_sc) \
119 mtx_lock(&_sc->lm_mtx);
120 #define lpc_mmc_unlock(_sc) \
121 mtx_unlock(&_sc->lm_mtx);
122 #define lpc_mmc_read_4(_sc, _reg) \
123 bus_space_read_4(_sc->lm_bst, _sc->lm_bsh, _reg)
124 #define lpc_mmc_write_4(_sc, _reg, _value) \
125 bus_space_write_4(_sc->lm_bst, _sc->lm_bsh, _reg, _value)
126
127 static struct lpc_dmac_channel_config lpc_mmc_dma_rxconf = {
128 .ldc_fcntl = LPC_DMAC_FLOW_D_P2M,
129 .ldc_src_periph = LPC_DMAC_SD_ID,
130 .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
131 .ldc_src_incr = 0,
132 .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
133 .ldc_dst_periph = LPC_DMAC_SD_ID,
134 .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
135 .ldc_dst_incr = 1,
136 .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
137 .ldc_success_handler = lpc_mmc_dma_rxfinish,
138 .ldc_error_handler = lpc_mmc_dma_rxerror,
139 };
140
141 static struct lpc_dmac_channel_config lpc_mmc_dma_txconf = {
142 .ldc_fcntl = LPC_DMAC_FLOW_P_M2P,
143 .ldc_src_periph = LPC_DMAC_SD_ID,
144 .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
145 .ldc_src_incr = 1,
146 .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
147 .ldc_dst_periph = LPC_DMAC_SD_ID,
148 .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
149 .ldc_dst_incr = 0,
150 .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
151 .ldc_success_handler = lpc_mmc_dma_txfinish,
152 .ldc_error_handler = lpc_mmc_dma_txerror,
153 };
154
155 static int
lpc_mmc_probe(device_t dev)156 lpc_mmc_probe(device_t dev)
157 {
158
159 if (!ofw_bus_status_okay(dev))
160 return (ENXIO);
161
162 if (!ofw_bus_is_compatible(dev, "lpc,mmc"))
163 return (ENXIO);
164
165 device_set_desc(dev, "LPC32x0 MMC/SD controller");
166 return (BUS_PROBE_DEFAULT);
167 }
168
169 static int
lpc_mmc_attach(device_t dev)170 lpc_mmc_attach(device_t dev)
171 {
172 struct lpc_mmc_softc *sc = device_get_softc(dev);
173 struct lpc_mmc_dmamap_arg ctx;
174 device_t child;
175 int rid, err;
176
177 sc->lm_dev = dev;
178 sc->lm_req = NULL;
179
180 mtx_init(&sc->lm_mtx, "lpcmmc", "mmc", MTX_DEF);
181
182 rid = 0;
183 sc->lm_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
184 RF_ACTIVE);
185 if (!sc->lm_mem_res) {
186 device_printf(dev, "cannot allocate memory window\n");
187 return (ENXIO);
188 }
189
190 sc->lm_bst = rman_get_bustag(sc->lm_mem_res);
191 sc->lm_bsh = rman_get_bushandle(sc->lm_mem_res);
192
193 debugf("virtual register space: 0x%08lx\n", sc->lm_bsh);
194
195 rid = 0;
196 sc->lm_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
197 RF_ACTIVE);
198 if (!sc->lm_irq_res) {
199 device_printf(dev, "cannot allocate interrupt\n");
200 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
201 return (ENXIO);
202 }
203
204 if (bus_setup_intr(dev, sc->lm_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
205 NULL, lpc_mmc_intr, sc, &sc->lm_intrhand))
206 {
207 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
208 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
209 device_printf(dev, "cannot setup interrupt handler\n");
210 return (ENXIO);
211 }
212
213 sc->lm_host.f_min = 312500;
214 sc->lm_host.f_max = 2500000;
215 sc->lm_host.host_ocr = MMC_OCR_300_310 | MMC_OCR_310_320 |
216 MMC_OCR_320_330 | MMC_OCR_330_340;
217 #if 0
218 sc->lm_host.caps = MMC_CAP_4_BIT_DATA;
219 #endif
220
221 lpc_pwr_write(dev, LPC_CLKPWR_MS_CTRL,
222 LPC_CLKPWR_MS_CTRL_CLOCK_EN | LPC_CLKPWR_MS_CTRL_SD_CLOCK | 1);
223 lpc_mmc_write_4(sc, LPC_SD_POWER, LPC_SD_POWER_CTRL_ON);
224
225 device_set_ivars(dev, &sc->lm_host);
226
227 child = device_add_child(dev, "mmc", -1);
228 if (!child) {
229 device_printf(dev, "attaching MMC bus failed!\n");
230 bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
231 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
232 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
233 return (ENXIO);
234 }
235
236 /* Alloc DMA memory */
237 err = bus_dma_tag_create(
238 bus_get_dma_tag(sc->lm_dev),
239 4, 0, /* alignment, boundary */
240 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
241 BUS_SPACE_MAXADDR, /* highaddr */
242 NULL, NULL, /* filter, filterarg */
243 LPC_SD_MAX_BLOCKSIZE, 1, /* maxsize, nsegments */
244 LPC_SD_MAX_BLOCKSIZE, 0, /* maxsegsize, flags */
245 NULL, NULL, /* lockfunc, lockarg */
246 &sc->lm_dma_tag);
247
248 err = bus_dmamem_alloc(sc->lm_dma_tag, (void **)&sc->lm_buffer,
249 0, &sc->lm_dma_map);
250 if (err) {
251 device_printf(dev, "cannot allocate framebuffer\n");
252 goto fail;
253 }
254
255 err = bus_dmamap_load(sc->lm_dma_tag, sc->lm_dma_map, sc->lm_buffer,
256 LPC_SD_MAX_BLOCKSIZE, lpc_mmc_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
257 if (err) {
258 device_printf(dev, "cannot load DMA map\n");
259 goto fail;
260 }
261
262 sc->lm_buffer_phys = ctx.lm_dma_busaddr;
263
264 lpc_mmc_dma_rxconf.ldc_handler_arg = (void *)sc;
265 err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_READ, &lpc_mmc_dma_rxconf);
266 if (err) {
267 device_printf(dev, "cannot allocate RX DMA channel\n");
268 goto fail;
269 }
270
271
272 lpc_mmc_dma_txconf.ldc_handler_arg = (void *)sc;
273 err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_WRITE, &lpc_mmc_dma_txconf);
274 if (err) {
275 device_printf(dev, "cannot allocate TX DMA channel\n");
276 goto fail;
277 }
278
279 bus_generic_probe(dev);
280 bus_generic_attach(dev);
281
282 return (0);
283
284 fail:
285 if (sc->lm_intrhand)
286 bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
287 if (sc->lm_irq_res)
288 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
289 if (sc->lm_mem_res)
290 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
291 return (err);
292 }
293
294 static int
lpc_mmc_detach(device_t dev)295 lpc_mmc_detach(device_t dev)
296 {
297 return (EBUSY);
298 }
299
300 static void
lpc_mmc_intr(void * arg)301 lpc_mmc_intr(void *arg)
302 {
303 struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
304 struct mmc_command *cmd;
305 uint32_t status;
306
307 status = lpc_mmc_read_4(sc, LPC_SD_STATUS);
308
309 debugf("interrupt: 0x%08x\n", status);
310
311 if (status & LPC_SD_STATUS_CMDCRCFAIL) {
312 cmd = sc->lm_req->cmd;
313 cmd->error = sc->lm_flags & LPC_SD_FLAGS_IGNORECRC
314 ? MMC_ERR_NONE : MMC_ERR_BADCRC;
315 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
316 sc->lm_req->done(sc->lm_req);
317 sc->lm_req = NULL;
318 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDCRCFAIL);
319 }
320
321 if (status & LPC_SD_STATUS_CMDACTIVE)
322 {
323 debugf("command active\n");
324 cmd = sc->lm_req->cmd;
325 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
326 sc->lm_req->done(sc->lm_req);
327 sc->lm_req = NULL;
328 }
329
330 if (status & LPC_SD_STATUS_DATATIMEOUT) {
331 device_printf(sc->lm_dev, "data timeout\n");
332 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATATIMEOUT);
333 }
334
335 if (status & LPC_SD_STATUS_TXUNDERRUN) {
336 device_printf(sc->lm_dev, "TX underrun\n");
337 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_TXUNDERRUN);
338 }
339
340 if (status & LPC_SD_STATUS_CMDRESPEND) {
341 debugf("command response\n");
342 cmd = sc->lm_req->cmd;
343
344 if (cmd->flags & MMC_RSP_136) {
345 cmd->resp[3] = lpc_mmc_read_4(sc, LPC_SD_RESP3);
346 cmd->resp[2] = lpc_mmc_read_4(sc, LPC_SD_RESP2);
347 cmd->resp[1] = lpc_mmc_read_4(sc, LPC_SD_RESP1);
348 }
349
350 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
351 cmd->error = MMC_ERR_NONE;
352
353 if (cmd->data && (cmd->data->flags & MMC_DATA_WRITE))
354 lpc_mmc_setup_xfer(sc, sc->lm_req->cmd->data);
355
356 if (!cmd->data) {
357 sc->lm_req->done(sc->lm_req);
358 sc->lm_req = NULL;
359 }
360
361 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDRESPEND);
362 }
363
364 if (status & LPC_SD_STATUS_CMDSENT) {
365 debugf("command sent\n");
366 cmd = sc->lm_req->cmd;
367 cmd->error = MMC_ERR_NONE;
368 sc->lm_req->done(sc->lm_req);
369 sc->lm_req = NULL;
370 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDSENT);
371 }
372
373 if (status & LPC_SD_STATUS_DATAEND) {
374 if (sc->lm_xfer_direction == DIRECTION_READ)
375 lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
376
377 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATAEND);
378 }
379
380 if (status & LPC_SD_STATUS_CMDTIMEOUT) {
381 device_printf(sc->lm_dev, "command response timeout\n");
382 cmd = sc->lm_req->cmd;
383 cmd->error = MMC_ERR_TIMEOUT;
384 sc->lm_req->done(sc->lm_req);
385 sc->lm_req = NULL;
386 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDTIMEOUT);
387 return;
388 }
389
390 if (status & LPC_SD_STATUS_STARTBITERR) {
391 device_printf(sc->lm_dev, "start bit error\n");
392 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_STARTBITERR);
393 }
394
395 if (status & LPC_SD_STATUS_DATACRCFAIL) {
396 device_printf(sc->lm_dev, "data CRC error\n");
397 debugf("data buffer: %p\n", sc->lm_buffer);
398 cmd = sc->lm_req->cmd;
399 cmd->error = MMC_ERR_BADCRC;
400 sc->lm_req->done(sc->lm_req);
401 sc->lm_req = NULL;
402
403 if (sc->lm_xfer_direction == DIRECTION_READ)
404 lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
405
406 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATACRCFAIL);
407 }
408
409 if (status & LPC_SD_STATUS_DATABLOCKEND) {
410 debugf("data block end\n");
411 if (sc->lm_xfer_direction == DIRECTION_READ)
412 memcpy(sc->lm_data->data, sc->lm_buffer, sc->lm_data->len);
413
414 if (sc->lm_xfer_direction == DIRECTION_WRITE) {
415 lpc_dmac_disable_channel(sc->lm_dev, LPC_MMC_DMACH_WRITE);
416 lpc_mmc_write_4(sc, LPC_SD_DATACTRL, 0);
417 }
418
419 sc->lm_req->done(sc->lm_req);
420 sc->lm_req = NULL;
421 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATABLOCKEND);
422 }
423
424 debugf("done\n");
425 }
426
427 static int
lpc_mmc_request(device_t bus,device_t child,struct mmc_request * req)428 lpc_mmc_request(device_t bus, device_t child, struct mmc_request *req)
429 {
430 struct lpc_mmc_softc *sc = device_get_softc(bus);
431
432 debugf("request: %p\n", req);
433
434 lpc_mmc_lock(sc);
435 if (sc->lm_req)
436 return (EBUSY);
437
438 sc->lm_req = req;
439
440 if (req->cmd->data && req->cmd->data->flags & MMC_DATA_WRITE) {
441 memcpy(sc->lm_buffer, req->cmd->data->data, req->cmd->data->len);
442 lpc_mmc_cmd(sc, req->cmd);
443 lpc_mmc_unlock(sc);
444 return (0);
445 }
446
447 if (req->cmd->data)
448 lpc_mmc_setup_xfer(sc, req->cmd->data);
449
450 lpc_mmc_cmd(sc, req->cmd);
451 lpc_mmc_unlock(sc);
452
453 return (0);
454 }
455
456 static void
lpc_mmc_cmd(struct lpc_mmc_softc * sc,struct mmc_command * cmd)457 lpc_mmc_cmd(struct lpc_mmc_softc *sc, struct mmc_command *cmd)
458 {
459 uint32_t cmdreg = 0;
460
461 debugf("cmd: %d arg: 0x%08x\n", cmd->opcode, cmd->arg);
462
463 if (lpc_mmc_read_4(sc, LPC_SD_COMMAND) & LPC_SD_COMMAND_ENABLE) {
464 lpc_mmc_write_4(sc, LPC_SD_COMMAND, 0);
465 DELAY(1000);
466 }
467
468 sc->lm_flags &= ~LPC_SD_FLAGS_IGNORECRC;
469
470 if (cmd->flags & MMC_RSP_PRESENT)
471 cmdreg |= LPC_SD_COMMAND_RESPONSE;
472
473 if (MMC_RSP(cmd->flags) == MMC_RSP_R2)
474 cmdreg |= LPC_SD_COMMAND_LONGRSP;
475
476 if (MMC_RSP(cmd->flags) == MMC_RSP_R3)
477 sc->lm_flags |= LPC_SD_FLAGS_IGNORECRC;
478
479 cmdreg |= LPC_SD_COMMAND_ENABLE;
480 cmdreg |= (cmd->opcode & LPC_SD_COMMAND_CMDINDEXMASK);
481
482 lpc_mmc_write_4(sc, LPC_SD_MASK0, 0xffffffff);
483 lpc_mmc_write_4(sc, LPC_SD_MASK1, 0xffffffff);
484 lpc_mmc_write_4(sc, LPC_SD_ARGUMENT, cmd->arg);
485 lpc_mmc_write_4(sc, LPC_SD_COMMAND, cmdreg);
486 }
487
488 static void
lpc_mmc_setup_xfer(struct lpc_mmc_softc * sc,struct mmc_data * data)489 lpc_mmc_setup_xfer(struct lpc_mmc_softc *sc, struct mmc_data *data)
490 {
491 uint32_t datactrl = 0;
492 int data_words = data->len / 4;
493
494 sc->lm_data = data;
495 sc->lm_xfer_done = 0;
496
497 debugf("data: %p, len: %d, %s\n", data,
498 data->len, (data->flags & MMC_DATA_READ) ? "read" : "write");
499
500 if (data->flags & MMC_DATA_READ) {
501 sc->lm_xfer_direction = DIRECTION_READ;
502 lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_READ,
503 LPC_SD_PHYS_BASE + LPC_SD_FIFO, sc->lm_buffer_phys,
504 data_words, 0);
505 }
506
507 if (data->flags & MMC_DATA_WRITE) {
508 sc->lm_xfer_direction = DIRECTION_WRITE;
509 lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_WRITE,
510 sc->lm_buffer_phys, LPC_SD_PHYS_BASE + LPC_SD_FIFO,
511 data_words, 0);
512 }
513
514 datactrl |= (sc->lm_xfer_direction
515 ? LPC_SD_DATACTRL_WRITE
516 : LPC_SD_DATACTRL_READ);
517
518 datactrl |= LPC_SD_DATACTRL_DMAENABLE | LPC_SD_DATACTRL_ENABLE;
519 datactrl |= (ffs(data->len) - 1) << 4;
520
521 debugf("datactrl: 0x%08x\n", datactrl);
522
523 lpc_mmc_write_4(sc, LPC_SD_DATATIMER, 0xFFFF0000);
524 lpc_mmc_write_4(sc, LPC_SD_DATALENGTH, data->len);
525 lpc_mmc_write_4(sc, LPC_SD_DATACTRL, datactrl);
526 }
527
528 static int
lpc_mmc_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)529 lpc_mmc_read_ivar(device_t bus, device_t child, int which,
530 uintptr_t *result)
531 {
532 struct lpc_mmc_softc *sc = device_get_softc(bus);
533
534 switch (which) {
535 default:
536 return (EINVAL);
537 case MMCBR_IVAR_BUS_MODE:
538 *(int *)result = sc->lm_host.ios.bus_mode;
539 break;
540 case MMCBR_IVAR_BUS_WIDTH:
541 *(int *)result = sc->lm_host.ios.bus_width;
542 break;
543 case MMCBR_IVAR_CHIP_SELECT:
544 *(int *)result = sc->lm_host.ios.chip_select;
545 break;
546 case MMCBR_IVAR_CLOCK:
547 *(int *)result = sc->lm_host.ios.clock;
548 break;
549 case MMCBR_IVAR_F_MIN:
550 *(int *)result = sc->lm_host.f_min;
551 break;
552 case MMCBR_IVAR_F_MAX:
553 *(int *)result = sc->lm_host.f_max;
554 break;
555 case MMCBR_IVAR_HOST_OCR:
556 *(int *)result = sc->lm_host.host_ocr;
557 break;
558 case MMCBR_IVAR_MODE:
559 *(int *)result = sc->lm_host.mode;
560 break;
561 case MMCBR_IVAR_OCR:
562 *(int *)result = sc->lm_host.ocr;
563 break;
564 case MMCBR_IVAR_POWER_MODE:
565 *(int *)result = sc->lm_host.ios.power_mode;
566 break;
567 case MMCBR_IVAR_VDD:
568 *(int *)result = sc->lm_host.ios.vdd;
569 break;
570 case MMCBR_IVAR_CAPS:
571 *(int *)result = sc->lm_host.caps;
572 break;
573 case MMCBR_IVAR_MAX_DATA:
574 *(int *)result = 1;
575 break;
576 }
577
578 return (0);
579 }
580
581 static int
lpc_mmc_write_ivar(device_t bus,device_t child,int which,uintptr_t value)582 lpc_mmc_write_ivar(device_t bus, device_t child, int which,
583 uintptr_t value)
584 {
585 struct lpc_mmc_softc *sc = device_get_softc(bus);
586
587 switch (which) {
588 default:
589 return (EINVAL);
590 case MMCBR_IVAR_BUS_MODE:
591 sc->lm_host.ios.bus_mode = value;
592 break;
593 case MMCBR_IVAR_BUS_WIDTH:
594 sc->lm_host.ios.bus_width = value;
595 break;
596 case MMCBR_IVAR_CHIP_SELECT:
597 sc->lm_host.ios.chip_select = value;
598 break;
599 case MMCBR_IVAR_CLOCK:
600 sc->lm_host.ios.clock = value;
601 break;
602 case MMCBR_IVAR_MODE:
603 sc->lm_host.mode = value;
604 break;
605 case MMCBR_IVAR_OCR:
606 sc->lm_host.ocr = value;
607 break;
608 case MMCBR_IVAR_POWER_MODE:
609 sc->lm_host.ios.power_mode = value;
610 break;
611 case MMCBR_IVAR_VDD:
612 sc->lm_host.ios.vdd = value;
613 break;
614 /* These are read-only */
615 case MMCBR_IVAR_CAPS:
616 case MMCBR_IVAR_HOST_OCR:
617 case MMCBR_IVAR_F_MIN:
618 case MMCBR_IVAR_F_MAX:
619 case MMCBR_IVAR_MAX_DATA:
620 return (EINVAL);
621 }
622 return (0);
623 }
624
625 static int
lpc_mmc_update_ios(device_t bus,device_t child)626 lpc_mmc_update_ios(device_t bus, device_t child)
627 {
628 struct lpc_mmc_softc *sc = device_get_softc(bus);
629 struct mmc_ios *ios = &sc->lm_host.ios;
630 uint32_t clkdiv = 0, pwr = 0;
631
632 if (ios->bus_width == bus_width_4)
633 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
634
635 /* Calculate clock divider */
636 clkdiv = (LPC_SD_CLK / (2 * ios->clock)) - 1;
637
638 /* Clock rate should not exceed rate requested in ios */
639 if ((LPC_SD_CLK / (2 * (clkdiv + 1))) > ios->clock)
640 clkdiv++;
641
642 debugf("clock: %dHz, clkdiv: %d\n", ios->clock, clkdiv);
643
644 if (ios->bus_width == bus_width_4) {
645 debugf("using wide bus mode\n");
646 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
647 }
648
649 lpc_mmc_write_4(sc, LPC_SD_CLOCK, clkdiv | LPC_SD_CLOCK_ENABLE);
650
651 switch (ios->power_mode) {
652 case power_off:
653 pwr |= LPC_SD_POWER_CTRL_OFF;
654 break;
655 case power_up:
656 pwr |= LPC_SD_POWER_CTRL_UP;
657 break;
658 case power_on:
659 pwr |= LPC_SD_POWER_CTRL_ON;
660 break;
661 }
662
663 if (ios->bus_mode == opendrain)
664 pwr |= LPC_SD_POWER_OPENDRAIN;
665
666 lpc_mmc_write_4(sc, LPC_SD_POWER, pwr);
667
668 return (0);
669 }
670
671 static int
lpc_mmc_get_ro(device_t bus,device_t child)672 lpc_mmc_get_ro(device_t bus, device_t child)
673 {
674
675 return (0);
676 }
677
678 static int
lpc_mmc_acquire_host(device_t bus,device_t child)679 lpc_mmc_acquire_host(device_t bus, device_t child)
680 {
681 struct lpc_mmc_softc *sc = device_get_softc(bus);
682 int error = 0;
683
684 lpc_mmc_lock(sc);
685 while (sc->lm_bus_busy)
686 error = mtx_sleep(sc, &sc->lm_mtx, PZERO, "mmcah", 0);
687
688 sc->lm_bus_busy++;
689 lpc_mmc_unlock(sc);
690 return (error);
691 }
692
693 static int
lpc_mmc_release_host(device_t bus,device_t child)694 lpc_mmc_release_host(device_t bus, device_t child)
695 {
696 struct lpc_mmc_softc *sc = device_get_softc(bus);
697
698 lpc_mmc_lock(sc);
699 sc->lm_bus_busy--;
700 wakeup(sc);
701 lpc_mmc_unlock(sc);
702 return (0);
703 }
704
lpc_mmc_dma_rxfinish(void * arg)705 static void lpc_mmc_dma_rxfinish(void *arg)
706 {
707 }
708
lpc_mmc_dma_rxerror(void * arg)709 static void lpc_mmc_dma_rxerror(void *arg)
710 {
711 struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
712 device_printf(sc->lm_dev, "DMA RX error\n");
713 }
714
lpc_mmc_dma_txfinish(void * arg)715 static void lpc_mmc_dma_txfinish(void *arg)
716 {
717 }
718
lpc_mmc_dma_txerror(void * arg)719 static void lpc_mmc_dma_txerror(void *arg)
720 {
721 struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
722 device_printf(sc->lm_dev, "DMA TX error\n");
723 }
724
725 static void
lpc_mmc_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int err)726 lpc_mmc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
727 {
728 struct lpc_mmc_dmamap_arg *ctx;
729
730 if (err)
731 return;
732
733 ctx = (struct lpc_mmc_dmamap_arg *)arg;
734 ctx->lm_dma_busaddr = segs[0].ds_addr;
735 }
736
737 static device_method_t lpc_mmc_methods[] = {
738 /* Device interface */
739 DEVMETHOD(device_probe, lpc_mmc_probe),
740 DEVMETHOD(device_attach, lpc_mmc_attach),
741 DEVMETHOD(device_detach, lpc_mmc_detach),
742
743 /* Bus interface */
744 DEVMETHOD(bus_read_ivar, lpc_mmc_read_ivar),
745 DEVMETHOD(bus_write_ivar, lpc_mmc_write_ivar),
746
747 /* MMC bridge interface */
748 DEVMETHOD(mmcbr_update_ios, lpc_mmc_update_ios),
749 DEVMETHOD(mmcbr_request, lpc_mmc_request),
750 DEVMETHOD(mmcbr_get_ro, lpc_mmc_get_ro),
751 DEVMETHOD(mmcbr_acquire_host, lpc_mmc_acquire_host),
752 DEVMETHOD(mmcbr_release_host, lpc_mmc_release_host),
753
754 DEVMETHOD_END
755 };
756
757 static devclass_t lpc_mmc_devclass;
758
759 static driver_t lpc_mmc_driver = {
760 "lpcmmc",
761 lpc_mmc_methods,
762 sizeof(struct lpc_mmc_softc),
763 };
764
765 DRIVER_MODULE(lpcmmc, simplebus, lpc_mmc_driver, lpc_mmc_devclass, NULL, NULL);
766 MMC_DECLARE_BRIDGE(lpcmmc);
767